From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) by mx.groups.io with SMTP id smtpd.web10.4297.1670618766950760250 for ; Fri, 09 Dec 2022 12:46:07 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@starlabs-systems.20210112.gappssmtp.com header.s=20210112 header.b=TQrJFOBP; spf=pass (domain: starlabs.systems, ip: 209.85.210.178, mailfrom: sean@starlabs.systems) Received: by mail-pf1-f178.google.com with SMTP id c13so4532778pfp.5 for ; Fri, 09 Dec 2022 12:46:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=starlabs-systems.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=0JI71eHKRN8+gKNIM4U28LaFbbIXSZRK2THGkNPvOBw=; b=TQrJFOBP/tr2Uqtkwx9RheDfUPFATek6YBFKVFJqGF4i5Uqy2h1X8i2/j3ZtwmlF3J +Be5rW9IZWimiwaKQ6RY+upyGQNYTROeSU4yyCDTRJkooVpoUauHsBNN5oprKtjSlVNq R1tkXtlZEXl49zAYuXvL99H9Zb/OX/ybHw2apxmnFjPbhn9Q9F+nW9/nYsjzIYeiXQyo uFyvKHbKHdfvyWcx7M37F57OPevOMK271M7vo6g5qTe9adIzumrumukbqjaEH5JaUBqL nU74e/AhMU3hGpIq8CFHPZ1NK3R8mucCNXtvfhocaT577CniaU4uIALqtqNN2RGMu9QS rAqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=0JI71eHKRN8+gKNIM4U28LaFbbIXSZRK2THGkNPvOBw=; b=4fh7mb8yAp+lOCUTrkPlIR50O7//e3cu7JcF0CUcVa+wEoJsx5BnynHKGg0t5HzseR brx9DxknAakCIhm+e/hnTzW86QXxMCgMsUJ5KjAFb9veLipGL5S+ayLeMHRv8sWaIz41 hjIGiCXi/lbHnuKQRAwqmCtrwoIy1YyNyrX55lugt67b+88BsrzfxJ4v/1KdwtnlbDO1 YklK1ykcCG7ahF8jbpzmf68J15KYxEJ1WNT/oHw0F2h7kwcqMWnelcTEhmQDoi4YYZ0l kzo+FdlgEFyKoKC67+PN85mxVSD/EuKnohZRmvPyyEMtunI9HqUHV00+VzkerkP3zlqD 0N2g== X-Gm-Message-State: ANoB5pmmyPD7KTCRHg1lRSqNqU+ICKjbF6gZcubBfDjlXmFDw29qiA5+ nda7kzNz8SgAXxnYc3pty84YjOxxxPNKIjy5tQwzWv44vS1v X-Google-Smtp-Source: AA0mqf7+IWJAkc3QO6K12YsJiEEnqzUfH9OE+pkdqMMH3cQJbKZtD+c31SHJWuiG6ZtNYrKyhbgXc5EhOWEoyUYZEsI= X-Received: by 2002:aa7:9892:0:b0:576:4aef:f1e7 with SMTP id r18-20020aa79892000000b005764aeff1e7mr30704839pfl.18.1670618765857; Fri, 09 Dec 2022 12:46:05 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: "Sean Rhodes" Date: Fri, 9 Dec 2022 20:45:54 +0000 Message-ID: Subject: Re: [edk2-devel] [PATCH 1/4] MdeModulePkg/XhciDxe/XhciReg: Handle incorrect PSIV indices To: devel@edk2.groups.io, ian.chiu@intel.com Cc: Matt DeVillier , "Wu, Hao A" , "Ni, Ray" Content-Type: multipart/alternative; boundary="000000000000182ccf05ef6b3ecb" --000000000000182ccf05ef6b3ecb Content-Type: text/plain; charset="UTF-8" Thank you :) On Thu, 8 Dec 2022 at 07:06, Chiu, Ian wrote: > Hi Sean, Matt DeVillier, > > I checked the patch 0001-0004, we are find and agree with 0002-0004. > For the patch > 0001-MdeModulePkg-XhciDxe-XhciReg-Handle-incorrect-PSIV-indices. > The case you mention below with same PSIV in USB3/USB2. > > We consider if there exist a case that actually want to go with USB3 > speed, > then will fail when data transmit. Since USB3 protocol is different than > USB2. > Otherwise we may need to fix it again, once issue coming out. > > We think about a solution to using the "Compatible Port Count" & > "Compatible Port Offset" to ensure the port is supported this protocol or > not. > Would you able to dump the xHCI Supported Protocol Capability raw data and > check if this solution works with you case. > > Attach sample code snippet and data dump from my side. > > Thanks, > Ian Chiu > > > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Sean Rhodes > Sent: Monday, December 5, 2022 5:18 PM > To: devel@edk2.groups.io > Cc: Matt DeVillier ; Wu, Hao A < > hao.a.wu@intel.com>; Ni, Ray ; Rhodes, Sean > > Subject: [edk2-devel] [PATCH 1/4] MdeModulePkg/XhciDxe/XhciReg: Handle > incorrect PSIV indices > > From: Matt DeVillier > > On some platforms, including Sky Lake and Kaby Lake, the PSIV (Protocol > Speed ID Value) indices are shared between Protocol Speed ID DWORD' in the > extended capabilities registers for both USB2 (Full Speed) and USB3 (Super > Speed). > > An example can be found below: > > XhcCheckUsbPortSpeedUsedPsic: checking for USB2 ext caps > XhciPsivGetPsid: found 3 PSID entries > XhciPsivGetPsid: looking for port speed 1 > XhciPsivGetPsid: PSIV 1 PSIE 2 PLT 0 PSIM 12 > XhciPsivGetPsid: PSIV 2 PSIE 1 PLT 0 PSIM 1500 > XhciPsivGetPsid: PSIV 3 PSIE 2 PLT 0 PSIM 480 > XhcCheckUsbPortSpeedUsedPsic: checking for USB3 ext caps > XhciPsivGetPsid: found 3 PSID entries > XhciPsivGetPsid: looking for port speed 1 > XhciPsivGetPsid: PSIV 1 PSIE 3 PLT 0 PSIM 5 > XhciPsivGetPsid: PSIV 2 PSIE 3 PLT 0 PSIM 10 > XhciPsivGetPsid: PSIV 34 PSIE 2 PLT 0 PSIM 1248 > > The result is edk2 detecting USB2 devices as USB3 devices, which > consequently causes enumeration to fail. > > To avoid incorrect detection, check the extended capability registers for > USB2 before USB3. If edk2 finds a match for a USB 2 device, don't check for > USB 3. > > Cc: Hao A Wu > Cc: Ray Ni > Reviewed-by: Sean Rhodes > Signed-off-by: Matt DeVillier > Change-Id: I5bcf32105ce85fda95b4ba98a5e420e8f522374c > --- > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 36 +++++++++++++++----------- > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h | 1 + > 2 files changed, 22 insertions(+), 15 deletions(-) > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > index 2b4a4b2444..c992323443 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > @@ -698,25 +698,11 @@ XhcCheckUsbPortSpeedUsedPsic ( > SpField.Dword = 0; UsbSpeedIdMap = 0; - //- // Check xHCI Supported > Protocol Capability, find the PSIV field to match- // PortSpeed definition > when the Major Revision is 03h.- //- if (Xhc->Usb3SupOffset != > 0xFFFFFFFF) {- SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, > PortSpeed);- if (SpField.Dword != 0) {- //- // Found the > corresponding PORTSC value in PSIV field of USB3 offset.- //- > UsbSpeedIdMap = USB_PORT_STAT_SUPER_SPEED;- }- }- // // Check xHCI > Supported Protocol Capability, find the PSIV field to match // PortSpeed > definition when the Major Revision is 02h. //- if ((UsbSpeedIdMap == 0) > && (Xhc->Usb2SupOffset != 0xFFFFFFFF)) {+ if (Xhc->Usb2SupOffset != > 0xFFFFFFFF) { SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb2SupOffset, > PortSpeed); if (SpField.Dword != 0) { //@@ -733,6 +719,12 @@ > XhcCheckUsbPortSpeedUsedPsic ( > // PSIM shows as default High-speed protocol, apply to > High-speed mapping // UsbSpeedIdMap = > USB_PORT_STAT_HIGH_SPEED;+ } else if (SpField.Data.Psim == > XHC_SUPPORTED_PROTOCOL_USB2_FULL_SPEED_PSIM) {+ //+ // > PSIM shows as default Full-speed protocol, return 0+ // to ensure > no port status set+ //+ return 0; } } else > if (SpField.Data.Psie == 1) { //@@ -750,6 +742,20 @@ > XhcCheckUsbPortSpeedUsedPsic ( > } } + //+ // Check xHCI Supported Protocol Capability, find the > PSIV field to match+ // PortSpeed definition when the Major Revision is > 03h.+ //+ if ((UsbSpeedIdMap == 0) && (Xhc->Usb3SupOffset != 0xFFFFFFFF)) > {+ SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, > PortSpeed);+ if (SpField.Dword != 0) {+ //+ // Found the > corresponding PORTSC value in PSIV field of USB3 offset.+ //+ > UsbSpeedIdMap = USB_PORT_STAT_SUPER_SPEED;+ }+ }+ return > UsbSpeedIdMap; } diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > index 5fe2ba4f0e..74ac6297ba 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h > @@ -85,6 +85,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET 0x08 #define > XHC_SUPPORTED_PROTOCOL_PSI_OFFSET 0x10 #define > XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM 480+#define > XHC_SUPPORTED_PROTOCOL_USB2_FULL_SPEED_PSIM 12 #define > XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM 1500 #pragma pack (1)-- > 2.37.2 > > > > -=-=-=-=-=-= > Groups.io Links: You receive all messages sent to this group. > View/Reply Online (#96950): https://edk2.groups.io/g/devel/message/96950 > Mute This Topic: https://groups.io/mt/95391831/5427408 > Group Owner: devel+owner@edk2.groups.io > Unsubscribe: https://edk2.groups.io/g/devel/unsub [ian.chiu@intel.com] > -=-=-=-=-=-= > > > > > > > > --000000000000182ccf05ef6b3ecb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thank you :)

On Thu, 8 Dec 2022 at 07:06, Chiu, Ian &= lt;ian.chiu@intel.com> wrote:<= br>
Hi Sean, Matt De= Villier,

I checked the patch 0001-0004, we are find and agree with 0002-0004.
For the patch 0001-MdeModulePkg-XhciDxe-XhciReg-Handle-incorrect-PSIV-indic= es.
The case you mention below with same PSIV in USB3/USB2.

We consider if there exist a case that actually want to go with USB3 speed,=
then will fail when data transmit. Since USB3 protocol is different than US= B2.
Otherwise we may need to fix it again, once issue coming out.

We think about a solution to using the "Compatible Port Count" &a= mp; "Compatible Port Offset" to ensure the port is supported this= protocol or not.
Would you able to dump the xHCI Supported Protocol Capability raw data and = check if this solution works with you case.

Attach sample code snippet and data dump from my side.

Thanks,
Ian Chiu


-----Original Message-----
From: devel@edk2.= groups.io <devel@edk2.groups.io> On Behalf Of Sean Rhodes
Sent: Monday, December 5, 2022 5:18 PM
To: devel@edk2.gr= oups.io
Cc: Matt DeVillier <matt.devillier@gmail.com>; Wu, Hao A <hao.a.wu@intel.com>; Ni, Ra= y <ray.ni@intel.co= m>; Rhodes, Sean <sean@starlabs.systems>
Subject: [edk2-devel] [PATCH 1/4] MdeModulePkg/XhciDxe/XhciReg: Handle inco= rrect PSIV indices

From: Matt DeVillier <matt.devillier@gmail.com>

On some platforms, including Sky Lake and Kaby Lake, the PSIV (Protocol Spe= ed ID Value) indices are shared between Protocol Speed ID DWORD' in the= extended capabilities registers for both USB2 (Full Speed) and USB3 (Super= Speed).

An example can be found below:

=C2=A0 =C2=A0 XhcCheckUsbPortSpeedUsedPsic: checking for USB2 ext caps
=C2=A0 =C2=A0 XhciPsivGetPsid: found 3 PSID entries
=C2=A0 =C2=A0 XhciPsivGetPsid: looking for port speed 1
=C2=A0 =C2=A0 XhciPsivGetPsid: PSIV 1 PSIE 2 PLT 0 PSIM 12
=C2=A0 =C2=A0 XhciPsivGetPsid: PSIV 2 PSIE 1 PLT 0 PSIM 1500
=C2=A0 =C2=A0 XhciPsivGetPsid: PSIV 3 PSIE 2 PLT 0 PSIM 480
=C2=A0 =C2=A0 XhcCheckUsbPortSpeedUsedPsic: checking for USB3 ext caps
=C2=A0 =C2=A0 XhciPsivGetPsid: found 3 PSID entries
=C2=A0 =C2=A0 XhciPsivGetPsid: looking for port speed 1
=C2=A0 =C2=A0 XhciPsivGetPsid: PSIV 1 PSIE 3 PLT 0 PSIM 5
=C2=A0 =C2=A0 XhciPsivGetPsid: PSIV 2 PSIE 3 PLT 0 PSIM 10
=C2=A0 =C2=A0 XhciPsivGetPsid: PSIV 34 PSIE 2 PLT 0 PSIM 1248

The result is edk2 detecting USB2 devices as USB3 devices, which consequent= ly causes enumeration to fail.

To avoid incorrect detection, check the extended capability registers for U= SB2 before USB3. If edk2 finds a match for a USB 2 device, don't check = for USB 3.

Cc: Hao A Wu <ha= o.a.wu@intel.com>
Cc: Ray Ni <ray.ni= @intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I5bcf32105ce85fda95b4ba98a5e420e8f522374c
---
=C2=A0MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 36 +++++++++++++++----------= -=C2=A0 MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h |=C2=A0 1 +
=C2=A02 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/= XhciDxe/XhciReg.c
index 2b4a4b2444..c992323443 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -698,25 +698,11 @@ XhcCheckUsbPortSpeedUsedPsic (
=C2=A0 =C2=A0SpField.Dword =3D 0;=C2=A0 =C2=A0UsbSpeedIdMap =3D 0; -=C2=A0 = //-=C2=A0 // Check xHCI Supported Protocol Capability, find the PSIV field = to match-=C2=A0 // PortSpeed definition when the Major Revision is 03h.-=C2= =A0 //-=C2=A0 if (Xhc->Usb3SupOffset !=3D 0xFFFFFFFF) {-=C2=A0 =C2=A0 Sp= Field.Dword =3D XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed);-= =C2=A0 =C2=A0 if (SpField.Dword !=3D 0) {-=C2=A0 =C2=A0 =C2=A0 //-=C2=A0 = =C2=A0 =C2=A0 // Found the corresponding PORTSC value in PSIV field of USB3= offset.-=C2=A0 =C2=A0 =C2=A0 //-=C2=A0 =C2=A0 =C2=A0 UsbSpeedIdMap =3D USB= _PORT_STAT_SUPER_SPEED;-=C2=A0 =C2=A0 }-=C2=A0 }-=C2=A0 =C2=A0//=C2=A0 =C2= =A0// Check xHCI Supported Protocol Capability, find the PSIV field to matc= h=C2=A0 =C2=A0// PortSpeed definition when the Major Revision is 02h.=C2=A0= =C2=A0//-=C2=A0 if ((UsbSpeedIdMap =3D=3D 0) && (Xhc->Usb2SupOf= fset !=3D 0xFFFFFFFF)) {+=C2=A0 if (Xhc->Usb2SupOffset !=3D 0xFFFFFFFF) = {=C2=A0 =C2=A0 =C2=A0SpField.Dword =3D XhciPsivGetPsid (Xhc, Xhc->Usb2Su= pOffset, PortSpeed);=C2=A0 =C2=A0 =C2=A0if (SpField.Dword !=3D 0) {=C2=A0 = =C2=A0 =C2=A0 =C2=A0//@@ -733,6 +719,12 @@ XhcCheckUsbPortSpeedUsedPsic ( =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0// PSIM shows as default High-spee= d protocol, apply to High-speed mapping=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0//=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0UsbSpeedIdMap =3D USB_PORT= _STAT_HIGH_SPEED;+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (SpField.Data.Psim = =3D=3D XHC_SUPPORTED_PROTOCOL_USB2_FULL_SPEED_PSIM) {+=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 //+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 // PSIM shows as defaul= t Full-speed protocol, return 0+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 // to en= sure no port status set+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 //+=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 return 0;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}=C2=A0 = =C2=A0 =C2=A0 =C2=A0} else if (SpField.Data.Psie =3D=3D 1) {=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0//@@ -750,6 +742,20 @@ XhcCheckUsbPortSpeedUsedPsic ( =C2=A0 =C2=A0 =C2=A0}=C2=A0 =C2=A0} +=C2=A0 //+=C2=A0 // Check xHCI Support= ed Protocol Capability, find the PSIV field to match+=C2=A0 // PortSpeed de= finition when the Major Revision is 03h.+=C2=A0 //+=C2=A0 if ((UsbSpeedIdMa= p =3D=3D 0) && (Xhc->Usb3SupOffset !=3D 0xFFFFFFFF)) {+=C2=A0 = =C2=A0 SpField.Dword =3D XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortS= peed);+=C2=A0 =C2=A0 if (SpField.Dword !=3D 0) {+=C2=A0 =C2=A0 =C2=A0 //+= =C2=A0 =C2=A0 =C2=A0 // Found the corresponding PORTSC value in PSIV field = of USB3 offset.+=C2=A0 =C2=A0 =C2=A0 //+=C2=A0 =C2=A0 =C2=A0 UsbSpeedIdMap = =3D USB_PORT_STAT_SUPER_SPEED;+=C2=A0 =C2=A0 }+=C2=A0 }+=C2=A0 =C2=A0return= UsbSpeedIdMap; } diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h b/Mde= ModulePkg/Bus/Pci/XhciDxe/XhciReg.h
index 5fe2ba4f0e..74ac6297ba 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h
@@ -85,6 +85,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
=C2=A0#define XHC_SUPPORTED_PROTOCOL_DW2_OFFSET=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A00x08 #define XHC_SUPPORTED_PROTOCOL_PSI_OFFSET= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x10 #define XHC_SUP= PORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM=C2=A0 =C2=A0 =C2=A0480+#define XHC_SUP= PORTED_PROTOCOL_USB2_FULL_SPEED_PSIM=C2=A0 =C2=A0 =C2=A012 #define XHC_SUPP= ORTED_PROTOCOL_USB2_LOW_SPEED_PSIM=C2=A0 =C2=A0 =C2=A0 1500=C2=A0 #pragma p= ack (1)--
2.37.2



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