From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-yb1-f177.google.com (mail-yb1-f177.google.com [209.85.219.177]) by mx.groups.io with SMTP id smtpd.web09.1712.1648664992623185805 for ; Wed, 30 Mar 2022 11:29:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@starlabs-systems.20210112.gappssmtp.com header.s=20210112 header.b=mVwxHwF8; spf=pass (domain: starlabs.systems, ip: 209.85.219.177, mailfrom: sean@starlabs.systems) Received: by mail-yb1-f177.google.com with SMTP id y142so38200353ybe.11 for ; Wed, 30 Mar 2022 11:29:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=starlabs-systems.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=fGuOrlMRkB0a0ksDlpV5trF8lPp9QMxJMWdU98Go+RQ=; b=mVwxHwF8ZNAlB/oxli7Js7JTuB17aIME+DI5GfJQBqwVYwgv9re6ABacULJxIDJRKy Mj9dYuvjqNAXZ7XZmkuqoMFELFDv3r77APPQ2xvf0+kL3efga0Ej2JECJ1+UWUh6UveI 9dSgAoBENkk8z5h0v5ifGoy2fzL7DMd64tO93oUkoEQ2bpDcWdbbroRUyvKxDbfSlKo2 wT6BsPwPJ8FaYX235mJxdfely11NfSIAK+3H7XpWS3MQLj95my5UBaJLBnc3Yp5tGWZf gfMsevjChXPP+IZ6qNw9xfouI1SwLbFylre7gR6S36Kl3HMM1DkBWM1cGmJWWcc1npmp i/YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fGuOrlMRkB0a0ksDlpV5trF8lPp9QMxJMWdU98Go+RQ=; b=ejeCgTx/4CwFRDMBAI0Fb08EOzKknYbZA6XfmGwqbrRlABib46yI8gMXeBzwS+mZ2w K5Ti9YVZSM2EZoS6djguPC7htPUdtnZ05fj+n4XCrmaTSAERgYbj9Wu1SwKl1TQQhHWc /LZbukRO6vN64VDMfce5xJqEkZulkTfo9ei7DAcu/DHK2r4QB8zfCxNbN1qzy9REt1iI CFmQjog8ugiiVN1z4Hh7FH2F1tjMuLGoI252PHvh3G0gFwLkFpV/gDp0P4FsP5JKy/a+ XFk2PmRQJIGvhLMKtnNeiAG3xC/rh9Q5DpEGjyMXCMso1plfBtx2/9Vwy9k4WpTfxbbV OsCA== X-Gm-Message-State: AOAM533O/hWhjiNolv88mahFIkAMz3SooPT6gEOciyfG/XsAyi+qA4/u TJlX5dv63zK/RsdqG1Amt6xiy1jtNCI7RBaSoaYF0loMgw== X-Google-Smtp-Source: ABdhPJy2xRql9ujw/EfAxb3Mj2zLqBPiMekRXwz0iHvtoIsTTlbWQa/axcAwUsV+pvvwBxxUv45TPtjP++mWXbwThRQ= X-Received: by 2002:a05:6902:34a:b0:633:9def:fe20 with SMTP id e10-20020a056902034a00b006339deffe20mr963593ybs.468.1648664991503; Wed, 30 Mar 2022 11:29:51 -0700 (PDT) MIME-Version: 1.0 References: <5b99fc3587bec6bd7552ec8aeda76501f1a7b935.1648664943.git.sean@starlabs.systems> In-Reply-To: <5b99fc3587bec6bd7552ec8aeda76501f1a7b935.1648664943.git.sean@starlabs.systems> From: "Sean Rhodes" Date: Wed, 30 Mar 2022 19:29:40 +0100 Message-ID: Subject: Re: [PATCH 1/2] UefiPayloadPkg: Fix PciHostBridgeLib To: devel@edk2.groups.io Cc: Lean Sheng Tan , Guo Dong , Ray Ni , Maurice Ma , Benjamin You , Patrick Rudolph Content-Type: multipart/alternative; boundary="0000000000002c28f505db73bb45" --0000000000002c28f505db73bb45 Content-Type: text/plain; charset="UTF-8" Reviewed-by Sean Rhodes On Wed, 30 Mar 2022 at 19:29, Sean Rhodes wrote: > From: Lean Sheng Tan > > Don't assume a 64bit register always holds an address greater than 4GB. > Check the value in the register and decide which Aperature it should be > assigned to. > > Fixes assertion > "ASSERT [PciHostBridgeDxe] Bridge->MemAbove4G.Base >= > 0x0000000100000000ULL". > > Tested with coreboot as bootloader on platforms that have PCI resource > above 4GiB and on platforms that don't have resource above 4GiB. > > Cc: Guo Dong > Cc: Ray Ni > Cc: Maurice Ma > Cc: Benjamin You > Cc: Sean Rhodes > Signed-off-by: Patrick Rudolph > --- > .../Library/PciHostBridgeLib/PciHostBridgeSupport.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git > a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > index 8a890b6b53..e1faa24ae7 100644 > --- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > +++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > @@ -354,14 +354,19 @@ ScanForRootBridges ( > Base = ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << > 16; > Limit = (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0) > << 16) | 0xfffff; > - MemAperture = &Mem; > + > if (Value == BIT0) { > - Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, > 32); > - Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, > 32); > - MemAperture = &MemAbove4G; > + Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32); > + Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32); > } > > if ((Base > 0) && (Base < Limit)) { > + if (Base < BASE_4GB) { > + MemAperture = &Mem; > + } else { > + MemAperture = &MemAbove4G; > + } > + > if (MemAperture->Base > Base) { > MemAperture->Base = Base; > } > -- > 2.32.0 > > --0000000000002c28f505db73bb45 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Reviewed-by Sean Rhodes <sean@starlabs.systems>

On Wed, 30 Mar 2022 at 19:29, Sean Rhodes <sean@starlabs.systems> wr= ote:
From: Lean = Sheng Tan <= sheng.tan@9elements.com>

Don't assume a 64bit register always holds an address greater than 4GB.=
Check the value in the register and decide which Aperature it should be
assigned to.

Fixes assertion
"ASSERT [PciHostBridgeDxe] Bridge->MemAbove4G.Base >=3D 0x000000= 0100000000ULL".

Tested with coreboot as bootloader on platforms that have PCI resource
above 4GiB and on platforms that don't have resource above 4GiB.

Cc: Guo Dong <gu= o.dong@intel.com>
Cc: Ray Ni <ray.ni= @intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
---
=C2=A0.../Library/PciHostBridgeLib/PciHostBridgeSupport.c | 13 +++++++++---= -
=C2=A01 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c= b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 8a890b6b53..e1faa24ae7 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -354,14 +354,19 @@ ScanForRootBridges (
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Base=C2=A0 =3D ((UINT32)Pci.Bridge= .PrefetchableMemoryBase & 0xfff0) << 16;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Limit =3D (((UINT32)Pci.Bridge.Pre= fetchableMemoryLimit & 0xfff0)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 <&= lt; 16) | 0xfffff;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MemAperture =3D &Mem;
+
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (Value =3D=3D BIT0) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Base=C2=A0 =C2=A0 =C2=A0 =C2=A0|= =3D LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Limit=C2=A0 =C2=A0 =C2=A0 |=3D L= ShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MemAperture =3D &MemAbove4G;=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Base=C2=A0 |=3D LShiftU64 (Pci.B= ridge.PrefetchableBaseUpper32, 32);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Limit |=3D LShiftU64 (Pci.Bridge= .PrefetchableLimitUpper32, 32);
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}

=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if ((Base > 0) && (Base= < Limit)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (Base < BASE_4GB) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MemAperture =3D &Mem;=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MemAperture =3D &MemA= bove4G;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (MemAperture->Base &g= t; Base) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0MemAperture->Base= =3D Base;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
--
2.32.0

--0000000000002c28f505db73bb45--