From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ed1-f42.google.com (mail-ed1-f42.google.com [209.85.208.42]) by mx.groups.io with SMTP id smtpd.web11.91627.1675794618190158868 for ; Tue, 07 Feb 2023 10:30:18 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@starlabs-systems.20210112.gappssmtp.com header.s=20210112 header.b=tzCAXEtH; spf=pass (domain: starlabs.systems, ip: 209.85.208.42, mailfrom: sean@starlabs.systems) Received: by mail-ed1-f42.google.com with SMTP id v10so17239960edi.8 for ; Tue, 07 Feb 2023 10:30:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=starlabs-systems.20210112.gappssmtp.com; s=20210112; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :from:to:cc:subject:date:message-id:reply-to; bh=CmvKhIkFcKIUOrzeRqsLjaEyGZQYnggRdqwck8HFtUY=; b=tzCAXEtHJCe+k7jCty/gWhb8AagSM1cOWPony52RFYABakDFJDQ4efEaMBnbh8MdL4 nlrsQo8UTlVIgiYuyXz/demOEvOG8DeDbVjuctLOeGSlr6BWc5+2r4EozAIjQorm+XIY pIATeCWazEqwBMPtCLVBBiPXVlgWZYutcjBStaphFkcI8DOpqc7PFJqVPnczMEyiZxSY 8K7ji/OVYvDEXv8MOQNkVCmucAeBrj1X9jtPYI4Sizb/u4/kt0qHNzUghwJfYVUYkgrc vpG68fjtbng0IAU2vdVnfUuJNY2qQd9GdzZbFgGVBUc88CBIsx2sTJmlPlBVeWwWo0+j 6Iqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=to:subject:message-id:date:from:in-reply-to:references:mime-version :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=CmvKhIkFcKIUOrzeRqsLjaEyGZQYnggRdqwck8HFtUY=; b=NkczetNBHURPhMGvJNf6nMxVRG2JnagfdSPFi46VmcxbjfqCDukX9u4g1w6KyD9tDv hzPdz5EPnPO/heKfTqsdf24lmgOKXUo32faLA4GtjjboxVhsdygnwlEtNxW+7pJkv8iL 4wo9MJOYw7Vhwwqr1Y/rFmkAXbViIPd0OIjO2YX1pwiRsFaPyxkL3FlM2BHOL2PyRL+0 nXj86uR9wB3EAi4z/HOJ6+h75mCIbbZ+/w+yGYZOEbmobX0mYp/PF95n2NA1WRu+YyIF EsJMg8r71cAam9ygqPjBQa847x/W+CsPC3+B0N2nk95AP2pPWN1nZovTzPhMLApGwYxz fGMg== X-Gm-Message-State: AO0yUKVn+hgqj8NMovzUUKHQKdXoKUtG0uCO3U6YLY8o3gadqo/GjWS3 iBtMgxEJ++3TrkGOnr4kHZ7xkTtnv+OaPlGJk/aP1Fgy6wpG X-Google-Smtp-Source: AK7set+q8AssDrCEb9VigP2rQwbfj2Q2+gP3RXdIhV5HxT55E1BoD56/DS08Zr6R9dcFTjOMVKIGmSidBLONOReQgzs= X-Received: by 2002:a50:9ec3:0:b0:4aa:a757:324d with SMTP id a61-20020a509ec3000000b004aaa757324dmr911580edf.6.1675794615584; Tue, 07 Feb 2023 10:30:15 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: "Sean Rhodes" Date: Tue, 7 Feb 2023 18:30:03 +0000 Message-ID: Subject: Re: [edk2-devel] regarding uefipayload build warning for pcd To: devel@edk2.groups.io, ritul.bits@gmail.com Content-Type: multipart/alternative; boundary="000000000000c75b3405f420569a" --000000000000c75b3405f420569a Content-Type: text/plain; charset="UTF-8" Hi Ritul It might be easier to build it inside coreboot; that'll use coreboots tool chain and Kconfig so everything will just work. I.e. CONFIG_PAYLOAD_EDK2=y Sean On Tue, 7 Feb 2023, 18:24 ritul guru, wrote: > UefiPayloadPkg/UefiPayloadPkg.fdf > DEFINE FD_BASE = 0x00800000 > > Is the above address correct in uefipaylaod? > As observing some regions are getting out of limit of FD limit, > > and when setting DEFINE FD_BASE = 0x02200000, then seeing assert in > [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]. > > > > > > > *Thanks & RegardsRitul Guru+91-9916513186* > > > On Tue, Feb 7, 2023 at 8:29 PM ritul guru wrote: > >> Hi, >> I am building edk2 payload and getting below warning for >> PcdRtcIndexRegister, >> and if try to boot to then observing that there is assert at: >> >> ASSERT_EFI_ERROR (Status = Device Error) >> >> DXE_ASSERT!: >> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c >> (141): !EFI_ERROR (Status) >> >> >> >> >> build time warning: >> Active Platform = >> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc >> .build: : warning: The PCD was not specified by any INF module in the >> platform for the given architecture. >> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister] >> Platform: [UefiPayloadPkg.dsc] >> Arch: ['IA32'] >> build: : warning: The PCD was not specified by any INF module in the >> platform for the given architecture. >> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister] >> Platform: [UefiPayloadPkg.dsc] >> Arch: ['IA32'] >> . done! >> >> >> >> >> *Thanks & RegardsRitul Guru+91-9916513186* >> > > --000000000000c75b3405f420569a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Ritul

It = might be easier to build it inside coreboot; that'll use coreboots tool= chain and Kconfig so everything will just work.
I.e. CONFIG_PAYLOAD_EDK2=3Dy

Sean

On Tue, 7 Feb 2023, 18:24 ritul gur= u, <ritul.bits@gmail.com>= wrote:
UefiPayloadPkg/UefiPayloadPkg.fdf
DEFINE FD_BASE =C2=A0 =C2=A0 =C2=A0 =3D 0x00800000

Is the a= bove=C2=A0address correct in uefipaylaod?
As = observing=C2=A0some regions are getting out of limit of FD limit,

and when setting DE= FINE FD_BASE =C2=A0 =C2=A0 =C2=A0 =3D 0x02200000, then seeing assert in=C2= =A0
[gPcAtChipsetPkgTokenSpaceGuid.PcdRtcInde= xRegister].




Thanks & Regards
Ritul Guru
+91-9916513186


On Tue, Feb 7, = 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
Hi,
I am buildi= ng edk2 payload and getting below warning for PcdRtcIndexRegister,
and if try to boot to then observing that there = is assert at:

ASSERT_EFI_ERROR (Status =3D Device Erro= r)

DXE_ASSERT!: /home/amd/src///coreboot/payloads/external/tianocore/= tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c (141): !E= FI_ERROR (Status)


<= div class=3D"gmail_default" style=3D"font-family:verdana,sans-serif;font-si= ze:small;color:rgb(0,0,153)">

=

build time warning:
Active Platform =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D /home//src///coreboot/payloads/external/= edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
.build: : war= ning: The PCD was not specified by any INF module in the platform for the g= iven architecture.
=C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD: [gPcAtChipsetPkgToke= nSpaceGuid.PcdRtcIndexRegister]
=C2=A0 =C2=A0 =C2=A0 =C2=A0 Platform: [U= efiPayloadPkg.dsc]
=C2=A0 =C2=A0 =C2=A0 =C2=A0 Arch: ['IA32']build: : warning: The PCD was not specified by any INF module in the platf= orm for the given architecture.
=C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD: [gPcAtC= hipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
=C2=A0 =C2=A0 =C2=A0 =C2= =A0 Platform: [UefiPayloadPkg.dsc]
=C2=A0 =C2=A0 =C2=A0 =C2=A0 Arch: [&#= 39;IA32']
. done!

<= div class=3D"gmail_default" style=3D"font-family:verdana,sans-serif;font-si= ze:small;color:rgb(0,0,153)">
Thanks & Regards
Ritul Guru
+91-9916513186

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