* regarding uefipayload build warning for pcd
@ 2023-02-07 14:59 ritul guru
2023-02-07 16:39 ` ritul guru
0 siblings, 1 reply; 14+ messages in thread
From: ritul guru @ 2023-02-07 14:59 UTC (permalink / raw)
To: edk2-devel-groups-io
[-- Attachment #1: Type: text/plain, Size: 1019 bytes --]
Hi,
I am building edk2 payload and getting below warning for
PcdRtcIndexRegister,
and if try to boot to then observing that there is assert at:
ASSERT_EFI_ERROR (Status = Device Error)
DXE_ASSERT!:
/home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
(141): !EFI_ERROR (Status)
build time warning:
Active Platform =
/home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
.build: : warning: The PCD was not specified by any INF module in the
platform for the given architecture.
PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
Platform: [UefiPayloadPkg.dsc]
Arch: ['IA32']
build: : warning: The PCD was not specified by any INF module in the
platform for the given architecture.
PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
Platform: [UefiPayloadPkg.dsc]
Arch: ['IA32']
. done!
*Thanks & RegardsRitul Guru+91-9916513186*
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* Re: regarding uefipayload build warning for pcd
2023-02-07 14:59 regarding uefipayload build warning for pcd ritul guru
@ 2023-02-07 16:39 ` ritul guru
2023-02-07 18:27 ` ritul guru
2023-02-07 18:30 ` Sean Rhodes
0 siblings, 2 replies; 14+ messages in thread
From: ritul guru @ 2023-02-07 16:39 UTC (permalink / raw)
To: edk2-devel-groups-io
[-- Attachment #1: Type: text/plain, Size: 1507 bytes --]
UefiPayloadPkg/UefiPayloadPkg.fdf
DEFINE FD_BASE = 0x00800000
Is the above address correct in uefipaylaod?
As observing some regions are getting out of limit of FD limit,
and when setting DEFINE FD_BASE = 0x02200000, then seeing assert in
[gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
*Thanks & RegardsRitul Guru+91-9916513186*
On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
> Hi,
> I am building edk2 payload and getting below warning for
> PcdRtcIndexRegister,
> and if try to boot to then observing that there is assert at:
>
> ASSERT_EFI_ERROR (Status = Device Error)
>
> DXE_ASSERT!:
> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
> (141): !EFI_ERROR (Status)
>
>
>
>
> build time warning:
> Active Platform =
> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
> .build: : warning: The PCD was not specified by any INF module in the
> platform for the given architecture.
> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
> Platform: [UefiPayloadPkg.dsc]
> Arch: ['IA32']
> build: : warning: The PCD was not specified by any INF module in the
> platform for the given architecture.
> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
> Platform: [UefiPayloadPkg.dsc]
> Arch: ['IA32']
> . done!
>
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: regarding uefipayload build warning for pcd
2023-02-07 16:39 ` ritul guru
@ 2023-02-07 18:27 ` ritul guru
2023-02-07 20:35 ` [edk2-devel] " Sean Rhodes
2023-02-07 18:30 ` Sean Rhodes
1 sibling, 1 reply; 14+ messages in thread
From: ritul guru @ 2023-02-07 18:27 UTC (permalink / raw)
To: edk2-devel-groups-io
[-- Attachment #1: Type: text/plain, Size: 2819 bytes --]
Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
ProtectUefiImageCommon - 0x51A3E1C0
- 0x0000000051DD1000 - 0x0000000000008000
SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
(0x0000000000004008)
SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
(0x0000000000020008)
SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
(0x0000000000004008)
PROGRESS CODE: V03040002 I0
ASSERT_EFI_ERROR (Status = Device Error)
*ASSERT [PcRtc]
/home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
getting above assert after changed to FD_BASE to below value,
This error is coming while booting to coreboot with edk2 payload:
UefiPayloadPkg/UefiPayloadPkg.fdf
DEFINE FD_BASE = 0x02182000
need to change FD_BASE, as it was going outside Available memory.
any hint would be appreciated.
*Thanks & RegardsRitul Guru+91-9916513186*
On Tue, Feb 7, 2023 at 10:09 PM ritul guru <ritul.bits@gmail.com> wrote:
> UefiPayloadPkg/UefiPayloadPkg.fdf
> DEFINE FD_BASE = 0x00800000
>
> Is the above address correct in uefipaylaod?
> As observing some regions are getting out of limit of FD limit,
>
> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert in
> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>
>
>
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
>
> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
>
>> Hi,
>> I am building edk2 payload and getting below warning for
>> PcdRtcIndexRegister,
>> and if try to boot to then observing that there is assert at:
>>
>> ASSERT_EFI_ERROR (Status = Device Error)
>>
>> DXE_ASSERT!:
>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>> (141): !EFI_ERROR (Status)
>>
>>
>>
>>
>> build time warning:
>> Active Platform =
>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>> .build: : warning: The PCD was not specified by any INF module in the
>> platform for the given architecture.
>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>> Platform: [UefiPayloadPkg.dsc]
>> Arch: ['IA32']
>> build: : warning: The PCD was not specified by any INF module in the
>> platform for the given architecture.
>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>> Platform: [UefiPayloadPkg.dsc]
>> Arch: ['IA32']
>> . done!
>>
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 16:39 ` ritul guru
2023-02-07 18:27 ` ritul guru
@ 2023-02-07 18:30 ` Sean Rhodes
2023-02-07 19:01 ` ritul guru
1 sibling, 1 reply; 14+ messages in thread
From: Sean Rhodes @ 2023-02-07 18:30 UTC (permalink / raw)
To: devel, ritul.bits
[-- Attachment #1: Type: text/plain, Size: 1810 bytes --]
Hi Ritul
It might be easier to build it inside coreboot; that'll use coreboots tool
chain and Kconfig so everything will just work.
I.e. CONFIG_PAYLOAD_EDK2=y
Sean
On Tue, 7 Feb 2023, 18:24 ritul guru, <ritul.bits@gmail.com> wrote:
> UefiPayloadPkg/UefiPayloadPkg.fdf
> DEFINE FD_BASE = 0x00800000
>
> Is the above address correct in uefipaylaod?
> As observing some regions are getting out of limit of FD limit,
>
> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert in
> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>
>
>
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
>
> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
>
>> Hi,
>> I am building edk2 payload and getting below warning for
>> PcdRtcIndexRegister,
>> and if try to boot to then observing that there is assert at:
>>
>> ASSERT_EFI_ERROR (Status = Device Error)
>>
>> DXE_ASSERT!:
>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>> (141): !EFI_ERROR (Status)
>>
>>
>>
>>
>> build time warning:
>> Active Platform =
>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>> .build: : warning: The PCD was not specified by any INF module in the
>> platform for the given architecture.
>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>> Platform: [UefiPayloadPkg.dsc]
>> Arch: ['IA32']
>> build: : warning: The PCD was not specified by any INF module in the
>> platform for the given architecture.
>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>> Platform: [UefiPayloadPkg.dsc]
>> Arch: ['IA32']
>> . done!
>>
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>
>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 18:30 ` Sean Rhodes
@ 2023-02-07 19:01 ` ritul guru
2023-02-07 19:02 ` ritul guru
0 siblings, 1 reply; 14+ messages in thread
From: ritul guru @ 2023-02-07 19:01 UTC (permalink / raw)
To: Sean Rhodes; +Cc: devel
[-- Attachment #1: Type: text/plain, Size: 2043 bytes --]
building it inside coreboot only.
*Thanks & RegardsRitul Guru+91-9916513186*
On Wed, Feb 8, 2023 at 12:00 AM Sean Rhodes <sean@starlabs.systems> wrote:
> Hi Ritul
>
> It might be easier to build it inside coreboot; that'll use coreboots tool
> chain and Kconfig so everything will just work.
>
> I.e. CONFIG_PAYLOAD_EDK2=y
>
> Sean
>
> On Tue, 7 Feb 2023, 18:24 ritul guru, <ritul.bits@gmail.com> wrote:
>
>> UefiPayloadPkg/UefiPayloadPkg.fdf
>> DEFINE FD_BASE = 0x00800000
>>
>> Is the above address correct in uefipaylaod?
>> As observing some regions are getting out of limit of FD limit,
>>
>> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert in
>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>
>>
>>
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>>
>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
>>
>>> Hi,
>>> I am building edk2 payload and getting below warning for
>>> PcdRtcIndexRegister,
>>> and if try to boot to then observing that there is assert at:
>>>
>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>
>>> DXE_ASSERT!:
>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>> (141): !EFI_ERROR (Status)
>>>
>>>
>>>
>>>
>>> build time warning:
>>> Active Platform =
>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>> .build: : warning: The PCD was not specified by any INF module in the
>>> platform for the given architecture.
>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>> Platform: [UefiPayloadPkg.dsc]
>>> Arch: ['IA32']
>>> build: : warning: The PCD was not specified by any INF module in the
>>> platform for the given architecture.
>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>> Platform: [UefiPayloadPkg.dsc]
>>> Arch: ['IA32']
>>> . done!
>>>
>>>
>>>
>>>
>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>
>>
>>
>>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 19:01 ` ritul guru
@ 2023-02-07 19:02 ` ritul guru
2023-02-07 19:53 ` Sean Rhodes
0 siblings, 1 reply; 14+ messages in thread
From: ritul guru @ 2023-02-07 19:02 UTC (permalink / raw)
To: Sean Rhodes; +Cc: devel
[-- Attachment #1: Type: text/plain, Size: 2761 bytes --]
CONFIG_PAYLOAD_EDK2=y
# CONFIG_PAYLOAD_LINUX is not set
CONFIG_PAYLOAD_FILE="build/UEFIPAYLOAD.fd"
CONFIG_PAYLOAD_OPTIONS=""
CONFIG_EDK2_UEFIPAYLOAD=y
# CONFIG_EDK2_REPO_MRCHROMEBOX is not set
CONFIG_EDK2_REPO_OFFICIAL=y
# CONFIG_EDK2_REPO_CUSTOM is not set
CONFIG_EDK2_REPOSITORY="https://github.com/tianocore/edk2"
CONFIG_EDK2_TAG_OR_REV="origin/master"
CONFIG_EDK2_DEBUG=y
# CONFIG_EDK2_RELEASE is not set
CONFIG_EDK2_VERBOSE_BUILD=y
# CONFIG_EDK2_ABOVE_4G_MEMORY is not set
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
*Thanks & RegardsRitul Guru+91-9916513186*
On Wed, Feb 8, 2023 at 12:31 AM ritul guru <ritul.bits@gmail.com> wrote:
> building it inside coreboot only.
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
>
> On Wed, Feb 8, 2023 at 12:00 AM Sean Rhodes <sean@starlabs.systems> wrote:
>
>> Hi Ritul
>>
>> It might be easier to build it inside coreboot; that'll use coreboots
>> tool chain and Kconfig so everything will just work.
>>
>> I.e. CONFIG_PAYLOAD_EDK2=y
>>
>> Sean
>>
>> On Tue, 7 Feb 2023, 18:24 ritul guru, <ritul.bits@gmail.com> wrote:
>>
>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>> DEFINE FD_BASE = 0x00800000
>>>
>>> Is the above address correct in uefipaylaod?
>>> As observing some regions are getting out of limit of FD limit,
>>>
>>> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert
>>> in
>>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>>
>>>
>>>
>>>
>>>
>>>
>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>
>>>
>>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
>>>
>>>> Hi,
>>>> I am building edk2 payload and getting below warning for
>>>> PcdRtcIndexRegister,
>>>> and if try to boot to then observing that there is assert at:
>>>>
>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>
>>>> DXE_ASSERT!:
>>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>>> (141): !EFI_ERROR (Status)
>>>>
>>>>
>>>>
>>>>
>>>> build time warning:
>>>> Active Platform =
>>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>>> .build: : warning: The PCD was not specified by any INF module in the
>>>> platform for the given architecture.
>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>>> Platform: [UefiPayloadPkg.dsc]
>>>> Arch: ['IA32']
>>>> build: : warning: The PCD was not specified by any INF module in the
>>>> platform for the given architecture.
>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>>> Platform: [UefiPayloadPkg.dsc]
>>>> Arch: ['IA32']
>>>> . done!
>>>>
>>>>
>>>>
>>>>
>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>
>>>
>>>
>>>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 19:02 ` ritul guru
@ 2023-02-07 19:53 ` Sean Rhodes
2023-02-07 20:25 ` ritul guru
0 siblings, 1 reply; 14+ messages in thread
From: Sean Rhodes @ 2023-02-07 19:53 UTC (permalink / raw)
To: ritul guru; +Cc: devel
[-- Attachment #1: Type: text/plain, Size: 3069 bytes --]
For anyone to be able to help, you'd need to post a build log, .config, tag
and what custom patches you are using.
On Tue, 7 Feb 2023 at 19:02, ritul guru <ritul.bits@gmail.com> wrote:
> CONFIG_PAYLOAD_EDK2=y
> # CONFIG_PAYLOAD_LINUX is not set
> CONFIG_PAYLOAD_FILE="build/UEFIPAYLOAD.fd"
> CONFIG_PAYLOAD_OPTIONS=""
> CONFIG_EDK2_UEFIPAYLOAD=y
> # CONFIG_EDK2_REPO_MRCHROMEBOX is not set
> CONFIG_EDK2_REPO_OFFICIAL=y
> # CONFIG_EDK2_REPO_CUSTOM is not set
> CONFIG_EDK2_REPOSITORY="https://github.com/tianocore/edk2"
> CONFIG_EDK2_TAG_OR_REV="origin/master"
> CONFIG_EDK2_DEBUG=y
> # CONFIG_EDK2_RELEASE is not set
> CONFIG_EDK2_VERBOSE_BUILD=y
> # CONFIG_EDK2_ABOVE_4G_MEMORY is not set
> CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
>
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
>
> On Wed, Feb 8, 2023 at 12:31 AM ritul guru <ritul.bits@gmail.com> wrote:
>
>> building it inside coreboot only.
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>>
>> On Wed, Feb 8, 2023 at 12:00 AM Sean Rhodes <sean@starlabs.systems>
>> wrote:
>>
>>> Hi Ritul
>>>
>>> It might be easier to build it inside coreboot; that'll use coreboots
>>> tool chain and Kconfig so everything will just work.
>>>
>>> I.e. CONFIG_PAYLOAD_EDK2=y
>>>
>>> Sean
>>>
>>> On Tue, 7 Feb 2023, 18:24 ritul guru, <ritul.bits@gmail.com> wrote:
>>>
>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>> DEFINE FD_BASE = 0x00800000
>>>>
>>>> Is the above address correct in uefipaylaod?
>>>> As observing some regions are getting out of limit of FD limit,
>>>>
>>>> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert
>>>> in
>>>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>
>>>>
>>>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
>>>>
>>>>> Hi,
>>>>> I am building edk2 payload and getting below warning for
>>>>> PcdRtcIndexRegister,
>>>>> and if try to boot to then observing that there is assert at:
>>>>>
>>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>>
>>>>> DXE_ASSERT!:
>>>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>>>> (141): !EFI_ERROR (Status)
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> build time warning:
>>>>> Active Platform =
>>>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>>>> .build: : warning: The PCD was not specified by any INF module in the
>>>>> platform for the given architecture.
>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>> Arch: ['IA32']
>>>>> build: : warning: The PCD was not specified by any INF module in the
>>>>> platform for the given architecture.
>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>> Arch: ['IA32']
>>>>> . done!
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>
>>>>
>>>>
>>>>
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 19:53 ` Sean Rhodes
@ 2023-02-07 20:25 ` ritul guru
0 siblings, 0 replies; 14+ messages in thread
From: ritul guru @ 2023-02-07 20:25 UTC (permalink / raw)
To: Sean Rhodes; +Cc: devel
[-- Attachment #1.1: Type: text/plain, Size: 3361 bytes --]
attaching uefipaylaod patch, .config file and logs.
*Thanks & RegardsRitul Guru+91-9916513186*
On Wed, Feb 8, 2023 at 1:23 AM Sean Rhodes <sean@starlabs.systems> wrote:
> For anyone to be able to help, you'd need to post a build log, .config,
> tag and what custom patches you are using.
>
> On Tue, 7 Feb 2023 at 19:02, ritul guru <ritul.bits@gmail.com> wrote:
>
>> CONFIG_PAYLOAD_EDK2=y
>> # CONFIG_PAYLOAD_LINUX is not set
>> CONFIG_PAYLOAD_FILE="build/UEFIPAYLOAD.fd"
>> CONFIG_PAYLOAD_OPTIONS=""
>> CONFIG_EDK2_UEFIPAYLOAD=y
>> # CONFIG_EDK2_REPO_MRCHROMEBOX is not set
>> CONFIG_EDK2_REPO_OFFICIAL=y
>> # CONFIG_EDK2_REPO_CUSTOM is not set
>> CONFIG_EDK2_REPOSITORY="https://github.com/tianocore/edk2"
>> CONFIG_EDK2_TAG_OR_REV="origin/master"
>> CONFIG_EDK2_DEBUG=y
>> # CONFIG_EDK2_RELEASE is not set
>> CONFIG_EDK2_VERBOSE_BUILD=y
>> # CONFIG_EDK2_ABOVE_4G_MEMORY is not set
>> CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
>>
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>>
>> On Wed, Feb 8, 2023 at 12:31 AM ritul guru <ritul.bits@gmail.com> wrote:
>>
>>> building it inside coreboot only.
>>>
>>>
>>>
>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>
>>>
>>> On Wed, Feb 8, 2023 at 12:00 AM Sean Rhodes <sean@starlabs.systems>
>>> wrote:
>>>
>>>> Hi Ritul
>>>>
>>>> It might be easier to build it inside coreboot; that'll use coreboots
>>>> tool chain and Kconfig so everything will just work.
>>>>
>>>> I.e. CONFIG_PAYLOAD_EDK2=y
>>>>
>>>> Sean
>>>>
>>>> On Tue, 7 Feb 2023, 18:24 ritul guru, <ritul.bits@gmail.com> wrote:
>>>>
>>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>>> DEFINE FD_BASE = 0x00800000
>>>>>
>>>>> Is the above address correct in uefipaylaod?
>>>>> As observing some regions are getting out of limit of FD limit,
>>>>>
>>>>> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert
>>>>> in
>>>>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>
>>>>>
>>>>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com>
>>>>> wrote:
>>>>>
>>>>>> Hi,
>>>>>> I am building edk2 payload and getting below warning for
>>>>>> PcdRtcIndexRegister,
>>>>>> and if try to boot to then observing that there is assert at:
>>>>>>
>>>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>>>
>>>>>> DXE_ASSERT!:
>>>>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>>>>> (141): !EFI_ERROR (Status)
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> build time warning:
>>>>>> Active Platform =
>>>>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>>>>> .build: : warning: The PCD was not specified by any INF module in the
>>>>>> platform for the given architecture.
>>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>>> Arch: ['IA32']
>>>>>> build: : warning: The PCD was not specified by any INF module in the
>>>>>> platform for the given architecture.
>>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>>> Arch: ['IA32']
>>>>>> . done!
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>>
>>>>>
>>>>>
>>>>>
[-- Attachment #1.2: Type: text/html, Size: 9658 bytes --]
[-- Attachment #2: tianocore_uefipayload.patch --]
[-- Type: text/plain, Size: 4986 bytes --]
diff --git a/MdeModulePkg/Logo/Logo.bmp b/MdeModulePkg/Logo/Logo.bmp
index 3e85229e17..7cf0039cfd 100644
Binary files a/MdeModulePkg/Logo/Logo.bmp and b/MdeModulePkg/Logo/Logo.bmp differ
diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec b/PcAtChipsetPkg/PcAtChipsetPkg.dec
index a53ca777e8..952f57ab2b 100644
--- a/PcAtChipsetPkg/PcAtChipsetPkg.dec
+++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec
@@ -47,7 +47,7 @@
# TRUE - RTC port registers are in MMIO space.<BR>
# FALSE - RTC port registers are in I/O space.<BR>
# @Prompt RTC port registers use MMIO.
- gPcAtChipsetPkgTokenSpaceGuid.PcdRtcUseMmio|FALSE|BOOLEAN|0x00000021
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcUseMmio|TRUE|BOOLEAN|0x00000021
[PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]
## This PCD specifies the base address of the HPET timer.
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec b/UefiPayloadPkg/UefiPayloadPkg.dec
index 1ccfc32548..dcc5f2c4ad 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dec
+++ b/UefiPayloadPkg/UefiPayloadPkg.dec
@@ -85,7 +85,7 @@ gUefiPayloadPkgTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000|UINT32|0x
gUefiPayloadPkgTokenSpaceGuid.PcdPcdDriverFile|{ 0x57, 0x72, 0xcf, 0x80, 0xab, 0x87, 0xf9, 0x47, 0xa3, 0xfe, 0xD5, 0x0B, 0x76, 0xd8, 0x95, 0x41 }|VOID*|0x00000018
# Above 4G Memory
-gUefiPayloadPkgTokenSpaceGuid.PcdDispatchModuleAbove4GMemory|TRUE|BOOLEAN|0x00000019
+gUefiPayloadPkgTokenSpaceGuid.PcdDispatchModuleAbove4GMemory|FALSE|BOOLEAN|0x00000019
# Boot Manager Key
gUefiPayloadPkgTokenSpaceGuid.PcdBootManagerEscape|FALSE|BOOLEAN|0x00000020
diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 2dbd875f37..2fd90452bf 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -34,7 +34,7 @@
DEFINE SECURITY_STUB_ENABLE = TRUE
DEFINE SMM_SUPPORT = FALSE
DEFINE PLATFORM_BOOT_TIMEOUT = 3
- DEFINE ABOVE_4G_MEMORY = TRUE
+ DEFINE ABOVE_4G_MEMORY = FALSE
DEFINE BOOT_MANAGER_ESCAPE = FALSE
DEFINE ATA_ENABLE = TRUE
DEFINE SD_ENABLE = TRUE
@@ -70,7 +70,7 @@
# Serial port set up
#
DEFINE BAUD_RATE = 115200
- DEFINE SERIAL_CLOCK_RATE = 1843200
+ DEFINE SERIAL_CLOCK_RATE = 47923200
DEFINE SERIAL_LINE_CONTROL = 3 # 8-bits, no parity
DEFINE SERIAL_HARDWARE_FLOW_CONTROL = FALSE
DEFINE SERIAL_DETECT_CABLE = FALSE
@@ -130,7 +130,7 @@
# For recent X86 CPU, 0x15 CPUID instruction will return Time Stamp Counter Frequence.
# This is how BaseCpuTimerLib works, and a recommended way to get Frequence, so set the default value as TRUE.
# Note: for emulation platform such as QEMU, this may not work and should set it as FALSE
- DEFINE CPU_TIMER_LIB_ENABLE = TRUE
+ DEFINE CPU_TIMER_LIB_ENABLE = FALSE
DEFINE MULTIPLE_DEBUG_PORT_SUPPORT = FALSE
@@ -285,7 +285,8 @@
!endif
!endif
- DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+# DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
@@ -496,11 +497,17 @@
#
# The following parameters are set by Library/PlatformHookLib
#
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0
+ # gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
+ # gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|$(BAUD_RATE)
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
-
+ # gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|4
+ #gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|FALSE
+ #gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0
+ #gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialPciDeviceInfo | {0xFF}
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase | 0xFEDC9000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio | TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride | 0x4
#
# Enable these parameters to be set on the command line
#
diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayloadPkg.fdf
index ee7d718b3f..2da9803af0 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -9,7 +9,7 @@
##
[Defines]
-DEFINE FD_BASE = 0x00800000
+DEFINE FD_BASE = 0x02182000
DEFINE FD_BLOCK_SIZE = 0x00001000
!if $(TARGET) == "NOOPT"
[-- Attachment #3: MobaXterm_EMBLAB6281amd_20230207_232513 - Copy.txt --]
[-- Type: text/plain, Size: 164136 bytes --]
[INFO ] FSPS returned 0
[INFO ] Timestamp - returning from FspSiliconInit: 17074382
[INFO ] POST: 0x99
[SPEW ] FspSiliconInit returned 0x00000000
[SPEW ] === FSP HOBs ===
[SPEW ] 0x520fe000: hob_list_ptr
[SPEW ] 0x520fe000, 0x00000038 bytes: HOB_TYPE_HANDOFF
[SPEW ] 0x520fe038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe060, 0x00000108 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe168, 0x00000108 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe270, 0x00000088 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe2f8, 0x00000088 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe380, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe588, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe5a8, 0x00000068 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe610, 0x000011e8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ea296d92-0b69-423c-8c2833b4e0a91268: Unknown GUID
[SPEW ] 0x520ff7f8, 0x00005658 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 9b3ada4f-ae56-4c24-8deaf03b7558ae50: Unknown GUID
[SPEW ] 0x52104e50, 0x00000038 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] bea654e4-4770-4b8d-9524c0f0dbe9e986: Unknown GUID
[SPEW ] 0x52104e88, 0x00000038 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] c8a27c35-c539-4def-90a9a0bd6ce75b17: Unknown GUID
[SPEW ] 0x52104ec0, 0x000037d8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52108698, 0x000003f0 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52108a88, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x521090c0, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x521096f8, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109788, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109818, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109e50, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x5210a488, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x5210aac0, 0x00001018 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 30b174f3-7712-4cca-bd13d0b8a8801997: Unknown GUID
[SPEW ] 0x5210bad8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x5210bb08, 0x00000210 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 0cdfa7da-0d0b-41f0-b98b0f6359c0857f: Unknown GUID
[SPEW ] 0x5210bd18, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd30, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd48, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd60, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd78, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd90, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bda8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdc0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdd8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdf0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be08, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be20, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be38, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be50, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be68, 0x00000e20 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ace4c26a-4a31-4861-8ef9dad07cfd391f: Unknown GUID
[SPEW ] 0x5210cc88, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cca0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccb8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccd0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cce8, 0x00000010 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccf8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cd10, 0x000008f8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 26ab8e31-6c47-480a-a0391e043fa793cd: Unknown GUID
[SPEW ] 0x5210d608, 0x00000058 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210d660, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210d678, 0x00004b98 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52112210, 0x000016f8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 03eb1d90-ce14-40d8-a6ba103a8d7bd32d: Unknown GUID
[SPEW ] 0x52113908, 0x00000420 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113d28, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52113d58, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113d70, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113f78, 0x00000228 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521141a0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521141d0, 0x000000d8 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521142a8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521142c0, 0x00000288 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114548, 0x00000138 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 1bce3d14-a5fe-4a0b-9a8d69ca5d9838d3: Unknown GUID
[SPEW ] 0x52114680, 0x00000828 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 89d85219-2ca1-42de-99327488df4f5f83: Unknown GUID
[SPEW ] 0x52114ea8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ec0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ed8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ef0, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114f10, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] a90f3dfd-db05-4e73-86750dd10f669e0f: Unknown GUID
[SPEW ] 0x52114f40, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52114f70, 0x000002b0 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115220, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115228, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115230, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115238, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115240, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115248, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115250, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115258, 0x00000110 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115368, 0x00000188 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521154f0, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521156f8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource SYSTEM_MEMORY, attribute 3c07
[SPEW ] 0x00000000 + 0x54000000
[SPEW ] 0x52115728, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x54000000 + 0x04000000
[SPEW ] 0x52115758, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x58000000 + 0x02000000
[SPEW ] 0x52115788, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5a000000 + 0x05f90000
[SPEW ] 0x521157b8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5ff90000 + 0x00060000
[SPEW ] 0x521157e8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5fff0000 + 0x00005000
[SPEW ] 0x52115818, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5fff5000 + 0x0000b000
[SPEW ] 0x52115848, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource SYSTEM_MEMORY, attribute 3c07
[SPEW ] 0x100000000 + 0x39e300000
[SPEW ] 0x52115878, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x49e300000 + 0x01040000
[SPEW ] 0x521158a8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x49f340000 + 0x00cc0000
[SPEW ] 0x521158d8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x53000000 + 0x01000000
[SPEW ] Owner GUID: 5fc7897a-5aff-4c61-aa7addcfa918430c (Unknown GUID)
[SPEW ] 0x52115908, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x52ffe000 + 0x00002000
[SPEW ] Owner GUID: 73ff4f56-aa8e-4451-b31636353667ad44 (BOOTLOADER_TOLUM)
[SPEW ] 0x52115938, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x51ffe000 + 0x01000000
[SPEW ] Owner GUID: 69a79759-1373-4367-a6c4c7f59efd986e (FSP_RESERVED_MEMORY)
[SPEW ] 0x52115968, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52115998, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521159c8, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] f2784616-b9bf-4e1e-99e09626da7ea5f5: Unknown GUID
[SPEW ] 0x521159e8, 0x00000688 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116070, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116088, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521160a8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521160d8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116108, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 614facf7-1ac6-4b15-a88c2c1a70d777ec: Unknown GUID
[SPEW ] 0x52116138, 0x00000080 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521161b8, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d178f11d-8716-418e-a131967d2ac42843: Unknown GUID
[SPEW ] 0x52116248, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 58eb6a19-3699-4c68-a836dacd8edcad4a: Unknown GUID
[SPEW ] 0x52116268, 0x00000350 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521165b8, 0x00000360 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 9e9f374b-8f16-4230-98245846ee766a97: Unknown GUID
[SPEW ] 0x52116918, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116948, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116978, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521169a8, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116bb0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116be0, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c08, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c20, 0x00000010 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c30, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c50, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116c80, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116cb0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116ce0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116d10, 0x00000e30 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ea296d92-0b69-423c-8c2833b4e0a91268: Unknown GUID
[SPEW ] 0x52117b40, 0x00000008 bytes: HOB_TYPE_END_OF_HOB_LIST
[SPEW ] === End of FSP HOBs ===
[DEBUG] 0x0000000000000508: IA32_MTRRCAP: WC, FIX, 8 variable MTRRs
[DEBUG] 0x0000000000000c00: IA32_MTRR_DEF_TYPE: E, FE, UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX64K_00000
[DEBUG] 0x00000000 - 0x0007ffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX16K_80000
[DEBUG] 0x00080000 - 0x0009ffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_A0000
[DEBUG] 0x000a0000 - 0x000bffff: UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C0000
[DEBUG] 0x000c0000 - 0x000c7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C8000
[DEBUG] 0x000c8000 - 0x000cffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D0000
[DEBUG] 0x000d0000 - 0x000d7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D8000
[DEBUG] 0x000d8000 - 0x000dffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E0000
[DEBUG] 0x000e0000 - 0x000e7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E8000
[DEBUG] 0x000e8000 - 0x000effff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F0000
[DEBUG] 0x000f0000 - 0x000f7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F8000
[DEBUG] 0x000f8000 - 0x000fffff: UC
[DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB
[DEBUG] 0x0000ffffc0000800: PHYMASK0: Length = 0x0000000040000000, Valid
[DEBUG] 0x0000000040000006: PHYBASE1: Address = 0x0000000040000000, WB
[DEBUG] 0x0000ffffe0000800: PHYMASK1: Length = 0x0000000020000000, Valid
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x0000ffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
[DEBUG] 0x0000000000000000: PHYBASE3
[DEBUG] 0x0000000000000000: PHYMASK3: Disabled
[DEBUG] 0x0000000000000000: PHYBASE4
[DEBUG] 0x0000000000000000: PHYMASK4: Disabled
[DEBUG] 0x0000000000000000: PHYBASE5
[DEBUG] 0x0000000000000000: PHYMASK5: Disabled
[DEBUG] 0x0000000000000000: PHYBASE6
[DEBUG] 0x0000000000000000: PHYMASK6: Disabled
[DEBUG] 0x0000000000000000: PHYBASE7
[DEBUG] 0x0000000000000000: PHYMASK7: Disabled
[INFO ] FPDT Extended Firmware Performance HOB Not Found!
[INFO ] Check if PcdFspPerformanceEnable is set to `TRUE` inside FSP package
[SPEW ] === Data Fabric MMIO configuration registers ===
[SPEW ] Addresses are shifted to the right by 16 bits.
[SPEW ] idx control base limit
[SPEW ] 0 130003 f000 febf
[SPEW ] 1 130003 1000000 3ffcffff
[SPEW ] 2 130003 6000 dfff
[SPEW ] 3 130000 0 0
[SPEW ] 4 130000 0 0
[SPEW ] 5 130000 0 0
[SPEW ] 6 130000 0 0
[SPEW ] 7 130000 0 0
[SPEW ] === Data Fabric MMIO configuration registers ===
[SPEW ] Addresses are shifted to the right by 16 bits.
[SPEW ] idx control base limit
[SPEW ] 0 130003 f000 febf
[SPEW ] 1 130003 1000000 3ffcffff
[SPEW ] 2 130003 6000 dfff
[SPEW ] 3 13000b fed0 fedf
[SPEW ] 4 130000 0 0
[SPEW ] 5 130000 0 0
[SPEW ] 6 130000 0 0
[SPEW ] 7 130000 0 0
[DEBUG] Configuring DDI1 as HDMI.
[INFO ] PCIe device 1.1 disabled, disabling GPP clk req 0, DXIO descriptor 0
[INFO ] PCIe device 2.2 disabled, disabling GPP clk req 6, DXIO descriptor 2
[DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 734 / 1847 ms
[INFO ] POST: 0x72
[INFO ] Enumerating buses...
[SPEW ] Show all devs... Before device enumeration.
[SPEW ] Root Device: enabled 1
[SPEW ] CPU_CLUSTER: 0: enabled 1
[SPEW ] DOMAIN: 0000: enabled 1
[SPEW ] MMIO: fedc2000: enabled 1
[SPEW ] MMIO: fedc3000: enabled 1
[SPEW ] MMIO: fedc4000: enabled 1
[SPEW ] MMIO: fedc5000: enabled 1
[SPEW ] MMIO: fedc9000: enabled 1
[SPEW ] MMIO: fedca000: enabled 0
[SPEW ] MMIO: fedce000: enabled 0
[SPEW ] MMIO: fedcf000: enabled 0
[SPEW ] MMIO: fedd1000: enabled 0
[SPEW ] MMIO: fedd5000: enabled 0
[SPEW ] PCI: 00:00.0: enabled 1
[SPEW ] PCI: 00:00.2: enabled 1
[SPEW ] PCI: 00:01.0: enabled 1
[SPEW ] PCI: 00:01.1: enabled 1
[SPEW ] PCI: 00:01.2: enabled 0
[SPEW ] PCI: 00:01.3: enabled 0
[SPEW ] PCI: 00:02.0: enabled 1
[SPEW ] PCI: 00:02.1: enabled 1
[SPEW ] PCI: 00:02.2: enabled 1
[SPEW ] PCI: 00:02.3: enabled 1
[SPEW ] PCI: 00:02.4: enabled 1
[SPEW ] PCI: 00:02.5: enabled 0
[SPEW ] PCI: 00:02.6: enabled 0
[SPEW ] PCI: 00:02.7: enabled 0
[SPEW ] PCI: 00:08.0: enabled 1
[SPEW ] PCI: 00:08.1: enabled 1
[SPEW ] PCI: 00:08.2: enabled 0
[SPEW ] PCI: 00:08.3: enabled 1
[SPEW ] PCI: 00:14.0: enabled 1
[SPEW ] PCI: 00:14.3: enabled 1
[SPEW ] PCI: 00:18.0: enabled 1
[SPEW ] PCI: 00:18.1: enabled 1
[SPEW ] PCI: 00:18.2: enabled 1
[SPEW ] PCI: 00:18.3: enabled 1
[SPEW ] PCI: 00:18.4: enabled 1
[SPEW ] PCI: 00:18.5: enabled 1
[SPEW ] PCI: 00:18.6: enabled 1
[SPEW ] PCI: 00:18.7: enabled 1
[SPEW ] PCI: 00:00.0: enabled 1
[SPEW ] PCI: 00:00.1: enabled 1
[SPEW ] PCI: 00:00.2: enabled 1
[SPEW ] PCI: 00:00.3: enabled 1
[SPEW ] PCI: 00:00.4: enabled 1
[SPEW ] PCI: 00:00.5: enabled 1
[SPEW ] PCI: 00:00.6: enabled 0
[SPEW ] PCI: 00:00.7: enabled 0
[SPEW ] PCI: 00:00.0: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB3 port 0: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] USB2 port 1: enabled 1
[SPEW ] USB3 port 0: enabled 1
[SPEW ] USB3 port 1: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] USB2 port 1: enabled 1
[SPEW ] USB2 port 2: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] Compare with tree...
[SPEW ] Root Device: enabled 1
[SPEW ] CPU_CLUSTER: 0: enabled 1
[SPEW ] DOMAIN: 0000: enabled 1
[SPEW ] PCI: 00:00.0: enabled 1
[SPEW ] PCI: 00:00.2: enabled 1
[SPEW ] PCI: 00:01.0: enabled 1
[SPEW ] PCI: 00:01.1: enabled 1
[SPEW ] PCI: 00:01.2: enabled 0
[SPEW ] PCI: 00:01.3: enabled 0
[SPEW ] PCI: 00:02.0: enabled 1
[SPEW ] PCI: 00:02.1: enabled 1
[SPEW ] PCI: 00:02.2: enabled 1
[SPEW ] PCI: 00:02.3: enabled 1
[SPEW ] PCI: 00:02.4: enabled 1
[SPEW ] PCI: 00:02.5: enabled 0
[SPEW ] PCI: 00:02.6: enabled 0
[SPEW ] PCI: 00:02.7: enabled 0
[SPEW ] PCI: 00:08.0: enabled 1
[SPEW ] PCI: 00:08.1: enabled 1
[SPEW ] PCI: 00:00.0: enabled 1
[SPEW ] PCI: 00:00.1: enabled 1
[SPEW ] PCI: 00:00.2: enabled 1
[SPEW ] PCI: 00:00.3: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB3 port 0: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] USB2 port 1: enabled 1
[SPEW ] PCI: 00:00.4: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB3 port 0: enabled 1
[SPEW ] USB3 port 1: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] USB2 port 1: enabled 1
[SPEW ] USB2 port 2: enabled 1
[SPEW ] PCI: 00:00.5: enabled 1
[SPEW ] PCI: 00:00.6: enabled 0
[SPEW ] PCI: 00:00.7: enabled 0
[SPEW ] PCI: 00:08.2: enabled 0
[SPEW ] PCI: 00:08.3: enabled 1
[SPEW ] PCI: 00:00.0: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] PCI: 00:14.0: enabled 1
[SPEW ] PCI: 00:14.3: enabled 1
[SPEW ] PCI: 00:18.0: enabled 1
[SPEW ] PCI: 00:18.1: enabled 1
[SPEW ] PCI: 00:18.2: enabled 1
[SPEW ] PCI: 00:18.3: enabled 1
[SPEW ] PCI: 00:18.4: enabled 1
[SPEW ] PCI: 00:18.5: enabled 1
[SPEW ] PCI: 00:18.6: enabled 1
[SPEW ] PCI: 00:18.7: enabled 1
[SPEW ] MMIO: fedc2000: enabled 1
[SPEW ] MMIO: fedc3000: enabled 1
[SPEW ] MMIO: fedc4000: enabled 1
[SPEW ] MMIO: fedc5000: enabled 1
[SPEW ] MMIO: fedc9000: enabled 1
[SPEW ] MMIO: fedca000: enabled 0
[SPEW ] MMIO: fedce000: enabled 0
[SPEW ] MMIO: fedcf000: enabled 0
[SPEW ] MMIO: fedd1000: enabled 0
[SPEW ] MMIO: fedd5000: enabled 0
[DEBUG] Root Device scanning...
[SPEW ] scan_static_bus for Root Device
[DEBUG] CPU_CLUSTER: 0 enabled
[DEBUG] DOMAIN: 0000 enabled
[DEBUG] MMIO: fedc2000 enabled
[DEBUG] MMIO: fedc3000 enabled
[DEBUG] MMIO: fedc4000 enabled
[DEBUG] MMIO: fedc5000 enabled
[DEBUG] MMIO: fedc9000 enabled
[DEBUG] MMIO: fedca000 disabled
[DEBUG] MMIO: fedce000 disabled
[DEBUG] MMIO: fedcf000 disabled
[DEBUG] MMIO: fedd1000 disabled
[DEBUG] MMIO: fedd5000 disabled
[DEBUG] DOMAIN: 0000 scanning...
[DEBUG] PCI: pci_scan_bus for bus 00
[INFO ] POST: 0x24
[DEBUG] PCI: 00:00.0 [1022/14e8] enabled
[DEBUG] PCI: 00:00.2 [1022/14e9] enabled
[DEBUG] PCI: 00:01.0 [1022/14ea] enabled
[INFO ] PCI: Static device PCI: 00:01.1 not found, disabling it.
[DEBUG] PCI: 00:02.0 [1022/14ea] enabled
[INFO ] PCI: Static device PCI: 00:02.1 not found, disabling it.
[INFO ] PCI: Static device PCI: 00:02.2 not found, disabling it.
[INFO ] PCI: Static device PCI: 00:02.3 not found, disabling it.
[DEBUG] PCI: 00:02.4 [1022/14ee] enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd7242
[SPEW ] memalign 0x51fd7248
[DEBUG] PCI: 00:03.0 [1022/14ea] enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd72e8
[SPEW ] memalign 0x51fd72e8
[DEBUG] PCI: 00:03.1 subordinate bus PCI Express
[DEBUG] PCI: 00:03.1 [1022/14ef] enabled
[SPEW ] PCI: 00:03.2, bad id 0x0
[SPEW ] PCI: 00:03.3, bad id 0x0
[SPEW ] PCI: 00:03.4, bad id 0x0
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd7388
[SPEW ] memalign 0x51fd7388
[DEBUG] PCI: 00:04.0 [1022/14ea] enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd7428
[SPEW ] memalign 0x51fd7428
[DEBUG] PCI: 00:04.1 subordinate bus PCI Express
[DEBUG] PCI: 00:04.1 [1022/14ef] enabled
[DEBUG] PCI: 00:08.0 [1022/14ea] enabled
[DEBUG] PCI: 00:08.1 [1022/14eb] enabled
[DEBUG] PCI: 00:08.2 [1022/14eb] disabled
[DEBUG] PCI: 00:08.3 [1022/14eb] enabled
[DEBUG] PCI: 00:14.0 [1022/790b] enabled
[DEBUG] PCI: 00:14.3 [1022/790e] enabled
[DEBUG] PCI: 00:18.0 [1022/12f8] enabled
[DEBUG] PCI: 00:18.1 [1022/12f9] enabled
[DEBUG] PCI: 00:18.2 [1022/12fa] enabled
[DEBUG] PCI: 00:18.3 [1022/12fb] enabled
[DEBUG] PCI: 00:18.4 [1022/12fc] enabled
[DEBUG] PCI: 00:18.5 [1022/12fd] enabled
[DEBUG] PCI: 00:18.6 [1022/12fe] enabled
[DEBUG] PCI: 00:18.7 [1022/12ff] enabled
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 00:01.1
[WARN ] PCI: 00:01.2
[WARN ] PCI: 00:01.3
[WARN ] PCI: 00:02.1
[WARN ] PCI: 00:02.2
[WARN ] PCI: 00:02.3
[WARN ] PCI: 00:02.5
[WARN ] PCI: 00:02.6
[WARN ] PCI: 00:02.7
[WARN ] PCI: Check your devicetree.cb.
[DEBUG] PCI: 00:02.4 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:02.4
[SPEW ] memalign Enter, boundary 8, size 36, free_mem_ptr 0x51fd74c8
[SPEW ] memalign 0x51fd74c8
[DEBUG] PCI: pci_scan_bus for bus 01
[INFO ] POST: 0x24
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd74ec
[SPEW ] memalign 0x51fd74f0
[DEBUG] PCI: 01:00.0 [144d/a808] enabled
[INFO ] POST: 0x25
[INFO ] Enabling Common Clock Configuration
[INFO ] L1 Sub-State supported from root port 2
[INFO ] L1 Sub-State Support = 0xf
[INFO ] CommonModeRestoreTime = 0xa
[INFO ] Power On Value = 0xf, Power On Scale = 0x1
[INFO ] ASPM: Enabled L1
[INFO ] PCIe: Max_Payload_Size adjusted to 256
[DEBUG] scan_bus: bus PCI: 00:02.4 finished in 69 msecs
[DEBUG] PCI: 00:03.1 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:03.1
[SPEW ] memalign Enter, boundary 8, size 36, free_mem_ptr 0x51fd7590
[SPEW ] memalign 0x51fd7590
[DEBUG] PCI: pci_scan_bus for bus 02
[INFO ] POST: 0x24
[INFO ] POST: 0x25
[DEBUG] scan_bus: bus PCI: 00:03.1 finished in 23 msecs
[DEBUG] PCI: 00:04.1 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:04.1
[SPEW ] memalign Enter, boundary 8, size 36, free_mem_ptr 0x51fd75b4
[SPEW ] memalign 0x51fd75b8
[DEBUG] PCI: pci_scan_bus for bus 03
[INFO ] POST: 0x24
[INFO ] POST: 0x25
[DEBUG] scan_bus: bus PCI: 00:04.1 finished in 23 msecs
[DEBUG] PCI: 00:08.1 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:08.1
[DEBUG] PCI: pci_scan_bus for bus 04
[INFO ] POST: 0x24
[DEBUG] PCI: 04:00.0 [1002/15c8] enabled
[DEBUG] PCI: 04:00.1 [1002/1640] enabled
[DEBUG] PCI: 04:00.2 [1022/15c7] enabled
[DEBUG] PCI: 04:00.3 [1022/15bb] enabled
[DEBUG] PCI: 04:00.4 [1022/15bd] enabled
[DEBUG] PCI: 04:00.5 [1022/15e2] enabled
[DEBUG] PCI: 04:00.7 [1022/164a] disabled
[WARN ] PCI: Leftover static devices:
[WARN ] PCI: 04:00.6
[WARN ] PCI: Check your devicetree.cb.
[DEBUG] PCI: 04:00.0 scanning...
[SPEW ] scan_static_bus for PCI: 04:00.0
[SPEW ] scan_static_bus for PCI: 04:00.0 done
[DEBUG] scan_bus: bus PCI: 04:00.0 finished in 9 msecs
[DEBUG] PCI: 04:00.5 scanning...
[SPEW ] scan_static_bus for PCI: 04:00.5
[SPEW ] scan_static_bus for PCI: 04:00.5 done
[DEBUG] scan_bus: bus PCI: 04:00.5 finished in 9 msecs
[INFO ] POST: 0x25
[DEBUG] scan_bus: bus PCI: 00:08.1 finished in 93 msecs
[DEBUG] PCI: 00:08.3 scanning...
[SPEW ] do_pci_scan_bridge for PCI: 00:08.3
[DEBUG] PCI: pci_scan_bus for bus 05
[INFO ] POST: 0x24
[DEBUG] PCI: 05:00.0 [1022/14ec] enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd75dc
[SPEW ] memalign 0x51fd75e0
[DEBUG] PCI: 05:00.3 [1022/15c2] enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd7680
[SPEW ] memalign 0x51fd7680
[DEBUG] PCI: 05:00.4 [1022/15c3] enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd7720
[SPEW ] memalign 0x51fd7720
[DEBUG] PCI: 05:00.5 [1022/15c4] enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd77c0
[SPEW ] memalign 0x51fd77c0
[DEBUG] PCI: 05:00.6 [1022/15c5] enabled
[INFO ] POST: 0x25
[DEBUG] scan_bus: bus PCI: 00:08.3 finished in 76 msecs
[DEBUG] PCI: 00:14.0 scanning...
[SPEW ] scan_generic_bus for PCI: 00:14.0
[SPEW ] scan_generic_bus for PCI: 00:14.0 done
[DEBUG] scan_bus: bus PCI: 00:14.0 finished in 9 msecs
[DEBUG] PCI: 00:14.3 scanning...
[SPEW ] scan_static_bus for PCI: 00:14.3
[SPEW ] scan_static_bus for PCI: 00:14.3 done
[DEBUG] scan_bus: bus PCI: 00:14.3 finished in 9 msecs
[INFO ] POST: 0x25
[DEBUG] scan_bus: bus DOMAIN: 0000 finished in 604 msecs
[DEBUG] MMIO: fedc2000 scanning...
[SPEW ] scan_generic_bus for MMIO: fedc2000
[SPEW ] scan_generic_bus for MMIO: fedc2000 done
[DEBUG] scan_bus: bus MMIO: fedc2000 finished in 9 msecs
[DEBUG] MMIO: fedc3000 scanning...
[SPEW ] scan_generic_bus for MMIO: fedc3000
[SPEW ] scan_generic_bus for MMIO: fedc3000 done
[DEBUG] scan_bus: bus MMIO: fedc3000 finished in 9 msecs
[DEBUG] MMIO: fedc4000 scanning...
[SPEW ] scan_generic_bus for MMIO: fedc4000
[SPEW ] scan_generic_bus for MMIO: fedc4000 done
[DEBUG] scan_bus: bus MMIO: fedc4000 finished in 9 msecs
[DEBUG] MMIO: fedc5000 scanning...
[SPEW ] scan_generic_bus for MMIO: fedc5000
[SPEW ] scan_generic_bus for MMIO: fedc5000 done
[DEBUG] scan_bus: bus MMIO: fedc5000 finished in 9 msecs
[DEBUG] MMIO: fedc9000 scanning...
[SPEW ] scan_static_bus for MMIO: fedc9000
[SPEW ] scan_static_bus for MMIO: fedc9000 done
[DEBUG] scan_bus: bus MMIO: fedc9000 finished in 9 msecs
[SPEW ] scan_static_bus for Root Device done
[DEBUG] scan_bus: bus Root Device finished in 763 msecs
[INFO ] done
[DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 1254 ms
[INFO ] POST: 0x73
[INFO ] Timestamp - device configuration: 19761328
[DEBUG] found VGA at PCI: 04:00.0
[DEBUG] Setting up VGA for PCI: 04:00.0
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:08.1
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ] Allocating resources...
[INFO ] Reading resources...
[SPEW ] Root Device read_resources bus 0 link: 0
[SPEW ] memalign Enter, boundary 8, size 2560, free_mem_ptr 0x51fd7860
[SPEW ] memalign 0x51fd7860
[SPEW ] DOMAIN: 0000 read_resources bus 0 link: 0
[SPEW ] dev: PCI: 00:00.0, index: 0x0, base: 0x0, size: 0xa0000
[SPEW ] dev: PCI: 00:00.0, index: 0x1, base: 0xa0000, size: 0x20000
[SPEW ] dev: PCI: 00:00.0, index: 0x2, base: 0xc0000, size: 0x40000
[SPEW ] dev: PCI: 00:00.0, index: 0x3, base: 0x100000, size: 0x1f00000
[SPEW ] dev: PCI: 00:00.0, index: 0x4, base: 0x2000000, size: 0x181400
[SPEW ] dev: PCI: 00:00.0, index: 0x5, base: 0x2181400, size: 0x50e7e800
[DEBUG] Adding PCIe enhanced config space BAR 0xe0000000-0xf0000000.
[ERROR] coreboot: address from the FSP HOB 0x 0 with attrib=0x3c07
[ERROR] coreboot: address from the FSP HOB 0x 54000000 with attrib=0x0
[SPEW ] dev: PCI: 00:00.0, index: 0x8, base: 0x54000000, size: 0x4000000
[ERROR] coreboot: address from the FSP HOB 0x 58000000 with attrib=0x0
[SPEW ] dev: PCI: 00:00.0, index: 0x9, base: 0x58000000, size: 0x2000000
[ERROR] coreboot: address from the FSP HOB 0x 5a000000 with attrib=0x0
[SPEW ] dev: PCI: 00:00.0, index: 0xa, base: 0x5a000000, size: 0x5f90000
[ERROR] coreboot: address from the FSP HOB 0x 5ff90000 with attrib=0x0
[SPEW ] dev: PCI: 00:00.0, index: 0xb, base: 0x5ff90000, size: 0x60000
[ERROR] coreboot: address from the FSP HOB 0x 5fff0000 with attrib=0x0
[SPEW ] dev: PCI: 00:00.0, index: 0xc, base: 0x5fff0000, size: 0x5000
[ERROR] coreboot: address from the FSP HOB 0x 5fff5000 with attrib=0x0
[SPEW ] dev: PCI: 00:00.0, index: 0xd, base: 0x5fff5000, size: 0xb000
[ERROR] coreboot: address from the FSP HOB 0x 100000000 with attrib=0x3c07
[SPEW ] dev: PCI: 00:00.0, index: 0xe, base: 0x100000000, size: 0x39e300000
[ERROR] coreboot: address from the FSP HOB 0x 49e300000 with attrib=0x0
[SPEW ] dev: PCI: 00:00.0, index: 0xf, base: 0x49e300000, size: 0x1040000
[ERROR] coreboot: address from the FSP HOB 0x 49f340000 with attrib=0x0
[SPEW ] dev: PCI: 00:00.0, index: 0x10, base: 0x49f340000, size: 0xcc0000
[ERROR] coreboot: address from the FSP HOB 0x 53000000 with attrib=0x3c07
[SPEW ] dev: PCI: 00:00.0, index: 0x11, base: 0x53000000, size: 0x1000000
[ERROR] coreboot: address from the FSP HOB 0x 52ffe000 with attrib=0x3c07
[SPEW ] dev: PCI: 00:00.0, index: 0x12, base: 0x52ffe000, size: 0x2000
[ERROR] coreboot: address from the FSP HOB 0x 51ffe000 with attrib=0x3c07
[SPEW ] dev: PCI: 00:00.0, index: 0x13, base: 0x51ffe000, size: 0x1000000
[SPEW ] PCI: 00:02.4 read_resources bus 1 link: 0
[SPEW ] PCI: 00:02.4 read_resources bus 1 link: 0 done
[SPEW ] PCI: 00:03.1 read_resources bus 2 link: 0
[SPEW ] PCI: 00:03.1 read_resources bus 2 link: 0 done
[SPEW ] PCI: 00:04.1 read_resources bus 3 link: 0
[SPEW ] PCI: 00:04.1 read_resources bus 3 link: 0 done
[SPEW ] PCI: 00:08.1 read_resources bus 4 link: 0
[SPEW ] PCI: 04:00.3 read_resources bus 0 link: 0
[ERROR] USB0 port 0 missing read_resources
[SPEW ] PCI: 04:00.3 read_resources bus 0 link: 0 done
[SPEW ] PCI: 04:00.4 read_resources bus 0 link: 0
[ERROR] USB0 port 0 missing read_resources
[SPEW ] PCI: 04:00.4 read_resources bus 0 link: 0 done
[SPEW ] PCI: 00:08.1 read_resources bus 4 link: 0 done
[SPEW ] PCI: 00:08.3 read_resources bus 5 link: 0
[SPEW ] PCI: 05:00.0 read_resources bus 0 link: 0
[ERROR] USB0 port 0 missing read_resources
[SPEW ] PCI: 05:00.0 read_resources bus 0 link: 0 done
[SPEW ] PCI: 00:08.3 read_resources bus 5 link: 0 done
[SPEW ] dev: PCI: 00:14.3, index: 0x2, base: 0xfec10000, size: 0x400
[SPEW ] DOMAIN: 0000 read_resources bus 0 link: 0 done
[SPEW ] dev: MMIO: fedc2000, index: 0x0, base: 0xfedc2000, size: 0x1000
[SPEW ] dev: MMIO: fedc3000, index: 0x0, base: 0xfedc3000, size: 0x1000
[SPEW ] dev: MMIO: fedc4000, index: 0x0, base: 0xfedc4000, size: 0x1000
[SPEW ] dev: MMIO: fedc5000, index: 0x0, base: 0xfedc5000, size: 0x1000
[SPEW ] dev: MMIO: fedc9000, index: 0x0, base: 0xfedc9000, size: 0x1000
[SPEW ] Root Device read_resources bus 0 link: 0 done
[INFO ] Done reading resources.
[SPEW ] Show resources in subtree (Root Device)...After reading.
[DEBUG] Root Device child on link 0 CPU_CLUSTER: 0
[DEBUG] CPU_CLUSTER: 0
[DEBUG] DOMAIN: 0000 child on link 0 PCI: 00:00.0
[SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
[SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffffffff flags 40040200 index 10000100
[DEBUG] PCI: 00:00.0
[SPEW ] PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
[SPEW ] PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
[SPEW ] PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
[SPEW ] PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3
[SPEW ] PCI: 00:00.0 resource base 2000000 size 181400 align 0 gran 0 limit 0 flags f0004200 index 4
[SPEW ] PCI: 00:00.0 resource base 2181400 size 50e7e800 align 0 gran 0 limit 0 flags e0004200 index 5
[SPEW ] PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 6
[SPEW ] PCI: 00:00.0 resource base fec01000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 7
[SPEW ] PCI: 00:00.0 resource base 54000000 size 4000000 align 0 gran 0 limit 0 flags f0004200 index 8
[SPEW ] PCI: 00:00.0 resource base 58000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 9
[SPEW ] PCI: 00:00.0 resource base 5a000000 size 5f90000 align 0 gran 0 limit 0 flags f0004200 index a
[SPEW ] PCI: 00:00.0 resource base 5ff90000 size 60000 align 0 gran 0 limit 0 flags f0004200 index b
[SPEW ] PCI: 00:00.0 resource base 5fff0000 size 5000 align 0 gran 0 limit 0 flags f0004200 index c
[SPEW ] PCI: 00:00.0 resource base 5fff5000 size b000 align 0 gran 0 limit 0 flags f0004200 index d
[SPEW ] PCI: 00:00.0 resource base 100000000 size 39e300000 align 0 gran 0 limit 0 flags e0004200 index e
[SPEW ] PCI: 00:00.0 resource base 49e300000 size 1040000 align 0 gran 0 limit 0 flags f0004200 index f
[SPEW ] PCI: 00:00.0 resource base 49f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 10
[SPEW ] PCI: 00:00.0 resource base 53000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 11
[SPEW ] PCI: 00:00.0 resource base 52ffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 12
[SPEW ] PCI: 00:00.0 resource base 51ffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 13
[DEBUG] PCI: 00:00.2
[SPEW ] PCI: 00:00.2 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 44
[DEBUG] PCI: 00:01.0
[DEBUG] PCI: 00:02.0
[DEBUG] PCI: 00:02.4 child on link 0 PCI: 01:00.0
[SPEW ] PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
[SPEW ] PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 01:00.0
[SPEW ] PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 00:03.0
[DEBUG] PCI: 00:03.1
[SPEW ] PCI: 00:03.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
[SPEW ] PCI: 00:03.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:03.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 00:04.0
[DEBUG] PCI: 00:04.1
[SPEW ] PCI: 00:04.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
[SPEW ] PCI: 00:04.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:04.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 00:08.0
[DEBUG] PCI: 00:08.1 child on link 0 PCI: 04:00.0
[SPEW ] PCI: 00:08.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
[SPEW ] PCI: 00:08.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:08.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 04:00.0
[SPEW ] PCI: 04:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 10
[SPEW ] PCI: 04:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 18
[SPEW ] PCI: 04:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20
[SPEW ] PCI: 04:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 24
[DEBUG] PCI: 04:00.1
[SPEW ] PCI: 04:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
[DEBUG] PCI: 04:00.2
[SPEW ] PCI: 04:00.2 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18
[SPEW ] PCI: 04:00.2 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24
[DEBUG] PCI: 04:00.3 child on link 0 USB0 port 0
[SPEW ] PCI: 04:00.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10
[DEBUG] USB0 port 0 child on link 0 USB3 port 0
[DEBUG] USB3 port 0
[DEBUG] USB2 port 0
[DEBUG] USB2 port 1
[DEBUG] PCI: 04:00.4 child on link 0 USB0 port 0
[SPEW ] PCI: 04:00.4 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10
[DEBUG] USB0 port 0 child on link 0 USB3 port 0
[DEBUG] USB3 port 0
[DEBUG] USB3 port 1
[DEBUG] USB2 port 0
[DEBUG] USB2 port 1
[DEBUG] USB2 port 2
[DEBUG] PCI: 04:00.5
[SPEW ] PCI: 04:00.5 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 10
[SPEW ] PCI: 04:00.5 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18
[DEBUG] PCI: 04:00.7
[DEBUG] PCI: 00:08.2
[DEBUG] PCI: 00:08.3 child on link 0 PCI: 05:00.0
[SPEW ] PCI: 00:08.3 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
[SPEW ] PCI: 00:08.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ] PCI: 00:08.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG] PCI: 05:00.0 child on link 0 USB0 port 0
[DEBUG] USB0 port 0 child on link 0 USB2 port 0
[DEBUG] USB2 port 0
[DEBUG] PCI: 05:00.3
[SPEW ] PCI: 05:00.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 05:00.4
[SPEW ] PCI: 05:00.4 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 05:00.5
[SPEW ] PCI: 05:00.5 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 05:00.6
[SPEW ] PCI: 05:00.6 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 201 index 10
[DEBUG] PCI: 00:14.0
[DEBUG] PCI: 00:14.3
[SPEW ] PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
[SPEW ] PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
[SPEW ] PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags f0000200 index 2
[SPEW ] PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
[DEBUG] PCI: 00:18.0
[DEBUG] PCI: 00:18.1
[DEBUG] PCI: 00:18.2
[DEBUG] PCI: 00:18.3
[DEBUG] PCI: 00:18.4
[DEBUG] PCI: 00:18.5
[DEBUG] PCI: 00:18.6
[DEBUG] PCI: 00:18.7
[DEBUG] MMIO: fedc2000
[SPEW ] MMIO: fedc2000 resource base fedc2000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedc3000
[SPEW ] MMIO: fedc3000 resource base fedc3000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedc4000
[SPEW ] MMIO: fedc4000 resource base fedc4000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedc5000
[SPEW ] MMIO: fedc5000 resource base fedc5000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedc9000
[SPEW ] MMIO: fedc9000 resource base fedc9000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedca000
[DEBUG] MMIO: fedce000
[DEBUG] MMIO: fedcf000
[DEBUG] MMIO: fedd1000
[DEBUG] MMIO: fedd5000
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
[DEBUG] PCI: 00:02.4 io: size: 0 align: 12 gran: 12 limit: ffffffff
[DEBUG] PCI: 00:02.4 io: size: 0 align: 12 gran: 12 limit: ffffffff done
[DEBUG] PCI: 00:02.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
[DEBUG] PCI: 00:02.4 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:02.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:02.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG] PCI: 00:08.1 io: size: 0 align: 12 gran: 12 limit: ffffffff
[DEBUG] PCI: 04:00.0 20 * [0x0 - 0xff] io
[DEBUG] PCI: 00:08.1 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG] PCI: 00:08.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 04:00.2 18 * [0x0 - 0xfffff] mem
[DEBUG] PCI: 04:00.3 10 * [0x100000 - 0x1fffff] mem
[DEBUG] PCI: 04:00.4 10 * [0x200000 - 0x2fffff] mem
[DEBUG] PCI: 04:00.0 24 * [0x300000 - 0x37ffff] mem
[DEBUG] PCI: 04:00.5 10 * [0x380000 - 0x3bffff] mem
[DEBUG] PCI: 04:00.1 10 * [0x3c0000 - 0x3c3fff] mem
[DEBUG] PCI: 04:00.2 24 * [0x3c4000 - 0x3c5fff] mem
[DEBUG] PCI: 00:08.1 mem: size: 400000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:08.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 04:00.0 10 * [0x0 - 0xfffffff] prefmem
[DEBUG] PCI: 04:00.5 18 * [0x10000000 - 0x107fffff] prefmem
[DEBUG] PCI: 04:00.0 18 * [0x10800000 - 0x109fffff] prefmem
[DEBUG] PCI: 00:08.1 prefmem: size: 10a00000 align: 28 gran: 20 limit: ffffffffffffffff done
[DEBUG] PCI: 00:08.3 io: size: 0 align: 12 gran: 12 limit: ffffffff
[DEBUG] PCI: 00:08.3 io: size: 0 align: 12 gran: 12 limit: ffffffff done
[DEBUG] PCI: 00:08.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG] PCI: 05:00.3 10 * [0x0 - 0xfffff] mem
[DEBUG] PCI: 05:00.4 10 * [0x100000 - 0x1fffff] mem
[DEBUG] PCI: 05:00.5 10 * [0x200000 - 0x27ffff] mem
[DEBUG] PCI: 05:00.6 10 * [0x280000 - 0x2fffff] mem
[DEBUG] PCI: 00:08.3 mem: size: 300000 align: 20 gran: 20 limit: ffffffff done
[DEBUG] PCI: 00:08.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG] PCI: 00:08.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8260
[SPEW ] memalign 0x51fd8260
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8278
[SPEW ] memalign 0x51fd8278
[DEBUG] update_constraints: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
[INFO ] DOMAIN: 0000: Resource ranges:
[INFO ] * Base: 1000, Size: f000, Tag: 100
[DEBUG] PCI: 00:08.1 1c * [0x1000 - 0x1fff] limit: 1fff io
[DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffffff
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8290
[SPEW ] memalign 0x51fd8290
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd82a8
[SPEW ] memalign 0x51fd82a8
[DEBUG] update_constraints: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 01 base 000a0000 limit 000bffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 02 base 000c0000 limit 000fffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 03 base 00100000 limit 01ffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 04 base 02000000 limit 021813ff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 05 base 02181400 limit 52fffbff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 06 base e0000000 limit efffffff mem (fixed)
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd82c0
[SPEW ] memalign 0x51fd82c0
[DEBUG] update_constraints: PCI: 00:00.0 07 base fec01000 limit fec01fff mem (fixed)
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd82d8
[SPEW ] memalign 0x51fd82d8
[DEBUG] update_constraints: PCI: 00:00.0 08 base 54000000 limit 57ffffff mem (fixed)
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd82f0
[SPEW ] memalign 0x51fd82f0
[DEBUG] update_constraints: PCI: 00:00.0 09 base 58000000 limit 59ffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 0a base 5a000000 limit 5ff8ffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 0b base 5ff90000 limit 5ffeffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 0c base 5fff0000 limit 5fff4fff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 0d base 5fff5000 limit 5fffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 0e base 100000000 limit 49e2fffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 0f base 49e300000 limit 49f33ffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 10 base 49f340000 limit 49fffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 11 base 53000000 limit 53ffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 12 base 52ffe000 limit 52ffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:00.0 13 base 51ffe000 limit 52ffdfff mem (fixed)
[DEBUG] update_constraints: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed)
[DEBUG] update_constraints: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed)
[DEBUG] update_constraints: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed)
[INFO ] DOMAIN: 0000: Resource ranges:
[INFO ] * Base: 60000000, Size: 80000000, Tag: 200
[INFO ] * Base: f0000000, Size: ec00000, Tag: 200
[INFO ] * Base: fec02000, Size: e000, Tag: 200
[INFO ] * Base: fec11000, Size: 3ef000, Tag: 200
[INFO ] * Base: 4a0000000, Size: fffb60000000, Tag: 100200
[DEBUG] PCI: 00:08.1 24 * [0x60000000 - 0x709fffff] limit: 709fffff prefmem
[DEBUG] PCI: 00:08.1 20 * [0x70a00000 - 0x70dfffff] limit: 70dfffff mem
[DEBUG] PCI: 00:08.3 20 * [0x70e00000 - 0x710fffff] limit: 710fffff mem
[DEBUG] PCI: 00:02.4 20 * [0x71100000 - 0x711fffff] limit: 711fffff mem
[DEBUG] PCI: 00:00.2 44 * [0x71200000 - 0x7127ffff] limit: 7127ffff mem
[DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffffff done
[DEBUG] PCI: 00:02.4 mem: base: 71100000 size: 100000 align: 20 gran: 20 limit: 711fffff
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8308
[SPEW ] memalign 0x51fd8308
[INFO ] PCI: 00:02.4: Resource ranges:
[INFO ] * Base: 71100000, Size: 100000, Tag: 200
[DEBUG] PCI: 01:00.0 10 * [0x71100000 - 0x71103fff] limit: 71103fff mem
[DEBUG] PCI: 00:02.4 mem: base: 71100000 size: 100000 align: 20 gran: 20 limit: 711fffff done
[DEBUG] PCI: 00:08.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8320
[SPEW ] memalign 0x51fd8320
[INFO ] PCI: 00:08.1: Resource ranges:
[INFO ] * Base: 1000, Size: 1000, Tag: 100
[DEBUG] PCI: 04:00.0 20 * [0x1000 - 0x10ff] limit: 10ff io
[DEBUG] PCI: 00:08.1 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done
[DEBUG] PCI: 00:08.1 prefmem: base: 60000000 size: 10a00000 align: 28 gran: 20 limit: 709fffff
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8338
[SPEW ] memalign 0x51fd8338
[INFO ] PCI: 00:08.1: Resource ranges:
[INFO ] * Base: 60000000, Size: 10a00000, Tag: 1200
[DEBUG] PCI: 04:00.0 10 * [0x60000000 - 0x6fffffff] limit: 6fffffff prefmem
[DEBUG] PCI: 04:00.5 18 * [0x70000000 - 0x707fffff] limit: 707fffff prefmem
[DEBUG] PCI: 04:00.0 18 * [0x70800000 - 0x709fffff] limit: 709fffff prefmem
[DEBUG] PCI: 00:08.1 prefmem: base: 60000000 size: 10a00000 align: 28 gran: 20 limit: 709fffff done
[DEBUG] PCI: 00:08.1 mem: base: 70a00000 size: 400000 align: 20 gran: 20 limit: 70dfffff
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8350
[SPEW ] memalign 0x51fd8350
[INFO ] PCI: 00:08.1: Resource ranges:
[INFO ] * Base: 70a00000, Size: 400000, Tag: 200
[DEBUG] PCI: 04:00.2 18 * [0x70a00000 - 0x70afffff] limit: 70afffff mem
[DEBUG] PCI: 04:00.3 10 * [0x70b00000 - 0x70bfffff] limit: 70bfffff mem
[DEBUG] PCI: 04:00.4 10 * [0x70c00000 - 0x70cfffff] limit: 70cfffff mem
[DEBUG] PCI: 04:00.0 24 * [0x70d00000 - 0x70d7ffff] limit: 70d7ffff mem
[DEBUG] PCI: 04:00.5 10 * [0x70d80000 - 0x70dbffff] limit: 70dbffff mem
[DEBUG] PCI: 04:00.1 10 * [0x70dc0000 - 0x70dc3fff] limit: 70dc3fff mem
[DEBUG] PCI: 04:00.2 24 * [0x70dc4000 - 0x70dc5fff] limit: 70dc5fff mem
[DEBUG] PCI: 00:08.1 mem: base: 70a00000 size: 400000 align: 20 gran: 20 limit: 70dfffff done
[DEBUG] PCI: 00:08.3 mem: base: 70e00000 size: 300000 align: 20 gran: 20 limit: 710fffff
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8368
[SPEW ] memalign 0x51fd8368
[INFO ] PCI: 00:08.3: Resource ranges:
[INFO ] * Base: 70e00000, Size: 300000, Tag: 200
[DEBUG] PCI: 05:00.3 10 * [0x70e00000 - 0x70efffff] limit: 70efffff mem
[DEBUG] PCI: 05:00.4 10 * [0x70f00000 - 0x70ffffff] limit: 70ffffff mem
[DEBUG] PCI: 05:00.5 10 * [0x71000000 - 0x7107ffff] limit: 7107ffff mem
[DEBUG] PCI: 05:00.6 10 * [0x71080000 - 0x710fffff] limit: 710fffff mem
[DEBUG] PCI: 00:08.3 mem: base: 70e00000 size: 300000 align: 20 gran: 20 limit: 710fffff done
[INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[SPEW ] Root Device assign_resources, bus 0 link: 0
[SPEW ] DOMAIN: 0000 assign_resources, bus 0 link: 0
[DEBUG] PCI: 00:00.2 44 <- [0x0000000071200000 - 0x000000007127ffff] size 0x00080000 gran 0x13 mem
[DEBUG] PCI: 00:02.4 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c bus 01 io
[DEBUG] PCI: 00:02.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
[DEBUG] PCI: 00:02.4 20 <- [0x0000000071100000 - 0x00000000711fffff] size 0x00100000 gran 0x14 bus 01 mem
[SPEW ] PCI: 00:02.4 assign_resources, bus 1 link: 0
[DEBUG] PCI: 01:00.0 10 <- [0x0000000071100000 - 0x0000000071103fff] size 0x00004000 gran 0x0e mem64
[SPEW ] PCI: 00:02.4 assign_resources, bus 1 link: 0 done
[DEBUG] PCI: 00:03.1 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c bus 02 io
[DEBUG] PCI: 00:03.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
[DEBUG] PCI: 00:03.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 02 mem
[DEBUG] PCI: 00:04.1 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c bus 03 io
[DEBUG] PCI: 00:04.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
[DEBUG] PCI: 00:04.1 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 03 mem
[DEBUG] PCI: 00:08.1 1c <- [0x0000000000001000 - 0x0000000000001fff] size 0x00001000 gran 0x0c bus 04 io
[DEBUG] PCI: 00:08.1 24 <- [0x0000000060000000 - 0x00000000709fffff] size 0x10a00000 gran 0x14 bus 04 prefmem
[DEBUG] PCI: 00:08.1 20 <- [0x0000000070a00000 - 0x0000000070dfffff] size 0x00400000 gran 0x14 bus 04 mem
[SPEW ] PCI: 00:08.1 assign_resources, bus 4 link: 0
[DEBUG] PCI: 04:00.0 10 <- [0x0000000060000000 - 0x000000006fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG] PCI: 04:00.0 18 <- [0x0000000070800000 - 0x00000000709fffff] size 0x00200000 gran 0x15 prefmem64
[DEBUG] PCI: 04:00.0 20 <- [0x0000000000001000 - 0x00000000000010ff] size 0x00000100 gran 0x08 io
[DEBUG] PCI: 04:00.0 24 <- [0x0000000070d00000 - 0x0000000070d7ffff] size 0x00080000 gran 0x13 mem
[INFO ] Timestamp - Option ROM initialization: 22193385
[SPEW ] CBFS DEBUG: _cbfs_alloc(name='pci1002,15c8.rom', alloc=0x00000000(0x00000000), force_ro=false, type=-1)
[WARN ] CBFS: 'pci1002,15c8.rom' not found.
[DEBUG] PCI Option ROM loading disabled for PCI: 04:00.0
[DEBUG] PCI: 04:00.1 10 <- [0x0000000070dc0000 - 0x0000000070dc3fff] size 0x00004000 gran 0x0e mem
[DEBUG] PCI: 04:00.2 18 <- [0x0000000070a00000 - 0x0000000070afffff] size 0x00100000 gran 0x14 mem
[DEBUG] PCI: 04:00.2 24 <- [0x0000000070dc4000 - 0x0000000070dc5fff] size 0x00002000 gran 0x0d mem
[DEBUG] PCI: 04:00.3 10 <- [0x0000000070b00000 - 0x0000000070bfffff] size 0x00100000 gran 0x14 mem64
[SPEW ] PCI: 04:00.3 assign_resources, bus 0 link: 0
[SPEW ] PCI: 04:00.3 assign_resources, bus 0 link: 0 done
[DEBUG] PCI: 04:00.4 10 <- [0x0000000070c00000 - 0x0000000070cfffff] size 0x00100000 gran 0x14 mem64
[SPEW ] PCI: 04:00.4 assign_resources, bus 0 link: 0
[SPEW ] PCI: 04:00.4 assign_resources, bus 0 link: 0 done
[DEBUG] PCI: 04:00.5 10 <- [0x0000000070d80000 - 0x0000000070dbffff] size 0x00040000 gran 0x12 mem
[DEBUG] PCI: 04:00.5 18 <- [0x0000000070000000 - 0x00000000707fffff] size 0x00800000 gran 0x17 prefmem64
[SPEW ] PCI: 00:08.1 assign_resources, bus 4 link: 0 done
[DEBUG] PCI: 00:08.3 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c bus 05 io
[DEBUG] PCI: 00:08.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
[DEBUG] PCI: 00:08.3 20 <- [0x0000000070e00000 - 0x00000000710fffff] size 0x00300000 gran 0x14 bus 05 mem
[SPEW ] PCI: 00:08.3 assign_resources, bus 5 link: 0
[DEBUG] PCI: 05:00.3 10 <- [0x0000000070e00000 - 0x0000000070efffff] size 0x00100000 gran 0x14 mem64
[DEBUG] PCI: 05:00.4 10 <- [0x0000000070f00000 - 0x0000000070ffffff] size 0x00100000 gran 0x14 mem64
[DEBUG] PCI: 05:00.5 10 <- [0x0000000071000000 - 0x000000007107ffff] size 0x00080000 gran 0x13 mem64
[DEBUG] PCI: 05:00.6 10 <- [0x0000000071080000 - 0x00000000710fffff] size 0x00080000 gran 0x13 mem64
[SPEW ] PCI: 00:08.3 assign_resources, bus 5 link: 0 done
[SPEW ] DOMAIN: 0000 assign_resources, bus 0 link: 0 done
[SPEW ] Root Device assign_resources, bus 0 link: 0 done
[INFO ] Done setting resources.
[SPEW ] Show resources in subtree (Root Device)...After assigning values.
[DEBUG] Root Device child on link 0 CPU_CLUSTER: 0
[DEBUG] CPU_CLUSTER: 0
[DEBUG] DOMAIN: 0000 child on link 0 PCI: 00:00.0
[SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
[SPEW ] DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffffffff flags 40040200 index 10000100
[DEBUG] PCI: 00:00.0
[SPEW ] PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
[SPEW ] PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
[SPEW ] PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
[SPEW ] PCI: 00:00.0 resource base 100000 size 1f00000 align 0 gran 0 limit 0 flags e0004200 index 3
[SPEW ] PCI: 00:00.0 resource base 2000000 size 181400 align 0 gran 0 limit 0 flags f0004200 index 4
[SPEW ] PCI: 00:00.0 resource base 2181400 size 50e7e800 align 0 gran 0 limit 0 flags e0004200 index 5
[SPEW ] PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 6
[SPEW ] PCI: 00:00.0 resource base fec01000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 7
[SPEW ] PCI: 00:00.0 resource base 54000000 size 4000000 align 0 gran 0 limit 0 flags f0004200 index 8
[SPEW ] PCI: 00:00.0 resource base 58000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 9
[SPEW ] PCI: 00:00.0 resource base 5a000000 size 5f90000 align 0 gran 0 limit 0 flags f0004200 index a
[SPEW ] PCI: 00:00.0 resource base 5ff90000 size 60000 align 0 gran 0 limit 0 flags f0004200 index b
[SPEW ] PCI: 00:00.0 resource base 5fff0000 size 5000 align 0 gran 0 limit 0 flags f0004200 index c
[SPEW ] PCI: 00:00.0 resource base 5fff5000 size b000 align 0 gran 0 limit 0 flags f0004200 index d
[SPEW ] PCI: 00:00.0 resource base 100000000 size 39e300000 align 0 gran 0 limit 0 flags e0004200 index e
[SPEW ] PCI: 00:00.0 resource base 49e300000 size 1040000 align 0 gran 0 limit 0 flags f0004200 index f
[SPEW ] PCI: 00:00.0 resource base 49f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 10
[SPEW ] PCI: 00:00.0 resource base 53000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 11
[SPEW ] PCI: 00:00.0 resource base 52ffe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 12
[SPEW ] PCI: 00:00.0 resource base 51ffe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 13
[DEBUG] PCI: 00:00.2
[SPEW ] PCI: 00:00.2 resource base 71200000 size 80000 align 19 gran 19 limit 7127ffff flags 60000200 index 44
[DEBUG] PCI: 00:01.0
[DEBUG] PCI: 00:02.0
[DEBUG] PCI: 00:02.4 child on link 0 PCI: 01:00.0
[SPEW ] PCI: 00:02.4 resource base ffffffff size 0 align 12 gran 12 limit ffffffff flags 20080102 index 1c
[SPEW ] PCI: 00:02.4 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ] PCI: 00:02.4 resource base 71100000 size 100000 align 20 gran 20 limit 711fffff flags 60080202 index 20
[DEBUG] PCI: 01:00.0
[SPEW ] PCI: 01:00.0 resource base 71100000 size 4000 align 14 gran 14 limit 71103fff flags 60000201 index 10
[DEBUG] PCI: 00:03.0
[DEBUG] PCI: 00:03.1
[SPEW ] PCI: 00:03.1 resource base ffffffff size 0 align 12 gran 12 limit ffffffff flags 20080102 index 1c
[SPEW ] PCI: 00:03.1 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ] PCI: 00:03.1 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
[DEBUG] PCI: 00:04.0
[DEBUG] PCI: 00:04.1
[SPEW ] PCI: 00:04.1 resource base ffffffff size 0 align 12 gran 12 limit ffffffff flags 20080102 index 1c
[SPEW ] PCI: 00:04.1 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ] PCI: 00:04.1 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
[DEBUG] PCI: 00:08.0
[DEBUG] PCI: 00:08.1 child on link 0 PCI: 04:00.0
[SPEW ] PCI: 00:08.1 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
[SPEW ] PCI: 00:08.1 resource base 60000000 size 10a00000 align 28 gran 20 limit 709fffff flags 60081202 index 24
[SPEW ] PCI: 00:08.1 resource base 70a00000 size 400000 align 20 gran 20 limit 70dfffff flags 60080202 index 20
[DEBUG] PCI: 04:00.0
[SPEW ] PCI: 04:00.0 resource base 60000000 size 10000000 align 28 gran 28 limit 6fffffff flags 60001201 index 10
[SPEW ] PCI: 04:00.0 resource base 70800000 size 200000 align 21 gran 21 limit 709fffff flags 60001201 index 18
[SPEW ] PCI: 04:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20
[SPEW ] PCI: 04:00.0 resource base 70d00000 size 80000 align 19 gran 19 limit 70d7ffff flags 60000200 index 24
[DEBUG] PCI: 04:00.1
[SPEW ] PCI: 04:00.1 resource base 70dc0000 size 4000 align 14 gran 14 limit 70dc3fff flags 60000200 index 10
[DEBUG] PCI: 04:00.2
[SPEW ] PCI: 04:00.2 resource base 70a00000 size 100000 align 20 gran 20 limit 70afffff flags 60000200 index 18
[SPEW ] PCI: 04:00.2 resource base 70dc4000 size 2000 align 13 gran 13 limit 70dc5fff flags 60000200 index 24
[DEBUG] PCI: 04:00.3 child on link 0 USB0 port 0
[SPEW ] PCI: 04:00.3 resource base 70b00000 size 100000 align 20 gran 20 limit 70bfffff flags 60000201 index 10
[DEBUG] USB0 port 0 child on link 0 USB3 port 0
[DEBUG] USB3 port 0
[DEBUG] USB2 port 0
[DEBUG] USB2 port 1
[DEBUG] PCI: 04:00.4 child on link 0 USB0 port 0
[SPEW ] PCI: 04:00.4 resource base 70c00000 size 100000 align 20 gran 20 limit 70cfffff flags 60000201 index 10
[DEBUG] USB0 port 0 child on link 0 USB3 port 0
[DEBUG] USB3 port 0
[DEBUG] USB3 port 1
[DEBUG] USB2 port 0
[DEBUG] USB2 port 1
[DEBUG] USB2 port 2
[DEBUG] PCI: 04:00.5
[SPEW ] PCI: 04:00.5 resource base 70d80000 size 40000 align 18 gran 18 limit 70dbffff flags 60000200 index 10
[SPEW ] PCI: 04:00.5 resource base 70000000 size 800000 align 23 gran 23 limit 707fffff flags 60001201 index 18
[DEBUG] PCI: 04:00.7
[DEBUG] PCI: 00:08.2
[DEBUG] PCI: 00:08.3 child on link 0 PCI: 05:00.0
[SPEW ] PCI: 00:08.3 resource base ffffffff size 0 align 12 gran 12 limit ffffffff flags 20080102 index 1c
[SPEW ] PCI: 00:08.3 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ] PCI: 00:08.3 resource base 70e00000 size 300000 align 20 gran 20 limit 710fffff flags 60080202 index 20
[DEBUG] PCI: 05:00.0 child on link 0 USB0 port 0
[DEBUG] USB0 port 0 child on link 0 USB2 port 0
[DEBUG] USB2 port 0
[DEBUG] PCI: 05:00.3
[SPEW ] PCI: 05:00.3 resource base 70e00000 size 100000 align 20 gran 20 limit 70efffff flags 60000201 index 10
[DEBUG] PCI: 05:00.4
[SPEW ] PCI: 05:00.4 resource base 70f00000 size 100000 align 20 gran 20 limit 70ffffff flags 60000201 index 10
[DEBUG] PCI: 05:00.5
[SPEW ] PCI: 05:00.5 resource base 71000000 size 80000 align 19 gran 19 limit 7107ffff flags 60000201 index 10
[DEBUG] PCI: 05:00.6
[SPEW ] PCI: 05:00.6 resource base 71080000 size 80000 align 19 gran 19 limit 710fffff flags 60000201 index 10
[DEBUG] PCI: 00:14.0
[DEBUG] PCI: 00:14.3
[SPEW ] PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
[SPEW ] PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
[SPEW ] PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags f0000200 index 2
[SPEW ] PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
[DEBUG] PCI: 00:18.0
[DEBUG] PCI: 00:18.1
[DEBUG] PCI: 00:18.2
[DEBUG] PCI: 00:18.3
[DEBUG] PCI: 00:18.4
[DEBUG] PCI: 00:18.5
[DEBUG] PCI: 00:18.6
[DEBUG] PCI: 00:18.7
[DEBUG] MMIO: fedc2000
[SPEW ] MMIO: fedc2000 resource base fedc2000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedc3000
[SPEW ] MMIO: fedc3000 resource base fedc3000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedc4000
[SPEW ] MMIO: fedc4000 resource base fedc4000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedc5000
[SPEW ] MMIO: fedc5000 resource base fedc5000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedc9000
[SPEW ] MMIO: fedc9000 resource base fedc9000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 0
[DEBUG] MMIO: fedca000
[DEBUG] MMIO: fedce000
[DEBUG] MMIO: fedcf000
[DEBUG] MMIO: fedd1000
[DEBUG] MMIO: fedd5000
[INFO ] Done allocating resources.
[DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 3524 ms
[DEBUG] 0x0000000000000508: IA32_MTRRCAP: WC, FIX, 8 variable MTRRs
[DEBUG] 0x0000000000000c00: IA32_MTRR_DEF_TYPE: E, FE, UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX64K_00000
[DEBUG] 0x00000000 - 0x0007ffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX16K_80000
[DEBUG] 0x00080000 - 0x0009ffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_A0000
[DEBUG] 0x000a0000 - 0x000bffff: UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C0000
[DEBUG] 0x000c0000 - 0x000c7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C8000
[DEBUG] 0x000c8000 - 0x000cffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D0000
[DEBUG] 0x000d0000 - 0x000d7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D8000
[DEBUG] 0x000d8000 - 0x000dffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E0000
[DEBUG] 0x000e0000 - 0x000e7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E8000
[DEBUG] 0x000e8000 - 0x000effff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F0000
[DEBUG] 0x000f0000 - 0x000f7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F8000
[DEBUG] 0x000f8000 - 0x000fffff: UC
[DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB
[DEBUG] 0x0000ffffc0000800: PHYMASK0: Length = 0x0000000040000000, Valid
[DEBUG] 0x0000000040000006: PHYBASE1: Address = 0x0000000040000000, WB
[DEBUG] 0x0000ffffe0000800: PHYMASK1: Length = 0x0000000020000000, Valid
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x0000ffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
[DEBUG] 0x0000000000000000: PHYBASE3
[DEBUG] 0x0000000000000000: PHYMASK3: Disabled
[DEBUG] 0x0000000000000000: PHYBASE4
[DEBUG] 0x0000000000000000: PHYMASK4: Disabled
[DEBUG] 0x0000000000000000: PHYBASE5
[DEBUG] 0x0000000000000000: PHYMASK5: Disabled
[DEBUG] 0x0000000000000000: PHYBASE6
[DEBUG] 0x0000000000000000: PHYMASK6: Disabled
[DEBUG] 0x0000000000000000: PHYBASE7
[DEBUG] 0x0000000000000000: PHYMASK7: Disabled
[SPEW ] 0x00000020: notify_params->phase
[SPEW ] Calling FspNotify: 0x51f1e378
[SPEW ] 0x51fcbf7c: notify_params
[INFO ] Timestamp - calling FspNotify(AfterPciEnumeration): 23510663
[INFO ] POST: 0x94
NotifyPhaseApi() - Begin [Phase: 00000020]
FSP Post PCI Enumeration ...
Install PPI: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793
Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 52F4571A
BuildAgesaFspAcpi Entry
BuildAgesaFspAcpi Make ALIB
PcieAlibBuildAcpiTable Enter
PcieAlibUpdateGnbData Enter
PcieAlibUpdateGnbData Exit
Sizeof(ALIB_DATA)=1312, PeApmEnable = 0
PcieAlibUpdatePcieData Enter
PsppPolicy = 0
Engine->Type.Port.PcieBridgeId = 5 not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = 4 not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = 3 not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = 2 not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = 1 not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = 0 not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = D not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = C not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = B not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = A not allocated or non-hotplug
Engine->Type.Port.PcieBridgeId = 1
PortData->PciePortMaxSpeed = 1
PortData->PciePortCurSpeed = 1
PortData->PciePortDcSpeed = 1
PortData->PciePortAcSpeed = 1
PortData->StartPhyLane = 14
PortData->EndPhyLane = 17
PortData->StartCoreLane = FF
PortData->EndCoreLane = FF
PortData->PortId = 1
PortData->LinkHotplug = 0
PortData->PciDev = 2
PortData->PciFun = 4
Engine->Type.Port.PcieBridgeId = 8 not allocated or non-hotplug
ExportFspAcpiTable Entry for A L I B
ExportFspAcpiTable Putting table into HOB of size 0x7D72. This hob is 1 out of 1.
PcieAlibBuildAcpiTable Exit [0x0]
BuildAgesaFspAcpi Exit
BuildAgesaSmbios Entry
Memory DMI information retrieved from heap data.
BuildAgesaSmbios Exit
[FchInitMid] Fch Init - After PCI Scan ...Start
FchInitMid Enter...
AGESA_TP:[B000AF07]
FchInitMid Exit... Status = [0x0]
[FchInitMid] Fch Init - After PCI Scan ...Complete
Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 52F388CC
SyncDpPhyStaicTable Entry
CompareBetweenApcbAndUMA Exit
Status of CompareBetweenApcbAndUMA 0
SyncDpPhyStaicTable Exit
NotifyPhaseApi() - End [Status: 0x00000000]
[INFO ] Timestamp - returning from FspNotify(AfterPciEnumeration): 23720101
[INFO ] POST: 0xa2
[SPEW ] FspNotify returned 0x00000000
[SPEW ] === FSP HOBs ===
[SPEW ] 0x520fe000: hob_list_ptr
[SPEW ] 0x520fe000, 0x00000038 bytes: HOB_TYPE_HANDOFF
[SPEW ] 0x520fe038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe060, 0x00000108 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe168, 0x00000108 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe270, 0x00000088 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe2f8, 0x00000088 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe380, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe588, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe5a8, 0x00000068 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe610, 0x000011e8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ea296d92-0b69-423c-8c2833b4e0a91268: Unknown GUID
[SPEW ] 0x520ff7f8, 0x00005658 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 9b3ada4f-ae56-4c24-8deaf03b7558ae50: Unknown GUID
[SPEW ] 0x52104e50, 0x00000038 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] bea654e4-4770-4b8d-9524c0f0dbe9e986: Unknown GUID
[SPEW ] 0x52104e88, 0x00000038 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] c8a27c35-c539-4def-90a9a0bd6ce75b17: Unknown GUID
[SPEW ] 0x52104ec0, 0x000037d8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52108698, 0x000003f0 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52108a88, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x521090c0, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x521096f8, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109788, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109818, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109e50, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x5210a488, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x5210aac0, 0x00001018 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 30b174f3-7712-4cca-bd13d0b8a8801997: Unknown GUID
[SPEW ] 0x5210bad8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x5210bb08, 0x00000210 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 0cdfa7da-0d0b-41f0-b98b0f6359c0857f: Unknown GUID
[SPEW ] 0x5210bd18, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd30, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd48, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd60, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd78, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd90, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bda8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdc0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdd8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdf0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be08, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be20, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be38, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be50, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be68, 0x00000e20 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ace4c26a-4a31-4861-8ef9dad07cfd391f: Unknown GUID
[SPEW ] 0x5210cc88, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cca0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccb8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccd0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cce8, 0x00000010 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccf8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cd10, 0x000008f8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 26ab8e31-6c47-480a-a0391e043fa793cd: Unknown GUID
[SPEW ] 0x5210d608, 0x00000058 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210d660, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210d678, 0x00004b98 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52112210, 0x000016f8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 03eb1d90-ce14-40d8-a6ba103a8d7bd32d: Unknown GUID
[SPEW ] 0x52113908, 0x00000420 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113d28, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52113d58, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113d70, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113f78, 0x00000228 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521141a0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521141d0, 0x000000d8 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521142a8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521142c0, 0x00000288 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114548, 0x00000138 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 1bce3d14-a5fe-4a0b-9a8d69ca5d9838d3: Unknown GUID
[SPEW ] 0x52114680, 0x00000828 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 89d85219-2ca1-42de-99327488df4f5f83: Unknown GUID
[SPEW ] 0x52114ea8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ec0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ed8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ef0, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114f10, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] a90f3dfd-db05-4e73-86750dd10f669e0f: Unknown GUID
[SPEW ] 0x52114f40, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52114f70, 0x000002b0 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115220, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115228, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115230, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115238, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115240, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115248, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115250, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115258, 0x00000110 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115368, 0x00000188 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521154f0, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521156f8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource SYSTEM_MEMORY, attribute 3c07
[SPEW ] 0x00000000 + 0x54000000
[SPEW ] 0x52115728, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x54000000 + 0x04000000
[SPEW ] 0x52115758, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x58000000 + 0x02000000
[SPEW ] 0x52115788, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5a000000 + 0x05f90000
[SPEW ] 0x521157b8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5ff90000 + 0x00060000
[SPEW ] 0x521157e8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5fff0000 + 0x00005000
[SPEW ] 0x52115818, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5fff5000 + 0x0000b000
[SPEW ] 0x52115848, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource SYSTEM_MEMORY, attribute 3c07
[SPEW ] 0x100000000 + 0x39e300000
[SPEW ] 0x52115878, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x49e300000 + 0x01040000
[SPEW ] 0x521158a8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x49f340000 + 0x00cc0000
[SPEW ] 0x521158d8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x53000000 + 0x01000000
[SPEW ] Owner GUID: 5fc7897a-5aff-4c61-aa7addcfa918430c (Unknown GUID)
[SPEW ] 0x52115908, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x52ffe000 + 0x00002000
[SPEW ] Owner GUID: 73ff4f56-aa8e-4451-b31636353667ad44 (BOOTLOADER_TOLUM)
[SPEW ] 0x52115938, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x51ffe000 + 0x01000000
[SPEW ] Owner GUID: 69a79759-1373-4367-a6c4c7f59efd986e (FSP_RESERVED_MEMORY)
[SPEW ] 0x52115968, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52115998, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521159c8, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] f2784616-b9bf-4e1e-99e09626da7ea5f5: Unknown GUID
[SPEW ] 0x521159e8, 0x00000688 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116070, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116088, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521160a8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521160d8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116108, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 614facf7-1ac6-4b15-a88c2c1a70d777ec: Unknown GUID
[SPEW ] 0x52116138, 0x00000080 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521161b8, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d178f11d-8716-418e-a131967d2ac42843: Unknown GUID
[SPEW ] 0x52116248, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 58eb6a19-3699-4c68-a836dacd8edcad4a: Unknown GUID
[SPEW ] 0x52116268, 0x00000350 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521165b8, 0x00000360 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 9e9f374b-8f16-4230-98245846ee766a97: Unknown GUID
[SPEW ] 0x52116918, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116948, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116978, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521169a8, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116bb0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116be0, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c08, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c20, 0x00000010 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c30, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c50, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116c80, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116cb0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116ce0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116d10, 0x00000e30 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ea296d92-0b69-423c-8c2833b4e0a91268: Unknown GUID
[SPEW ] 0x52117b40, 0x0000fff8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 42494c41-4002-403b-87e13feb13c5669a: Unknown GUID
[SPEW ] 0x52127b38, 0x0000fff8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 4118fc0e-353d-4726-97c053cd92b64925: Unknown GUID
[SPEW ] 0x52137b30, 0x00000070 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 6d5cd69d-fb24-4461-aa328ee1b303319c: Unknown GUID
[SPEW ] 0x52137ba0, 0x00000008 bytes: HOB_TYPE_END_OF_HOB_LIST
[SPEW ] === End of FSP HOBs ===
[DEBUG] 0x0000000000000508: IA32_MTRRCAP: WC, FIX, 8 variable MTRRs
[DEBUG] 0x0000000000000c00: IA32_MTRR_DEF_TYPE: E, FE, UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX64K_00000
[DEBUG] 0x00000000 - 0x0007ffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX16K_80000
[DEBUG] 0x00080000 - 0x0009ffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_A0000
[DEBUG] 0x000a0000 - 0x000bffff: UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C0000
[DEBUG] 0x000c0000 - 0x000c7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C8000
[DEBUG] 0x000c8000 - 0x000cffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D0000
[DEBUG] 0x000d0000 - 0x000d7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D8000
[DEBUG] 0x000d8000 - 0x000dffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E0000
[DEBUG] 0x000e0000 - 0x000e7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_E8000
[DEBUG] 0x000e8000 - 0x000effff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F0000
[DEBUG] 0x000f0000 - 0x000f7fff: UC
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX4K_F8000
[DEBUG] 0x000f8000 - 0x000fffff: UC
[DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB
[DEBUG] 0x0000ffffc0000800: PHYMASK0: Length = 0x0000000040000000, Valid
[DEBUG] 0x0000000040000006: PHYBASE1: Address = 0x0000000040000000, WB
[DEBUG] 0x0000ffffe0000800: PHYMASK1: Length = 0x0000000020000000, Valid
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x0000ffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
[DEBUG] 0x0000000000000000: PHYBASE3
[DEBUG] 0x0000000000000000: PHYMASK3: Disabled
[DEBUG] 0x0000000000000000: PHYBASE4
[DEBUG] 0x0000000000000000: PHYMASK4: Disabled
[DEBUG] 0x0000000000000000: PHYBASE5
[DEBUG] 0x0000000000000000: PHYMASK5: Disabled
[DEBUG] 0x0000000000000000: PHYBASE6
[DEBUG] 0x0000000000000000: PHYMASK6: Disabled
[DEBUG] 0x0000000000000000: PHYBASE7
[DEBUG] 0x0000000000000000: PHYMASK7: Disabled
[DEBUG] PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing:
[DEBUG] PCI_INTR_INDEX name PIC mode APIC mode
[DEBUG] 0x00 INTA# 0x0C 0x1F
[DEBUG] 0x01 INTB# 0x0E 0x1F
[DEBUG] 0x02 INTC# 0x0F 0x1F
[DEBUG] 0x03 INTD# 0x0C 0x1F
[DEBUG] 0x04 INTE# 0x0E 0x1F
[DEBUG] 0x05 INTF#/GENINT2 0x0F 0x1F
[DEBUG] 0x06 INTG# 0x0C 0x1F
[DEBUG] 0x07 INTH# 0x0E 0x1F
[DEBUG] 0x08 Misc 0xFA 0x00
[DEBUG] 0x09 Misc0 0x91 0x00
[DEBUG] 0x0A HPET_L 0x00 0x00
[DEBUG] 0x0B HPET_H 0x00 0x00
[DEBUG] 0x0C Ser IRQ INTA 0x1F 0x1F
[DEBUG] 0x0D Ser IRQ INTB 0x1F 0x1F
[DEBUG] 0x0E Ser IRQ INTC 0x1F 0x1F
[DEBUG] 0x0F Ser IRQ INTD 0x1F 0x1F
[DEBUG] 0x10 SCI 0x09 0x09
[DEBUG] 0x11 SMBUS 0x1F 0x1F
[DEBUG] 0x12 ASF 0x1F 0x1F
[DEBUG] 0x16 PerMon 0x1F 0x1F
[DEBUG] 0x17 SD 0x1F 0x1F
[DEBUG] 0x1A SDIO 0x1F 0x1F
[DEBUG] 0x20 CIR 0x1F 0x1F
[DEBUG] 0x21 GPIOa 0x1F 0x1F
[DEBUG] 0x22 GPIOb 0x1F 0x1F
[DEBUG] 0x23 GPIOc 0x1F 0x1F
[DEBUG] 0x43 eMMC 0x1F 0x1F
[DEBUG] 0x50 GPP0 0x1F 0x1F
[DEBUG] 0x51 GPP1 0x1F 0x1F
[DEBUG] 0x52 GPP2 0x1F 0x1F
[DEBUG] 0x53 GPP3 0x1F 0x1F
[DEBUG] 0x62 GPIO 0x0B 0x0B
[DEBUG] 0x70 I2C0 0x0A 0x0A
[DEBUG] 0x71 I2C1 0x07 0x07
[DEBUG] 0x72 I2C2 0x06 0x06
[DEBUG] 0x73 I2C3 0x05 0x05
[DEBUG] 0x74 UART0 0x04 0x04
[DEBUG] 0x75 UART1 0x03 0x03
[DEBUG] 0x76 I2C4 0x1F 0x1F
[DEBUG] 0x77 UART4 0x1F 0x1F
[DEBUG] 0x78 UART2 0x1F 0x1F
[DEBUG] 0x79 UART3 0x1F 0x1F
[DEBUG] 01.1: group: 0, swizzle: 0, irq: 0
[DEBUG] 01.2: group: 1, swizzle: 0, irq: 0
[DEBUG] 01.3: group: 2, swizzle: 0, irq: 0
[DEBUG] 01.4: group: 3, swizzle: 0, irq: 0
[DEBUG] 01.5: group: 4, swizzle: 0, irq: 0
[DEBUG] 01.6: group: 5, swizzle: 0, irq: 0
[DEBUG] 02.1: group: 0, swizzle: 1, irq: 2
[DEBUG] 02.2: group: 1, swizzle: 2, irq: 2
[DEBUG] 02.3: group: 1, swizzle: 1, irq: 2
[DEBUG] 02.4: group: 0, swizzle: 2, irq: 2
[DEBUG] 02.5: group: 2, swizzle: 2, irq: 3
[DEBUG] 02.6: group: 5, swizzle: 2, irq: 1
[DEBUG] 03.1: group: 4, swizzle: 2, irq: 1
[DEBUG] 03.2: group: 5, swizzle: 0, irq: 1
[DEBUG] 03.3: group: 5, swizzle: 2, irq: 1
[DEBUG] 03.4: group: 3, swizzle: 2, irq: 1
[DEBUG] 04.1: group: 2, swizzle: 2, irq: 1
[DEBUG] 08.1: group: 3, swizzle: 2, irq: 4
[DEBUG] 08.2: group: 4, swizzle: 2, irq: 4
[DEBUG] 08.3: group: 5, swizzle: 2, irq: 4
[SPEW ] memalign Enter, boundary 8, size 100, free_mem_ptr 0x51fd8380
[SPEW ] memalign 0x51fd8380
[DEBUG] PCI_CFG IRQ: Write PCI config space IRQ assignments
[SPEW ] PCI IRQ: Found device 0:00.02 using PIN A
[SPEW ] PCI Devfn (0x2) not found in pirq_data table
[SPEW ] PCI IRQ: Found device 0:08.01 using PIN A
[SPEW ] Found this device in pirq_data table entry 17
[SPEW ] Orig INT_PIN : 1 (PIN A)
[SPEW ] PCI_INTR idx : 0x06 (INTG#)
[SPEW ] INT_LINE : 0xC (IRQ 12)
[SPEW ] PCI IRQ: Found device 0:08.03 using PIN A
[SPEW ] Found this device in pirq_data table entry 19
[SPEW ] Orig INT_PIN : 1 (PIN A)
[SPEW ] PCI_INTR idx : 0x06 (INTG#)
[SPEW ] INT_LINE : 0xC (IRQ 12)
[SPEW ] PCI IRQ: Found device 4:00.00 using PIN A
[SPEW ] With INT_PIN swizzled to PIN A
[SPEW ] Attached to bridge device 0:08h.01h
[SPEW ] Found this device in pirq_data table entry 17
[SPEW ] Orig INT_PIN : 1 (PIN A)
[SPEW ] PCI_INTR idx : 0x06 (INTG#)
[SPEW ] INT_LINE : 0xC (IRQ 12)
[SPEW ] PCI IRQ: Found device 4:00.01 using PIN B
[SPEW ] With INT_PIN swizzled to PIN B
[SPEW ] Attached to bridge device 0:08h.01h
[SPEW ] Found this device in pirq_data table entry 17
[SPEW ] Orig INT_PIN : 2 (PIN B)
[SPEW ] PCI_INTR idx : 0x07 (INTH#)
[SPEW ] INT_LINE : 0xE (IRQ 14)
[SPEW ] PCI IRQ: Found device 4:00.02 using PIN C
[SPEW ] With INT_PIN swizzled to PIN C
[SPEW ] Attached to bridge device 0:08h.01h
[SPEW ] Found this device in pirq_data table entry 17
[SPEW ] Orig INT_PIN : 3 (PIN C)
[SPEW ] PCI_INTR idx : 0x04 (INTE#)
[SPEW ] INT_LINE : 0xE (IRQ 14)
[SPEW ] PCI IRQ: Found device 4:00.03 using PIN D
[SPEW ] With INT_PIN swizzled to PIN D
[SPEW ] Attached to bridge device 0:08h.01h
[SPEW ] Found this device in pirq_data table entry 17
[SPEW ] Orig INT_PIN : 4 (PIN D)
[SPEW ] PCI_INTR idx : 0x05 (INTF#/GENINT2)
[SPEW ] INT_LINE : 0xF (IRQ 15)
[SPEW ] PCI IRQ: Found device 4:00.04 using PIN A
[SPEW ] With INT_PIN swizzled to PIN A
[SPEW ] Attached to bridge device 0:08h.01h
[SPEW ] Found this device in pirq_data table entry 17
[SPEW ] Orig INT_PIN : 1 (PIN A)
[SPEW ] PCI_INTR idx : 0x06 (INTG#)
[SPEW ] INT_LINE : 0xC (IRQ 12)
[SPEW ] PCI IRQ: Found device 4:00.05 using PIN B
[SPEW ] With INT_PIN swizzled to PIN B
[SPEW ] Attached to bridge device 0:08h.01h
[SPEW ] Found this device in pirq_data table entry 17
[SPEW ] Orig INT_PIN : 2 (PIN B)
[SPEW ] PCI_INTR idx : 0x07 (INTH#)
[SPEW ] INT_LINE : 0xE (IRQ 14)
[SPEW ] PCI IRQ: Found device 1:00.00 using PIN A
[SPEW ] With INT_PIN swizzled to PIN A
[SPEW ] Attached to bridge device 0:02h.04h
[SPEW ] Found this device in pirq_data table entry 9
[SPEW ] Orig INT_PIN : 1 (PIN A)
[SPEW ] PCI_INTR idx : 0x02 (INTC#)
[SPEW ] INT_LINE : 0xF (IRQ 15)
[SPEW ] PCI IRQ: Found device 5:00.03 using PIN A
[SPEW ] With INT_PIN swizzled to PIN A
[SPEW ] Attached to bridge device 0:08h.03h
[SPEW ] Found this device in pirq_data table entry 19
[SPEW ] Orig INT_PIN : 1 (PIN A)
[SPEW ] PCI_INTR idx : 0x06 (INTG#)
[SPEW ] INT_LINE : 0xC (IRQ 12)
[SPEW ] PCI IRQ: Found device 5:00.04 using PIN B
[SPEW ] With INT_PIN swizzled to PIN B
[SPEW ] Attached to bridge device 0:08h.03h
[SPEW ] Found this device in pirq_data table entry 19
[SPEW ] Orig INT_PIN : 2 (PIN B)
[SPEW ] PCI_INTR idx : 0x07 (INTH#)
[SPEW ] INT_LINE : 0xE (IRQ 14)
[SPEW ] PCI IRQ: Found device 5:00.05 using PIN C
[SPEW ] With INT_PIN swizzled to PIN C
[SPEW ] Attached to bridge device 0:08h.03h
[SPEW ] Found this device in pirq_data table entry 19
[SPEW ] Orig INT_PIN : 3 (PIN C)
[SPEW ] PCI_INTR idx : 0x04 (INTE#)
[SPEW ] INT_LINE : 0xE (IRQ 14)
[SPEW ] PCI IRQ: Found device 5:00.06 using PIN D
[SPEW ] With INT_PIN swizzled to PIN D
[SPEW ] Attached to bridge device 0:08h.03h
[SPEW ] Found this device in pirq_data table entry 19
[SPEW ] Orig INT_PIN : 4 (PIN D)
[SPEW ] PCI_INTR idx : 0x05 (INTF#/GENINT2)
[SPEW ] INT_LINE : 0xF (IRQ 15)
[DEBUG] PCI_CFG IRQ: Finished writing PCI config space IRQ assignments
[DEBUG] BS: BS_DEV_ENABLE entry times (exec / console): 202 / 2279 ms
[INFO ] POST: 0x74
[INFO ] Timestamp - device enable: 25782955
[INFO ] Enabling resources...
[DEBUG] PCI: 00:00.0 cmd <- 00
[DEBUG] PCI: 00:00.2 subsystem <- 1022/14e9
[DEBUG] PCI: 00:00.2 cmd <- 06
[DEBUG] PCI: 00:01.0 subsystem <- 1022/14ea
[DEBUG] PCI: 00:01.0 cmd <- 00
[DEBUG] PCI: 00:02.0 subsystem <- 1022/14ea
[DEBUG] PCI: 00:02.0 cmd <- 00
[DEBUG] PCI: 00:02.4 bridge ctrl <- 0013
[DEBUG] PCI: 00:02.4 cmd <- 06
[DEBUG] PCI: 00:03.0 cmd <- 00
[DEBUG] PCI: 00:03.1 bridge ctrl <- 0013
[DEBUG] PCI: 00:03.1 cmd <- 00
[DEBUG] PCI: 00:04.0 cmd <- 00
[DEBUG] PCI: 00:04.1 bridge ctrl <- 0013
[DEBUG] PCI: 00:04.1 cmd <- 00
[DEBUG] PCI: 00:08.0 subsystem <- 1022/14ea
[DEBUG] PCI: 00:08.0 cmd <- 00
[DEBUG] PCI: 00:08.1 bridge ctrl <- 001b
[DEBUG] PCI: 00:08.1 cmd <- 07
[DEBUG] PCI: 00:08.3 bridge ctrl <- 0013
[DEBUG] PCI: 00:08.3 cmd <- 06
[DEBUG] PCI: 00:14.0 subsystem <- 1022/790b
[DEBUG] PCI: 00:14.0 cmd <- 403
[DEBUG] PCI: 00:14.3 subsystem <- 1022/790e
[DEBUG] PCI: 00:14.3 cmd <- 0f
[DEBUG] PCI: 01:00.0 cmd <- 02
[DEBUG] PCI: 04:00.0 subsystem <- 1002/15c8
[DEBUG] PCI: 04:00.0 cmd <- 03
[DEBUG] PCI: 04:00.1 subsystem <- 1002/1640
[DEBUG] PCI: 04:00.1 cmd <- 02
[DEBUG] PCI: 04:00.2 subsystem <- 1022/15c7
[DEBUG] PCI: 04:00.2 cmd <- 02
[DEBUG] PCI: 04:00.3 subsystem <- 1022/15bb
[DEBUG] PCI: 04:00.3 cmd <- 02
[DEBUG] PCI: 04:00.4 subsystem <- 1022/15bd
[DEBUG] PCI: 04:00.4 cmd <- 02
[DEBUG] PCI: 04:00.5 subsystem <- 1022/15e2
[DEBUG] PCI: 04:00.5 cmd <- 02
[DEBUG] PCI: 05:00.0 subsystem <- 1022/14ec
[DEBUG] PCI: 05:00.0 cmd <- 00
[DEBUG] PCI: 05:00.3 cmd <- 02
[DEBUG] PCI: 05:00.4 cmd <- 02
[DEBUG] PCI: 05:00.5 cmd <- 02
[DEBUG] PCI: 05:00.6 cmd <- 02
[INFO ] done.
[DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 188 ms
[INFO ] POST: 0x75
[INFO ] Timestamp - device initialization: 25977243
[INFO ] Initializing devices...
[INFO ] POST: 0x75
[DEBUG] CPU_CLUSTER: 0 init
[SPEW ] memalign Enter, boundary 8, size 36, free_mem_ptr 0x51fd83e4
[SPEW ] memalign 0x51fd83e8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd840c
[SPEW ] memalign 0x51fd8410
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8428
[SPEW ] memalign 0x51fd8428
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8440
[SPEW ] memalign 0x51fd8440
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8458
[SPEW ] memalign 0x51fd8458
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8470
[SPEW ] memalign 0x51fd8470
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8488
[SPEW ] memalign 0x51fd8488
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd84a0
[SPEW ] memalign 0x51fd84a0
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd84b8
[SPEW ] memalign 0x51fd84b8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd84d0
[SPEW ] memalign 0x51fd84d0
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd84e8
[SPEW ] memalign 0x51fd84e8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8500
[SPEW ] memalign 0x51fd8500
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8518
[SPEW ] memalign 0x51fd8518
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8530
[SPEW ] memalign 0x51fd8530
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8548
[SPEW ] memalign 0x51fd8548
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8560
[SPEW ] memalign 0x51fd8560
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8578
[SPEW ] memalign 0x51fd8578
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8590
[SPEW ] memalign 0x51fd8590
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd85a8
[SPEW ] memalign 0x51fd85a8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd85c0
[SPEW ] memalign 0x51fd85c0
[DEBUG] MTRR: Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000005fffffff size 0x5ff40000 type 6
[DEBUG] 0x0000000060000000 - 0x000000006fffffff size 0x10000000 type 1
[DEBUG] 0x0000000070000000 - 0x00000000707fffff size 0x00800000 type 0
[DEBUG] 0x0000000070800000 - 0x00000000709fffff size 0x00200000 type 1
[DEBUG] 0x0000000070a00000 - 0x00000000ffffffff size 0x8f600000 type 0
[DEBUG] 0x0000000100000000 - 0x000000049fffffff size 0x3a0000000 type 6
[DEBUG] MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG] MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
[DEBUG] MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
[SPEW ] call enable_fixed_mtrr()
[DEBUG] CPU physical address size: 48 bits
[DEBUG] MTRR: default type WB/UC MTRR counts: 10/4.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000ffffc0000000 type 6
[DEBUG] MTRR: 1 base 0x0000000040000000 mask 0x0000ffffe0000000 type 6
[DEBUG] MTRR: 2 base 0x0000000060000000 mask 0x0000fffff0000000 type 1
[DEBUG] MTRR: 3 base 0x0000000070800000 mask 0x0000ffffffe00000 type 1
[DEBUG] MTRR check
[DEBUG] Fixed MTRRs : Enabled
[DEBUG] Variable MTRRs: Enabled
[INFO ] POST: 0x93
[DEBUG] Setting up SMI for CPU
[WARN ] TSEG: tseg_base=0x53000000, tseg_size=0x1000000
[INFO ] Will perform SMM setup.
[INFO ] CPU: AMD Eng Sample: 100-000000929-21_N .
[INFO ] LAPIC 0x0 in XAPIC mode.
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd85d8
[SPEW ] memalign 0x51fd85d8
[DEBUG] CPU: APIC: 00 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8678
[SPEW ] memalign 0x51fd8678
[DEBUG] CPU: APIC: 01 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8718
[SPEW ] memalign 0x51fd8718
[DEBUG] CPU: APIC: 02 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd87b8
[SPEW ] memalign 0x51fd87b8
[DEBUG] CPU: APIC: 03 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8858
[SPEW ] memalign 0x51fd8858
[DEBUG] CPU: APIC: 04 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd88f8
[SPEW ] memalign 0x51fd88f8
[DEBUG] CPU: APIC: 05 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8998
[SPEW ] memalign 0x51fd8998
[DEBUG] CPU: APIC: 06 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8a38
[SPEW ] memalign 0x51fd8a38
[DEBUG] CPU: APIC: 07 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8ad8
[SPEW ] memalign 0x51fd8ad8
[DEBUG] CPU: APIC: 08 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8b78
[SPEW ] memalign 0x51fd8b78
[DEBUG] CPU: APIC: 09 enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8c18
[SPEW ] memalign 0x51fd8c18
[DEBUG] CPU: APIC: 0a enabled
[SPEW ] memalign Enter, boundary 8, size 160, free_mem_ptr 0x51fd8cb8
[SPEW ] memalign 0x51fd8cb8
[DEBUG] CPU: APIC: 0b enabled
[DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG] Processing 16 relocs. Offset value of 0x00030000
[DEBUG] Attempting to start 11 APs
[DEBUG] Waiting for SIPI to complete...
[INFO ] LAPIC 0x9 in XAPIC mode.
[INFO ] LAPIC 0x1 in XAPIC mode.
[INFO ] LAPIC 0x8 in XAPIC mode.
[INFO ] AP: slot 1 apic_id 1
[INFO ] AP: slot 8 apic_id 9
[DEBUG] done.
[SPEW ] APs are ready after 0us
[INFO ] AP: slot 6 apic_id 8
[INFO ] LAPIC 0xb in XAPIC mode.
[INFO ] LAPIC 0x5 in XAPIC mode.
[INFO ] LAPIC 0x6 in XAPIC mode.
[INFO ] LAPIC 0x4 in XAPIC mode.
[INFO ] LAPIC 0x2 in XAPIC mode.
[INFO ] LAPIC 0x7 in XAPIC mode.
[INFO ] LAPIC 0xa in XAPIC mode.
[INFO ] AP: slot 2 apic_id 5
[INFO ] LAPIC 0x3 in XAPIC mode.
[INFO ] AP: slot 5 apic_id 6
[INFO ] AP: slot 10 apic_id b
[INFO ] AP: slot 11 apic_id a
[INFO ] AP: slot 4 apic_id 4
[INFO ] AP: slot 3 apic_id 7
[INFO ] AP: slot 7 apic_id 3
[INFO ] AP: slot 9 apic_id 2
[SPEW ] APs are ready after 60300us
[DEBUG] Installing permanent SMM handler to 0x53000000
[DEBUG] FX_SAVE [0x53e7e800-0x53e80000]
[DEBUG] HANDLER [0x53e7a000-0x53e7dda0]
[DEBUG] CPU 0
[DEBUG] ss0 [0x53e79e00-0x53e7a000]
[DEBUG] stub0 [0x53e72000-0x53e721f8]
[DEBUG] CPU 1
[DEBUG] ss1 [0x53e79c00-0x53e79e00]
[DEBUG] stub1 [0x53e71e00-0x53e71ff8]
[DEBUG] CPU 2
[DEBUG] ss2 [0x53e79a00-0x53e79c00]
[DEBUG] stub2 [0x53e71c00-0x53e71df8]
[DEBUG] CPU 3
[DEBUG] ss3 [0x53e79800-0x53e79a00]
[DEBUG] stub3 [0x53e71a00-0x53e71bf8]
[DEBUG] CPU 4
[DEBUG] ss4 [0x53e79600-0x53e79800]
[DEBUG] stub4 [0x53e71800-0x53e719f8]
[DEBUG] CPU 5
[DEBUG] ss5 [0x53e79400-0x53e79600]
[DEBUG] stub5 [0x53e71600-0x53e717f8]
[DEBUG] CPU 6
[DEBUG] ss6 [0x53e79200-0x53e79400]
[DEBUG] stub6 [0x53e71400-0x53e715f8]
[DEBUG] CPU 7
[DEBUG] ss7 [0x53e79000-0x53e79200]
[DEBUG] stub7 [0x53e71200-0x53e713f8]
[DEBUG] CPU 8
[DEBUG] ss8 [0x53e78e00-0x53e79000]
[DEBUG] stub8 [0x53e71000-0x53e711f8]
[DEBUG] CPU 9
[DEBUG] ss9 [0x53e78c00-0x53e78e00]
[DEBUG] stub9 [0x53e70e00-0x53e70ff8]
[DEBUG] CPU 10
[DEBUG] ss10 [0x53e78a00-0x53e78c00]
[DEBUG] stub10 [0x53e70c00-0x53e70df8]
[DEBUG] CPU 11
[DEBUG] ss11 [0x53e78800-0x53e78a00]
[DEBUG] stub11 [0x53e70a00-0x53e70bf8]
[DEBUG] stacks [0x53000000-0x53006000]
[DEBUG] Loading module at 0x53e7a000 with entry 0x53e7b13a. filesize: 0x2568 memsize: 0x3da0
[DEBUG] Processing 142 relocs. Offset value of 0x53e7a000
[DEBUG] Loading module at 0x53e72000 with entry 0x53e72000. filesize: 0x1f8 memsize: 0x1f8
[DEBUG] Processing 11 relocs. Offset value of 0x53e72000
[DEBUG] smm_module_setup_stub: stack_top = 0x53006000
[DEBUG] smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG] smm_module_setup_stub: runtime.smm_size = 0xe80000
[DEBUG] SMM Module: placing smm entry code at 53e71e00, cpu # 0x1
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e71e00 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e71c00, cpu # 0x2
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e71c00 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e71a00, cpu # 0x3
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e71a00 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e71800, cpu # 0x4
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e71800 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e71600, cpu # 0x5
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e71600 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e71400, cpu # 0x6
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e71400 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e71200, cpu # 0x7
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e71200 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e71000, cpu # 0x8
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e71000 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e70e00, cpu # 0x9
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e70e00 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e70c00, cpu # 0xa
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e70c00 0x1f8 bytes
[DEBUG] SMM Module: placing smm entry code at 53e70a00, cpu # 0xb
[SPEW ] smm_place_entry_code: copying from 53e72000 to 53e70a00 0x1f8 bytes
[DEBUG] SMM Module: stub loaded at 53e72000. Will call 0x53e7b13a
[SPEW ] APs are ready after 100us
[INFO ] Initializing CPU #0
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[INFO ] Timestamp - started reading uCode: 27064718
[SPEW ] CBFS DEBUG: _cbfs_alloc(name='cpu_microcode_a780.bin', alloc=0x00000000(0x00000000), force_ro=false, type=-1)
[INFO ] CBFS: Found 'cpu_microcode_a780.bin' @0x922480 size 0x16c0 in mcache @0x51fdd140
[INFO ] Timestamp - finished reading uCode: 27089691
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #0 initialized
[INFO ] Initializing CPU #8
[INFO ] Initializing CPU #4
[INFO ] Initializing CPU #6
[INFO ] Initializing CPU #3
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[INFO ] Initializing CPU #1
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] Initializing CPU #11
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #6 initialized
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[INFO ] Initializing CPU #5
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[INFO ] Initializing CPU #10
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[DEBUG] microcode: patch id to apply = 0x0a708000
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #8 initialized
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #1 initialized
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] Initializing CPU #2
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #5 initialized
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[INFO ] Initializing CPU #9
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] Initializing CPU #7
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[DEBUG] microcode: patch id to apply = 0x0a708000
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #2 initialized
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #4 initialized
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #10 initialized
[DEBUG] microcode: patch id to apply = 0x0a708000
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #11 initialized
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #3 initialized
[DEBUG] CPU: vendor AMD device a70f80
[DEBUG] CPU: family 19, model 78, stepping 00
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #7 initialized
[DEBUG] microcode: patch id to apply = 0x0a708000
[INFO ] microcode: being updated to patch id = 0x0a708000 succeeded
[INFO ] CPU #9 initialized
[SPEW ] APs are ready after 302700us
[INFO ] bsp_do_flight_plan done after 814 msecs.
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8d58
[SPEW ] memalign 0x51fd8d58
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8d70
[SPEW ] memalign 0x51fd8d70
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8d88
[SPEW ] memalign 0x51fd8d88
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8da0
[SPEW ] memalign 0x51fd8da0
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8db8
[SPEW ] memalign 0x51fd8db8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8dd0
[SPEW ] memalign 0x51fd8dd0
[DEBUG] MTRR: TEMPORARY Physical address space:
[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG] 0x00000000000c0000 - 0x000000005fffffff size 0x5ff40000 type 6
[DEBUG] 0x0000000060000000 - 0x00000000feffffff size 0x9f000000 type 0
[DEBUG] 0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
[DEBUG] 0x0000000100000000 - 0x000000049fffffff size 0x3a0000000 type 6
[DEBUG] MTRR: default type WB/UC MTRR counts: 9/6.
[DEBUG] MTRR: UC selected as default type.
[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000ffffc0000000 type 6
[DEBUG] MTRR: 1 base 0x0000000040000000 mask 0x0000ffffe0000000 type 6
[DEBUG] MTRR: 2 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5
[DEBUG] MTRR: 3 base 0x0000000100000000 mask 0x0000ffff00000000 type 6
[DEBUG] MTRR: 4 base 0x0000000200000000 mask 0x0000fffe00000000 type 6
[DEBUG] MTRR: 5 base 0x0000000400000000 mask 0x0000ffff00000000 type 6
[NOTE ] coreboot-4.18-667-gb1d1aeaafb-dirty Tue Jan 24 03:44:30 UTC 2023 smm starting (log level: 8)...
[SPEW ] SMI# #8
[DEBUG] PSP: Notify SMM info... OK
[DEBUG] APMC done.
[DEBUG] CPU_CLUSTER: 0 init finished in 1611 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[DEBUG] PCI: 00:00.0 init
[DEBUG] IOAPIC: Initializing IOAPIC at 0xfec01000
[DEBUG] IOAPIC: ID = 0x01
[SPEW ] IOAPIC: Dumping registers
[SPEW ] reg 0x0000: 0x01000000
[SPEW ] reg 0x0001: 0x001f8021
[SPEW ] reg 0x0002: 0x00000000
[DEBUG] IOAPIC: 32 interrupts
[DEBUG] IOAPIC: Clearing IOAPIC at 0xfec01000
[SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x01 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x02 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x03 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x04 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x05 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x06 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x07 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x08 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x09 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x10 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x11 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x12 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x13 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x14 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x15 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x16 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x17 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x18 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x19 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x1f value 0x00000000 0x00010000
[DEBUG] PCI: 00:00.0 init finished in 214 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[DEBUG] PCI: 00:01.0 init
[DEBUG] PCI: 00:01.0 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 00:02.0 init
[DEBUG] PCI: 00:02.0 init finished in 0 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[DEBUG] PCI: 00:03.0 init
[DEBUG] PCI: 00:03.0 init finished in 0 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[DEBUG] PCI: 00:04.0 init
[DEBUG] PCI: 00:04.0 init finished in 0 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[DEBUG] PCI: 00:08.0 init
[DEBUG] PCI: 00:08.0 init finished in 0 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[DEBUG] PCI: 00:14.3 init
[DEBUG] RTC Init
[DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000
[SPEW ] IOAPIC: Dumping registers
[SPEW ] reg 0x0000: 0x00000000
[SPEW ] reg 0x0001: 0x00178021
[SPEW ] reg 0x0002: 0x00000000
[DEBUG] IOAPIC: 24 interrupts
[DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000
[SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x01 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x02 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x03 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x04 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x05 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x06 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x07 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x08 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x09 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0a value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0b value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0c value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0d value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0e value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x0f value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x10 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x11 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x12 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x13 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x14 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x15 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x16 value 0x00000000 0x00010000
[SPEW ] IOAPIC: vector 0x17 value 0x00000000 0x00010000
[DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00
[SPEW ] IOAPIC: vector 0x00 value 0x00000000 0x00000700
[DEBUG] PCI: 00:14.3 init finished in 179 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[DEBUG] PCI: 01:00.0 init
[DEBUG] PCI: 01:00.0 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 04:00.0 init
[ALERT] Graphics hand-off block not found
[DEBUG] PCI: 04:00.0 init finished in 4 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 04:00.1 init
[DEBUG] PCI: 04:00.1 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 04:00.2 init
[DEBUG] PCI: 04:00.2 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 04:00.3 init
[DEBUG] PCI: 04:00.3 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 04:00.4 init
[DEBUG] PCI: 04:00.4 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 04:00.5 init
[DEBUG] PCI: 04:00.5 init finished in 0 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[DEBUG] PCI: 05:00.0 init
[DEBUG] PCI: 05:00.0 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 05:00.3 init
[DEBUG] PCI: 05:00.3 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 05:00.4 init
[DEBUG] PCI: 05:00.4 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 05:00.5 init
[DEBUG] PCI: 05:00.5 init finished in 0 msecs
[INFO ] POST: 0x75
[DEBUG] PCI: 05:00.6 init
[DEBUG] PCI: 05:00.6 init finished in 0 msecs
[INFO ] POST: 0x75
[INFO ] POST: 0x75
[INFO ] Devices initialized
[SPEW ] Show all devs... After init.
[SPEW ] Root Device: enabled 1
[SPEW ] CPU_CLUSTER: 0: enabled 1
[SPEW ] DOMAIN: 0000: enabled 1
[SPEW ] MMIO: fedc2000: enabled 1
[SPEW ] MMIO: fedc3000: enabled 1
[SPEW ] MMIO: fedc4000: enabled 1
[SPEW ] MMIO: fedc5000: enabled 1
[SPEW ] MMIO: fedc9000: enabled 1
[SPEW ] MMIO: fedca000: enabled 0
[SPEW ] MMIO: fedce000: enabled 0
[SPEW ] MMIO: fedcf000: enabled 0
[SPEW ] MMIO: fedd1000: enabled 0
[SPEW ] MMIO: fedd5000: enabled 0
[SPEW ] PCI: 00:00.0: enabled 1
[SPEW ] PCI: 00:00.2: enabled 1
[SPEW ] PCI: 00:01.0: enabled 1
[SPEW ] PCI: 00:01.1: enabled 0
[SPEW ] PCI: 00:01.2: enabled 0
[SPEW ] PCI: 00:01.3: enabled 0
[SPEW ] PCI: 00:02.0: enabled 1
[SPEW ] PCI: 00:02.1: enabled 0
[SPEW ] PCI: 00:02.2: enabled 0
[SPEW ] PCI: 00:02.3: enabled 0
[SPEW ] PCI: 00:02.4: enabled 1
[SPEW ] PCI: 00:02.5: enabled 0
[SPEW ] PCI: 00:02.6: enabled 0
[SPEW ] PCI: 00:02.7: enabled 0
[SPEW ] PCI: 00:08.0: enabled 1
[SPEW ] PCI: 00:08.1: enabled 1
[SPEW ] PCI: 00:08.2: enabled 0
[SPEW ] PCI: 00:08.3: enabled 1
[SPEW ] PCI: 00:14.0: enabled 1
[SPEW ] PCI: 00:14.3: enabled 1
[SPEW ] PCI: 00:18.0: enabled 1
[SPEW ] PCI: 00:18.1: enabled 1
[SPEW ] PCI: 00:18.2: enabled 1
[SPEW ] PCI: 00:18.3: enabled 1
[SPEW ] PCI: 00:18.4: enabled 1
[SPEW ] PCI: 00:18.5: enabled 1
[SPEW ] PCI: 00:18.6: enabled 1
[SPEW ] PCI: 00:18.7: enabled 1
[SPEW ] PCI: 04:00.0: enabled 1
[SPEW ] PCI: 04:00.1: enabled 1
[SPEW ] PCI: 04:00.2: enabled 1
[SPEW ] PCI: 04:00.3: enabled 1
[SPEW ] PCI: 04:00.4: enabled 1
[SPEW ] PCI: 04:00.5: enabled 1
[SPEW ] PCI: 04:00.6: enabled 0
[SPEW ] PCI: 04:00.7: enabled 0
[SPEW ] PCI: 05:00.0: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB0 port 0: enabled 1
[SPEW ] USB3 port 0: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] USB2 port 1: enabled 1
[SPEW ] USB3 port 0: enabled 1
[SPEW ] USB3 port 1: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] USB2 port 1: enabled 1
[SPEW ] USB2 port 2: enabled 1
[SPEW ] USB2 port 0: enabled 1
[SPEW ] PCI: 00:03.0: enabled 1
[SPEW ] PCI: 00:03.1: enabled 1
[SPEW ] PCI: 00:04.0: enabled 1
[SPEW ] PCI: 00:04.1: enabled 1
[SPEW ] PCI: 01:00.0: enabled 1
[SPEW ] PCI: 05:00.3: enabled 1
[SPEW ] PCI: 05:00.4: enabled 1
[SPEW ] PCI: 05:00.5: enabled 1
[SPEW ] PCI: 05:00.6: enabled 1
[SPEW ] APIC: 00: enabled 1
[SPEW ] APIC: 01: enabled 1
[SPEW ] APIC: 05: enabled 1
[SPEW ] APIC: 07: enabled 1
[SPEW ] APIC: 04: enabled 1
[SPEW ] APIC: 06: enabled 1
[SPEW ] APIC: 08: enabled 1
[SPEW ] APIC: 03: enabled 1
[SPEW ] APIC: 09: enabled 1
[SPEW ] APIC: 02: enabled 1
[SPEW ] APIC: 0b: enabled 1
[SPEW ] APIC: 0a: enabled 1
[DEBUG] BS: BS_DEV_INIT run times (exec / console): 402 / 2266 ms
[DEBUG] SCIMAP 56 maps to GPE 31 (active high, edge trigger)
[DEBUG] BS: BS_POST_DEVICE entry times (exec / console): 0 / 6 ms
[INFO ] POST: 0x76
[INFO ] Finalize devices...
[INFO ] Devices finalized
[INFO ] Timestamp - device setup done: 28670574
[DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 14 ms
[DEBUG] FMAP: area RW_MRC_CACHE found @ 1001000 (122880 bytes)
[INFO ] Timestamp - starting APOB read: 28688393
[INFO ] APOB RAM hash differs from flash
[SPEW ] Copy APOB from RAM 0x02001000/0xb04c to flash 0x1001000/0x1e000
[DEBUG] FMAP: area RW_MRC_CACHE found @ 1001000 (122880 bytes)
[DEBUG] spi_init: SPI BAR at 0xfec10000
[INFO ] Manufacturer: ef
[INFO ] SF: Detected ef 6019 with sector size 0x1000, total 0x2000000
[INFO ] Timestamp - starting APOB erase: 28725590
[DEBUG] SF: Successfully erased 122880 bytes @ 0x1001000
[INFO ] Timestamp - starting APOB write: 28737333
[INFO ] Timestamp - finished APOB: 28922454
[INFO ] Updated APOB in flash
[DEBUG] BS: BS_POST_DEVICE exit times (exec / console): 181 / 67 ms
[INFO ] POST: 0x77
[INFO ] Timestamp - cbmem post: 28939682
[DEBUG] BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 7 ms
[DEBUG] Saving dimm info for smbios type 17
[DEBUG] AMD_FSP_DMI_HOB found
[DEBUG] AGESA TYPE 17 DMI INFO:
[DEBUG] Handle: 1
[DEBUG] TotalWidth: 32
[DEBUG] DataWidth: 32
[DEBUG] MemorySize: 4096
[DEBUG] DeviceSet: 0
[DEBUG] Speed: 16512
[DEBUG] ManufacturerIdCode: ea6
[DEBUG] Attributes: 50
[DEBUG] ExtSize: 1414996022
[DEBUG] ConfigSpeed: 256
[DEBUG] MemoryType: 0x230000
[DEBUG] FormFactor: 0x1
[DEBUG] DeviceLocator: DIMM 0
[DEBUG] BankLocator: P0 CHANNEL A
[DEBUG] SerialNumber(0):
[DEBUG] PartNumber(5): 00000
[ERROR] Unknown memory type 0
[ERROR] Unknown memory type 0
[ERROR] Unknown memory type 0
[DEBUG] CBMEM_ID_MEMINFO:
[DEBUG] dimm_size: 4096
[DEBUG] ddr_type: 0x0
[DEBUG] max_speed_mts: 0
[DEBUG] config_speed_mts: 0
[DEBUG] vdd_voltage: 0
[DEBUG] rank_per_dimm: 50
[DEBUG] channel_num: 0
[DEBUG] dimm_num: 0
[DEBUG] bank_locator: 0
[DEBUG] mod_id: ea6
[DEBUG] mod_type: 0x0
[DEBUG] bus_width: 2
[DEBUG] serial: 00000000
[DEBUG] module_part_number(5): 00000
[DEBUG] AGESA TYPE 17 DMI INFO:
[DEBUG] Handle: 500
[DEBUG] TotalWidth: 3
[DEBUG] DataWidth: 8
[DEBUG] MemorySize: 0
[DEBUG] DeviceSet: 0
[DEBUG] Speed: 0
[DEBUG] ManufacturerIdCode: 1
[DEBUG] Attributes: 0
[DEBUG] ExtSize: 0
[DEBUG] ConfigSpeed: 0
[DEBUG] MemoryType: 0x0
[DEBUG] FormFactor: 0x0
[DEBUG] DeviceLocator:
[DEBUG] BankLocator:
[DEBUG] SerialNumber(0):
[DEBUG] PartNumber(0):
[ERROR] Unknown memory type 0
[ERROR] Unknown memory type 0
[NOTE ] Unknown number of extension bits 65531Unknown memory type 0
[DEBUG] CBMEM_ID_MEMINFO:
[DEBUG] dimm_size: 0
[DEBUG] ddr_type: 0x0
[DEBUG] max_speed_mts: 0
[DEBUG] config_speed_mts: 0
[DEBUG] vdd_voltage: 0
[DEBUG] rank_per_dimm: 0
[DEBUG] channel_num: 1
[DEBUG] dimm_num: 1
[DEBUG] bank_locator: 0
[DEBUG] mod_id: 1
[DEBUG] mod_type: 0x0
[DEBUG] bus_width: 0
[DEBUG] serial: 00000000
[DEBUG] module_part_number(0):
[DEBUG] AGESA TYPE 17 DMI INFO:
[DEBUG] Handle: 18225
[DEBUG] TotalWidth: 12851
[DEBUG] DataWidth: 12868
[DEBUG] MemorySize: 21316
[DEBUG] DeviceSet: 32
[DEBUG] Speed: 0
[DEBUG] ManufacturerIdCode: 0
[DEBUG] Attributes: 0
[DEBUG] ExtSize: 0
[DEBUG] ConfigSpeed: 0
[DEBUG] MemoryType: 0x0
[DEBUG] FormFactor: 0x3632302d
[DEBUG] DeviceLocator: WT
[DEBUG] BankLocator:
[DEBUG] SerialNumber(0):
[DEBUG] PartNumber(0):
[ERROR] Unknown memory type 0
[ERROR] Unknown memory type 0
[NOTE ] Unknown memory size 12868Unknown number of extension bits 65519Unknown memory type 0
[DEBUG] CBMEM_ID_MEMINFO:
[DEBUG] dimm_size: 21316
[DEBUG] ddr_type: 0x0
[DEBUG] max_speed_mts: 0
[DEBUG] config_speed_mts: 0
[DEBUG] vdd_voltage: 0
[DEBUG] rank_per_dimm: 0
[DEBUG] channel_num: 1
[DEBUG] dimm_num: 1
[DEBUG] bank_locator: 0
[DEBUG] mod_id: 0
[DEBUG] mod_type: 0x0
[DEBUG] bus_width: 0
[DEBUG] serial: 00000000
[DEBUG] module_part_number(0):
[DEBUG] BS: BS_WRITE_TABLES entry times (exec / console): 0 / 358 ms
[INFO ] POST: 0x79
[INFO ] Timestamp - write tables: 29318482
[INFO ] POST: 0x9c
[SPEW ] CBFS DEBUG: _cbfs_alloc(name='fallback/dsdt.aml', alloc=0x00000000(0x00000000), force_ro=false, type=-1)
[INFO ] CBFS: Found 'fallback/dsdt.aml' @0x93e5c0 size 0x347e in mcache @0x51fdd1e8
[SPEW ] CBFS DEBUG: _cbfs_alloc(name='fallback/slic', alloc=0x00000000(0x00000000), force_ro=false, type=-1)
[WARN ] CBFS: 'fallback/slic' not found.
[INFO ] ACPI: Writing ACPI tables at 51ef1000.
[DEBUG] ACPI: * FACS
[DEBUG] ACPI: * DSDT
[DEBUG] ACPI: * FADT
[DEBUG] pm_base: 0x0400
[DEBUG] ACPI: added table 1/32, length now 40
[DEBUG] ACPI: * SSDT
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[ERROR] Couldn't find CCX CPPC data HOB.
[ERROR] Couldn't find CCX CPPC data HOB.
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[DEBUG] PSS: 2800MHz power 3360 control 0x0 status 0x0
[DEBUG] PSS: 1800MHz power 1980 control 0x1 status 0x1
[DEBUG] PSS: 1600MHz power 1600 control 0x2 status 0x2
[SPEW ] memalign Enter, boundary 8, size 5, free_mem_ptr 0x51fd8de8
[SPEW ] memalign 0x51fd8de8
[SPEW ] memalign Enter, boundary 8, size 5, free_mem_ptr 0x51fd8ded
[SPEW ] memalign 0x51fd8df0
[SPEW ] memalign Enter, boundary 8, size 5, free_mem_ptr 0x51fd8df5
[SPEW ] memalign 0x51fd8df8
[SPEW ] memalign Enter, boundary 8, size 5, free_mem_ptr 0x51fd8dfd
[SPEW ] memalign 0x51fd8e00
[SPEW ] memalign Enter, boundary 8, size 5, free_mem_ptr 0x51fd8e05
[SPEW ] memalign 0x51fd8e08
[SPEW ] memalign Enter, boundary 8, size 5, free_mem_ptr 0x51fd8e0d
[SPEW ] memalign 0x51fd8e10
[DEBUG] ACPI: added table 2/32, length now 44
[DEBUG] ACPI: * MCFG
[DEBUG] ACPI: added table 3/32, length now 48
[DEBUG] ACPI: * MADT
[DEBUG] IOAPIC: 24 interrupts
[DEBUG] IOAPIC: 32 interrupts
[DEBUG] ACPI: added table 4/32, length now 52
[DEBUG] current = 51ef7230
[INFO ] ACPI: * ALIB (AGESA).
[DEBUG] ACPI: added table 5/32, length now 56
[DEBUG] ACPI: added table 6/32, length now 60
[DEBUG] ACPI: * HPET
[DEBUG] ACPI: added table 7/32, length now 64
[SPEW ] CBFS DEBUG: _cbfs_alloc(name='pci1002,15c8.rom', alloc=0x00000000(0x00000000), force_ro=false, type=-1)
[WARN ] CBFS: 'pci1002,15c8.rom' not found.
[DEBUG] PCI Option ROM loading disabled for PCI: 04:00.0
[ERROR] pci_rom_acpi_fill_vfct failed
[INFO ] ACPI: done.
[DEBUG] ACPI tables: 57744 bytes.
[DEBUG] smbios_write_tables: 51ee9000
[DEBUG] SMBIOS firmware version is set to coreboot_version: '4.18-667-gb1d1aeaafb-dirty'
[INFO ] Create SMBIOS type 16
[INFO ] Create SMBIOS type 17
[INFO ] Create SMBIOS type 20
[DEBUG] SMBIOS tables: 1125 bytes.
[DEBUG] Writing table forward entry at 0x00000500
[DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 5ded
[DEBUG] Writing coreboot table at 0x51f15000
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8e15
[SPEW ] memalign 0x51fd8e18
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8e30
[SPEW ] memalign 0x51fd8e30
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8e48
[SPEW ] memalign 0x51fd8e48
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8e60
[SPEW ] memalign 0x51fd8e60
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8e78
[SPEW ] memalign 0x51fd8e78
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8e90
[SPEW ] memalign 0x51fd8e90
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8ea8
[SPEW ] memalign 0x51fd8ea8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8ec0
[SPEW ] memalign 0x51fd8ec0
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8ed8
[SPEW ] memalign 0x51fd8ed8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8ef0
[SPEW ] memalign 0x51fd8ef0
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8f08
[SPEW ] memalign 0x51fd8f08
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8f20
[SPEW ] memalign 0x51fd8f20
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8f38
[SPEW ] memalign 0x51fd8f38
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8f50
[SPEW ] memalign 0x51fd8f50
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8f68
[SPEW ] memalign 0x51fd8f68
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8f80
[SPEW ] memalign 0x51fd8f80
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8f98
[SPEW ] memalign 0x51fd8f98
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8fb0
[SPEW ] memalign 0x51fd8fb0
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8fc8
[SPEW ] memalign 0x51fd8fc8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8fe0
[SPEW ] memalign 0x51fd8fe0
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd8ff8
[SPEW ] memalign 0x51fd8ff8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd9010
[SPEW ] memalign 0x51fd9010
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd9028
[SPEW ] memalign 0x51fd9028
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd9040
[SPEW ] memalign 0x51fd9040
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd9058
[SPEW ] memalign 0x51fd9058
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd9070
[SPEW ] memalign 0x51fd9070
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd9088
[SPEW ] memalign 0x51fd9088
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd90a0
[SPEW ] memalign 0x51fd90a0
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd90b8
[SPEW ] memalign 0x51fd90b8
[SPEW ] memalign Enter, boundary 8, size 24, free_mem_ptr 0x51fd90d0
[SPEW ] memalign 0x51fd90d0
[DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG] 1. 0000000000001000-000000000009ffff: RAM
[DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG] 3. 0000000000100000-0000000001ffffff: RAM
[DEBUG] 4. 0000000002000000-0000000002181fff: RESERVED
[DEBUG] 5. 0000000002182000-0000000051ee8fff: RAM
[DEBUG] 6. 0000000051ee9000-0000000051f72fff: CONFIGURATION TABLES
[DEBUG] 7. 0000000051f73000-0000000051fdbfff: RAMSTAGE
[DEBUG] 8. 0000000051fdc000-0000000052ffffff: CONFIGURATION TABLES
[DEBUG] 9. 0000000053000000-000000005fffffff: RESERVED
[DEBUG] 10. 00000000e0000000-00000000efffffff: RESERVED
[DEBUG] 11. 00000000fec10000-00000000fec10fff: RESERVED
[DEBUG] 12. 00000000fedc2000-00000000fedc5fff: RESERVED
[DEBUG] 13. 00000000fedc9000-00000000fedc9fff: RESERVED
[DEBUG] 14. 0000000100000000-000000049e2fffff: RAM
[DEBUG] 15. 000000049e300000-000000049fffffff: RESERVED
[DEBUG] Wrote coreboot table at: 0x51f15000, 0x458 bytes, checksum eaf9
[DEBUG] coreboot table: 1136 bytes.
[DEBUG] IMD ROOT 0. 0x52fff000 0x00001000
[DEBUG] IMD SMALL 1. 0x52ffe000 0x00001000
[DEBUG] FSP MEMORY 2. 0x51ffe000 0x01000000
[DEBUG] CONSOLE 3. 0x51fde000 0x00020000
[DEBUG] RO MCACHE 4. 0x51fdd000 0x00000354
[DEBUG] TIME STAMP 5. 0x51fdc000 0x00000910
[DEBUG] RAMSTAGE 6. 0x51f72000 0x0006a000
[DEBUG] ACPI BERT 7. 0x51f6e000 0x00004000
[DEBUG] REFCODE 8. 0x51f1e000 0x00050000
[DEBUG] MEM INFO 9. 0x51f1d000 0x00000788
[DEBUG] COREBOOT 10. 0x51f15000 0x00008000
[DEBUG] ACPI 11. 0x51ef1000 0x00024000
[DEBUG] SMBIOS 12. 0x51ee9000 0x00008000
[DEBUG] IMD small region:
[DEBUG] IMD ROOT 0. 0x52ffec00 0x00000400
[DEBUG] FSP RUNTIME 1. 0x52ffebe0 0x00000004
[DEBUG] FMAP 2. 0x52ffea80 0x0000015e
[DEBUG] POWER STATE 3. 0x52ffea20 0x00000060
[DEBUG] ROMSTAGE 4. 0x52ffea00 0x00000004
[DEBUG] EARLY DRAM USAGE 5. 0x52ffe9e0 0x00000008
[DEBUG] ACPI GNVS 6. 0x52ffe9c0 0x00000020
[INFO ] Timestamp - finalize chips: 30291147
[DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 2 / 978 ms
[INFO ] POST: 0x7a
[INFO ] Timestamp - starting to load payload: 30305074
[SPEW ] CBFS DEBUG: _cbfs_alloc(name='fallback/payload', alloc=0x00000000(0x00000000), force_ro=false, type=0)
[INFO ] CBFS: Found 'fallback/payload' @0x98b600 size 0x4bbe in mcache @0x51fdd2b8
[DEBUG] Checking segment from ROM address 0xffa8b62c
[DEBUG] Checking segment from ROM address 0xffa8b648
[DEBUG] Checking segment from ROM address 0xffa8b664
[DEBUG] Loading segment from ROM address 0xffa8b62c
[DEBUG] code (compression=0)
[DEBUG] New segment dstaddr 0x00800000 memsize 0x4afe srcaddr 0xffa8b680 filesize 0x4afe
[DEBUG] Loading Segment: addr: 0x00800000 memsz: 0x0000000000004afe filesz: 0x0000000000004afe
[DEBUG] it's not compressed!
[SPEW ] [ 0x00800000, 00804afe, 0x00804afe) <- ffa8b680
[DEBUG] Loading segment from ROM address 0xffa8b648
[DEBUG] data (compression=0)
[DEBUG] New segment dstaddr 0x00804b00 memsize 0x6c srcaddr 0xffa9017e filesize 0x6c
[DEBUG] Loading Segment: addr: 0x00804b00 memsz: 0x000000000000006c filesz: 0x000000000000006c
[DEBUG] it's not compressed!
[SPEW ] [ 0x00804b00, 00804b6c, 0x00804b6c) <- ffa9017e
[DEBUG] Loading segment from ROM address 0xffa8b664
[DEBUG] Entry Point 0x00801260
[SPEW ] Loaded segments
[DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 2 / 126 ms
[DEBUG] 0x0000000000000508: IA32_MTRRCAP: WC, FIX, 8 variable MTRRs
[DEBUG] 0x0000000000000c00: IA32_MTRR_DEF_TYPE: E, FE, UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX64K_00000
[DEBUG] 0x00000000 - 0x0007ffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX16K_80000
[DEBUG] 0x00080000 - 0x0009ffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_A0000
[DEBUG] 0x000a0000 - 0x000bffff: UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C0000
[DEBUG] 0x000c0000 - 0x000c7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C8000
[DEBUG] 0x000c8000 - 0x000cffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D0000
[DEBUG] 0x000d0000 - 0x000d7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D8000
[DEBUG] 0x000d8000 - 0x000dffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_E0000
[DEBUG] 0x000e0000 - 0x000e7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_E8000
[DEBUG] 0x000e8000 - 0x000effff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_F0000
[DEBUG] 0x000f0000 - 0x000f7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_F8000
[DEBUG] 0x000f8000 - 0x000fffff: WB
[DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB
[DEBUG] 0x0000ffffc0000800: PHYMASK0: Length = 0x0000000040000000, Valid
[DEBUG] 0x0000000040000006: PHYBASE1: Address = 0x0000000040000000, WB
[DEBUG] 0x0000ffffe0000800: PHYMASK1: Length = 0x0000000020000000, Valid
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x0000ffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
[DEBUG] 0x0000000100000006: PHYBASE3: Address = 0x0000000100000000, WB
[DEBUG] 0x0000ffff00000800: PHYMASK3: Length = 0x0000000100000000, Valid
[DEBUG] 0x0000000200000006: PHYBASE4: Address = 0x0000000200000000, WB
[DEBUG] 0x0000fffe00000800: PHYMASK4: Length = 0x0000000200000000, Valid
[DEBUG] 0x0000000400000006: PHYBASE5: Address = 0x0000000400000000, WB
[DEBUG] 0x0000ffff00000800: PHYMASK5: Length = 0x0000000100000000, Valid
[DEBUG] 0x0000000000000000: PHYBASE6
[DEBUG] 0x0000000000000000: PHYMASK6: Disabled
[DEBUG] 0x0000000000000000: PHYBASE7
[DEBUG] 0x0000000000000000: PHYMASK7: Disabled
[SPEW ] 0x00000040: notify_params->phase
[SPEW ] Calling FspNotify: 0x51f1e378
[SPEW ] 0x51fcbf6c: notify_params
[INFO ] Timestamp - calling FspNotify(ReadyToBoot): 30670760
[INFO ] POST: 0x95
NotifyPhaseApi() - Begin [Phase: 00000040]
FSP Ready To Boot ...
Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B
Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 52F5E404
AGESA_TP:[B000AD56]
phx: FabricReadyToBoot: Disable extended configuration access
AGESA_TP:[B000ADE6]
Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 52F46194
AGESA_TP:[B000A50A]
Psp.C2PMbox.LockDFReg
Psp.SendC2PCMD [0x1B] Buffer:0x520FCD80
08 00 00 00 00 00 00 00
PspCmd.Value 80000000
AGESA_TP:[B000A61B]
Clear the ready bit before send the command
PspCmd.MboxBuffer 0_520FCD80
AGESA_TP:[B000A69B]
AGESA_TP:[B000A600]
Buffer dump after CMD finished:
08 00 00 00 00 00 00 00
PspCmd.Value 80000000
Psp.SendC2PCMD Exit
Mbox.Hdr.Sts:0x0
AGESA_TP:[B000A50A]
[FchInitLate] Fch Init - Before Boot ...Start
FchInitLate Enter...
AGESA_TP:[B000AF08]
AGESA_TP:[B000AF73]
AGESA_TP:[B000AF70]
AGESA_TP:[B000AF78]
FchInitLate Exit... Status = [0x0]
[FchInitLate] Fch Init - Before Boot ...Complete
NotifyPhaseApi() - End [Status: 0x00000000]
[INFO ] Timestamp - returning from FspNotify(ReadyToBoot): 30775749
[INFO ] POST: 0xa3
[SPEW ] FspNotify returned 0x00000000
[SPEW ] === FSP HOBs ===
[SPEW ] 0x520fe000: hob_list_ptr
[SPEW ] 0x520fe000, 0x00000038 bytes: HOB_TYPE_HANDOFF
[SPEW ] 0x520fe038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe060, 0x00000108 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe168, 0x00000108 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe270, 0x00000088 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe2f8, 0x00000088 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe380, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe588, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe5a8, 0x00000068 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe610, 0x000011e8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ea296d92-0b69-423c-8c2833b4e0a91268: Unknown GUID
[SPEW ] 0x520ff7f8, 0x00005658 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 9b3ada4f-ae56-4c24-8deaf03b7558ae50: Unknown GUID
[SPEW ] 0x52104e50, 0x00000038 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] bea654e4-4770-4b8d-9524c0f0dbe9e986: Unknown GUID
[SPEW ] 0x52104e88, 0x00000038 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] c8a27c35-c539-4def-90a9a0bd6ce75b17: Unknown GUID
[SPEW ] 0x52104ec0, 0x000037d8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52108698, 0x000003f0 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52108a88, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x521090c0, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x521096f8, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109788, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109818, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109e50, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x5210a488, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x5210aac0, 0x00001018 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 30b174f3-7712-4cca-bd13d0b8a8801997: Unknown GUID
[SPEW ] 0x5210bad8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x5210bb08, 0x00000210 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 0cdfa7da-0d0b-41f0-b98b0f6359c0857f: Unknown GUID
[SPEW ] 0x5210bd18, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd30, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd48, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd60, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd78, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd90, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bda8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdc0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdd8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdf0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be08, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be20, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be38, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be50, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be68, 0x00000e20 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ace4c26a-4a31-4861-8ef9dad07cfd391f: Unknown GUID
[SPEW ] 0x5210cc88, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cca0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccb8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccd0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cce8, 0x00000010 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccf8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cd10, 0x000008f8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 26ab8e31-6c47-480a-a0391e043fa793cd: Unknown GUID
[SPEW ] 0x5210d608, 0x00000058 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210d660, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210d678, 0x00004b98 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52112210, 0x000016f8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 03eb1d90-ce14-40d8-a6ba103a8d7bd32d: Unknown GUID
[SPEW ] 0x52113908, 0x00000420 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113d28, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52113d58, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113d70, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113f78, 0x00000228 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521141a0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521141d0, 0x000000d8 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521142a8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521142c0, 0x00000288 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114548, 0x00000138 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 1bce3d14-a5fe-4a0b-9a8d69ca5d9838d3: Unknown GUID
[SPEW ] 0x52114680, 0x00000828 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 89d85219-2ca1-42de-99327488df4f5f83: Unknown GUID
[SPEW ] 0x52114ea8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ec0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ed8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ef0, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114f10, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] a90f3dfd-db05-4e73-86750dd10f669e0f: Unknown GUID
[SPEW ] 0x52114f40, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52114f70, 0x000002b0 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115220, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115228, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115230, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115238, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115240, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115248, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115250, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115258, 0x00000110 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115368, 0x00000188 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521154f0, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521156f8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource SYSTEM_MEMORY, attribute 3c07
[SPEW ] 0x00000000 + 0x54000000
[SPEW ] 0x52115728, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x54000000 + 0x04000000
[SPEW ] 0x52115758, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x58000000 + 0x02000000
[SPEW ] 0x52115788, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5a000000 + 0x05f90000
[SPEW ] 0x521157b8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5ff90000 + 0x00060000
[SPEW ] 0x521157e8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5fff0000 + 0x00005000
[SPEW ] 0x52115818, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5fff5000 + 0x0000b000
[SPEW ] 0x52115848, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource SYSTEM_MEMORY, attribute 3c07
[SPEW ] 0x100000000 + 0x39e300000
[SPEW ] 0x52115878, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x49e300000 + 0x01040000
[SPEW ] 0x521158a8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x49f340000 + 0x00cc0000
[SPEW ] 0x521158d8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x53000000 + 0x01000000
[SPEW ] Owner GUID: 5fc7897a-5aff-4c61-aa7addcfa918430c (Unknown GUID)
[SPEW ] 0x52115908, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x52ffe000 + 0x00002000
[SPEW ] Owner GUID: 73ff4f56-aa8e-4451-b31636353667ad44 (BOOTLOADER_TOLUM)
[SPEW ] 0x52115938, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x51ffe000 + 0x01000000
[SPEW ] Owner GUID: 69a79759-1373-4367-a6c4c7f59efd986e (FSP_RESERVED_MEMORY)
[SPEW ] 0x52115968, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52115998, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521159c8, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] f2784616-b9bf-4e1e-99e09626da7ea5f5: Unknown GUID
[SPEW ] 0x521159e8, 0x00000688 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116070, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116088, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521160a8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521160d8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116108, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 614facf7-1ac6-4b15-a88c2c1a70d777ec: Unknown GUID
[SPEW ] 0x52116138, 0x00000080 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521161b8, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d178f11d-8716-418e-a131967d2ac42843: Unknown GUID
[SPEW ] 0x52116248, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 58eb6a19-3699-4c68-a836dacd8edcad4a: Unknown GUID
[SPEW ] 0x52116268, 0x00000350 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521165b8, 0x00000360 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 9e9f374b-8f16-4230-98245846ee766a97: Unknown GUID
[SPEW ] 0x52116918, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116948, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116978, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521169a8, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116bb0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116be0, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c08, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c20, 0x00000010 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c30, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c50, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116c80, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116cb0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116ce0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116d10, 0x00000e30 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ea296d92-0b69-423c-8c2833b4e0a91268: Unknown GUID
[SPEW ] 0x52117b40, 0x0000fff8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 42494c41-4002-403b-87e13feb13c5669a: Unknown GUID
[SPEW ] 0x52127b38, 0x0000fff8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 4118fc0e-353d-4726-97c053cd92b64925: Unknown GUID
[SPEW ] 0x52137b30, 0x00000070 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 6d5cd69d-fb24-4461-aa328ee1b303319c: Unknown GUID
[SPEW ] 0x52137ba0, 0x00000008 bytes: HOB_TYPE_END_OF_HOB_LIST
[SPEW ] === End of FSP HOBs ===
[DEBUG] 0x0000000000000508: IA32_MTRRCAP: WC, FIX, 8 variable MTRRs
[DEBUG] 0x0000000000000c00: IA32_MTRR_DEF_TYPE: E, FE, UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX64K_00000
[DEBUG] 0x00000000 - 0x0007ffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX16K_80000
[DEBUG] 0x00080000 - 0x0009ffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_A0000
[DEBUG] 0x000a0000 - 0x000bffff: UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C0000
[DEBUG] 0x000c0000 - 0x000c7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C8000
[DEBUG] 0x000c8000 - 0x000cffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D0000
[DEBUG] 0x000d0000 - 0x000d7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_D8000
[DEBUG] 0x000d8000 - 0x000dffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_E0000
[DEBUG] 0x000e0000 - 0x000e7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_E8000
[DEBUG] 0x000e8000 - 0x000effff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_F0000
[DEBUG] 0x000f0000 - 0x000f7fff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_F8000
[DEBUG] 0x000f8000 - 0x000fffff: WB
[DEBUG] 0x0000000000000006: PHYBASE0: Address = 0x0000000000000000, WB
[DEBUG] 0x0000ffffc0000800: PHYMASK0: Length = 0x0000000040000000, Valid
[DEBUG] 0x0000000040000006: PHYBASE1: Address = 0x0000000040000000, WB
[DEBUG] 0x0000ffffe0000800: PHYMASK1: Length = 0x0000000020000000, Valid
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x0000ffffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
[DEBUG] 0x0000000100000006: PHYBASE3: Address = 0x0000000100000000, WB
[DEBUG] 0x0000ffff00000800: PHYMASK3: Length = 0x0000000100000000, Valid
[DEBUG] 0x0000000200000006: PHYBASE4: Address = 0x0000000200000000, WB
[DEBUG] 0x0000fffe00000800: PHYMASK4: Length = 0x0000000200000000, Valid
[DEBUG] 0x0000000400000006: PHYBASE5: Address = 0x0000000400000000, WB
[DEBUG] 0x0000ffff00000800: PHYMASK5: Length = 0x0000000100000000, Valid
[DEBUG] 0x0000000000000000: PHYBASE6
[DEBUG] 0x0000000000000000: PHYMASK6: Disabled
[DEBUG] 0x0000000000000000: PHYBASE7
[DEBUG] 0x0000000000000000: PHYMASK7: Disabled
[SPEW ] 0x000000f0: notify_params->phase
[SPEW ] Calling FspNotify: 0x51f1e378
[SPEW ] 0x51fcbf7c: notify_params
[INFO ] Timestamp - calling FspNotify(EndOfFirmware): 32126328
[INFO ] POST: 0x88
NotifyPhaseApi() - Begin [Phase: 000000F0]
FSP End of Firmware ...
Install PPI: BD44F629-EAE7-4198-87F1-39FAB0FD717E
NotifyPhaseApi() - End [Status: 0x00000000]
[INFO ] Timestamp - returning from FspNotify(EndOfFirmware): 32148689
[INFO ] POST: 0x89
[SPEW ] FspNotify returned 0x00000000
[SPEW ] === FSP HOBs ===
[SPEW ] 0x520fe000: hob_list_ptr
[SPEW ] 0x520fe000, 0x00000038 bytes: HOB_TYPE_HANDOFF
[SPEW ] 0x520fe038, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe060, 0x00000108 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe168, 0x00000108 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe270, 0x00000088 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe2f8, 0x00000088 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe380, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe588, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe5a8, 0x00000068 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x520fe610, 0x000011e8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ea296d92-0b69-423c-8c2833b4e0a91268: Unknown GUID
[SPEW ] 0x520ff7f8, 0x00005658 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 9b3ada4f-ae56-4c24-8deaf03b7558ae50: Unknown GUID
[SPEW ] 0x52104e50, 0x00000038 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] bea654e4-4770-4b8d-9524c0f0dbe9e986: Unknown GUID
[SPEW ] 0x52104e88, 0x00000038 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] c8a27c35-c539-4def-90a9a0bd6ce75b17: Unknown GUID
[SPEW ] 0x52104ec0, 0x000037d8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52108698, 0x000003f0 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52108a88, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x521090c0, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x521096f8, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109788, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109818, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52109e50, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x5210a488, 0x00000638 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x5210aac0, 0x00001018 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 30b174f3-7712-4cca-bd13d0b8a8801997: Unknown GUID
[SPEW ] 0x5210bad8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x5210bb08, 0x00000210 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 0cdfa7da-0d0b-41f0-b98b0f6359c0857f: Unknown GUID
[SPEW ] 0x5210bd18, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd30, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd48, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd60, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd78, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bd90, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bda8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdc0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdd8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210bdf0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be08, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be20, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be38, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be50, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210be68, 0x00000e20 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ace4c26a-4a31-4861-8ef9dad07cfd391f: Unknown GUID
[SPEW ] 0x5210cc88, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cca0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccb8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccd0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cce8, 0x00000010 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210ccf8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210cd10, 0x000008f8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 26ab8e31-6c47-480a-a0391e043fa793cd: Unknown GUID
[SPEW ] 0x5210d608, 0x00000058 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210d660, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x5210d678, 0x00004b98 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52112210, 0x000016f8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 03eb1d90-ce14-40d8-a6ba103a8d7bd32d: Unknown GUID
[SPEW ] 0x52113908, 0x00000420 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113d28, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d97d161a-16cd-4ada-b9f6aec3f9fccc2c: Unknown GUID
[SPEW ] 0x52113d58, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113d70, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52113f78, 0x00000228 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521141a0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521141d0, 0x000000d8 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521142a8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521142c0, 0x00000288 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114548, 0x00000138 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 1bce3d14-a5fe-4a0b-9a8d69ca5d9838d3: Unknown GUID
[SPEW ] 0x52114680, 0x00000828 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 89d85219-2ca1-42de-99327488df4f5f83: Unknown GUID
[SPEW ] 0x52114ea8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ec0, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ed8, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114ef0, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52114f10, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] a90f3dfd-db05-4e73-86750dd10f669e0f: Unknown GUID
[SPEW ] 0x52114f40, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52114f70, 0x000002b0 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115220, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115228, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115230, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115238, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115240, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115248, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115250, 0x00000008 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115258, 0x00000110 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52115368, 0x00000188 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521154f0, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521156f8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource SYSTEM_MEMORY, attribute 3c07
[SPEW ] 0x00000000 + 0x54000000
[SPEW ] 0x52115728, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x54000000 + 0x04000000
[SPEW ] 0x52115758, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x58000000 + 0x02000000
[SPEW ] 0x52115788, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5a000000 + 0x05f90000
[SPEW ] 0x521157b8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5ff90000 + 0x00060000
[SPEW ] 0x521157e8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5fff0000 + 0x00005000
[SPEW ] 0x52115818, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x5fff5000 + 0x0000b000
[SPEW ] 0x52115848, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource SYSTEM_MEMORY, attribute 3c07
[SPEW ] 0x100000000 + 0x39e300000
[SPEW ] 0x52115878, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x49e300000 + 0x01040000
[SPEW ] 0x521158a8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 0
[SPEW ] 0x49f340000 + 0x00cc0000
[SPEW ] 0x521158d8, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x53000000 + 0x01000000
[SPEW ] Owner GUID: 5fc7897a-5aff-4c61-aa7addcfa918430c (Unknown GUID)
[SPEW ] 0x52115908, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x52ffe000 + 0x00002000
[SPEW ] Owner GUID: 73ff4f56-aa8e-4451-b31636353667ad44 (BOOTLOADER_TOLUM)
[SPEW ] 0x52115938, 0x00000030 bytes: HOB_TYPE_RESOURCE_DESCRIPTOR
[SPEW ] Resource MEMORY_RESERVED, attribute 3c07
[SPEW ] 0x51ffe000 + 0x01000000
[SPEW ] Owner GUID: 69a79759-1373-4367-a6c4c7f59efd986e (FSP_RESERVED_MEMORY)
[SPEW ] 0x52115968, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52115998, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521159c8, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] f2784616-b9bf-4e1e-99e09626da7ea5f5: Unknown GUID
[SPEW ] 0x521159e8, 0x00000688 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116070, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116088, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521160a8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521160d8, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116108, 0x00000030 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 614facf7-1ac6-4b15-a88c2c1a70d777ec: Unknown GUID
[SPEW ] 0x52116138, 0x00000080 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521161b8, 0x00000090 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] d178f11d-8716-418e-a131967d2ac42843: Unknown GUID
[SPEW ] 0x52116248, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 58eb6a19-3699-4c68-a836dacd8edcad4a: Unknown GUID
[SPEW ] 0x52116268, 0x00000350 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x521165b8, 0x00000360 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 9e9f374b-8f16-4230-98245846ee766a97: Unknown GUID
[SPEW ] 0x52116918, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116948, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116978, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x521169a8, 0x00000208 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116bb0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116be0, 0x00000028 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c08, 0x00000018 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c20, 0x00000010 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c30, 0x00000020 bytes: HOB_TYPE_MEMORY_POOL
[SPEW ] 0x52116c50, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116c80, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116cb0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116ce0, 0x00000030 bytes: HOB_TYPE_MEMORY_ALLOCATION
[SPEW ] 0x52116d10, 0x00000e30 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] ea296d92-0b69-423c-8c2833b4e0a91268: Unknown GUID
[SPEW ] 0x52117b40, 0x0000fff8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 42494c41-4002-403b-87e13feb13c5669a: Unknown GUID
[SPEW ] 0x52127b38, 0x0000fff8 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 4118fc0e-353d-4726-97c053cd92b64925: Unknown GUID
[SPEW ] 0x52137b30, 0x00000070 bytes: HOB_TYPE_GUID_EXTENSION
[SPEW ] 6d5cd69d-fb24-4461-aa328ee1b303319c: Unknown GUID
[SPEW ] 0x52137ba0, 0x00000008 bytes: HOB_TYPE_END_OF_HOB_LIST
[SPEW ] === End of FSP HOBs ===
[DEBUG] 0x0000000000000508: IA32_MTRRCAP: WC, FIX, 8 variable MTRRs
[DEBUG] 0x0000000000000c00: IA32_MTRR_DEF_TYPE: E, FE, UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX64K_00000
[DEBUG] 0x00000000 - 0x0007ffff: WB
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX16K_80000
[DEBUG] 0x00080000 - 0x0009ffff: WB
[DEBUG] 0x0000000000000000: IA32_MTRR_FIX16K_A0000
[DEBUG] 0x000a0000 - 0x000bffff: UC
[DEBUG] 0x0606060606060606: IA32_MTRR_FIX4K_C0000
[DEBUG] 0x000c0000 - 0x000c7fff: WB
CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.8 | VT102 | Offline | ttyUSB0
CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.8 | VT102 | Offline | ttyUSB0
[-- Attachment #4: .config --]
[-- Type: application/octet-stream, Size: 19212 bytes --]
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
CONFIG_OPTION_BACKEND_NONE=y
CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_COMPRESS_PRERAM_STAGES=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
CONFIG_TIMESTAMPS_ON_CONSOLE=y
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
# CONFIG_NO_STAGE_CACHE is not set
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
CONFIG_VENDOR_AMD=y
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SCALEWAY is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="MAYAN"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="amd/mayan"
CONFIG_VGA_BIOS_ID="1002,1205"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE="src/mainboard/amd/mayan/board.fmd"
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="AMD"
CONFIG_CBFS_SIZE=0x02000000
CONFIG_CONSOLE_SERIAL=y
CONFIG_MAX_CPUS=16
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
# CONFIG_POST_DEVICE is not set
CONFIG_POST_IO=y
CONFIG_UART_FOR_CONSOLE=0
# CONFIG_BOARD_AMD_BILBY is not set
#
# Birman
#
# CONFIG_BOARD_AMD_BIRMAN_MORGANA is not set
# CONFIG_BOARD_AMD_BIRMAN_GLINDA is not set
# CONFIG_BOARD_AMD_CHAUSIE is not set
# CONFIG_BOARD_AMD_GARDENIA is not set
# CONFIG_BOARD_AMD_MAJOLICA is not set
# CONFIG_BOARD_AMD_MANDOLIN is not set
# CONFIG_BOARD_AMD_CEREME is not set
#
# Mayan
#
CONFIG_BOARD_AMD_MAYAN_MORGANA=y
# CONFIG_BOARD_AMD_PADEMELON is not set
CONFIG_EFS_SPI_READ_MODE=3
CONFIG_EFS_SPI_SPEED=0
CONFIG_EFS_SPI_MICRON_FLAG=0
CONFIG_NORMAL_READ_SPI_SPEED=1
CONFIG_ALT_SPI_SPEED=1
CONFIG_TPM_SPI_SPEED=1
CONFIG_DEVICETREE="devicetree_morgana.cb"
CONFIG_AMD_FWM_POSITION_INDEX=5
# CONFIG_VBOOT is not set
CONFIG_VBOOT_VBNV_OFFSET=0x2A
CONFIG_MAYAN_HAVE_MCHP_FW=y
CONFIG_MAYAN_MCHP_SIG_FILE="3rdparty/blobs/mainboard/amd/mayan/EC_mayan_sig.bin"
CONFIG_MAYAN_MCHP_FW_FILE="3rdparty/blobs/mainboard/amd/mayan/EC_mayan.bin"
CONFIG_MAYAN_MCHP_FW_OFFSET=0x81000
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_VGA_BIOS=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="AMD"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0x1600
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_CONSOLE_POST=y
CONFIG_MEMLAYOUT_LD_FILE="src/soc/amd/common/block/cpu/noncar/memlayout.ld"
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xE0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_EDK2_BOOT_TIMEOUT=2
CONFIG_AMDFW_CONFIG_FILE="src/soc/amd/morgana/fw.cfg"
# CONFIG_HAVE_SPL_FILE is not set
CONFIG_VGA_BIOS_FILE="3rdparty/amd_blobs/morgana/Vbios.bin"
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MAYAN"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EDK2_BOOTSPLASH_FILE="Documentation/coreboot_logo.bmp"
CONFIG_BOARD_ROMSIZE_KB_32768=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
CONFIG_COREBOOT_ROMSIZE_KB_32768=y
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=32768
CONFIG_ROM_SIZE=0x02000000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_SOC_SPECIFIC_OPTIONS=y
CONFIG_CHIPSET_DEVICETREE="soc/amd/morgana/chipset.cb"
CONFIG_FSP_M_FILE="3rdparty/amd_blobs/morgana/MORGANA_SERIAL_M.fd"
CONFIG_FSP_S_FILE="3rdparty/amd_blobs/morgana/MORGANA_SERIAL_S.fd"
CONFIG_EARLY_RESERVED_DRAM_BASE=0x2000000
CONFIG_EARLYRAM_BSP_STACK_SIZE=0x1000
CONFIG_PSP_APOB_DRAM_ADDRESS=0x2001000
CONFIG_PSP_APOB_DRAM_SIZE=0x1E000
CONFIG_PSP_SHAREDMEM_BASE=0x0
CONFIG_PSP_SHAREDMEM_SIZE=0x0
CONFIG_PRE_X86_CBMEM_CONSOLE_SIZE=0x1600
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2040000
CONFIG_ROMSTAGE_SIZE=0x80000
CONFIG_FSP_M_ADDR=0x20C0000
CONFIG_FSP_M_SIZE=0xC0000
CONFIG_FSP_TEMP_RAM_SIZE=0x40000
CONFIG_VERSTAGE_ADDR=0x2000000
# CONFIG_ASYNC_FILE_LOADING is not set
CONFIG_CONSOLE_UART_BASE_ADDRESS=0xfedc9000
CONFIG_SMM_TSEG_SIZE=0x1000000
CONFIG_SMM_RESERVED_SIZE=0x180000
CONFIG_SMM_MODULE_STACK_SIZE=0x800
CONFIG_ACPI_BERT=y
CONFIG_ACPI_BERT_SIZE=0x4000
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=150
CONFIG_ACPI_SSDT_PSD_INDEPENDENT=y
# CONFIG_PSP_DISABLE_POSTCODES is not set
CONFIG_PSP_POSTCODES_ON_ESPI=y
CONFIG_PSP_LOAD_MP2_FW=y
CONFIG_PSP_UNLOCK_SECURE_DEBUG=y
# CONFIG_HAVE_PSP_WHITELIST_FILE is not set
CONFIG_PSP_SOFTFUSE_BITS="36 14"
CONFIG_SOC_AMD_MORGANA=y
#
# PSP Configuration Options
#
#
# AMD Firmware Directory Table set to location for 16MB ROM
#
# end of PSP Configuration Options
# CONFIG_VGA_BIOS_SECOND is not set
CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_FSP_HEADER_PATH=""
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_TTYS0_BASE=0x3f8
CONFIG_TTYS0_LCS=3
CONFIG_SOC_AMD_COMMON=y
CONFIG_SOC_AMD_COMMON_BLOCK_ACP_GEN2=y
CONFIG_SOC_AMD_COMMON_BLOCK_ACPI=y
CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_ALIB=y
CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPPC=y
CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO=y
CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_IVRS=y
CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO=y
CONFIG_SOC_AMD_COMMON_BLOCK_AOAC=y
CONFIG_SOC_AMD_COMMON_BLOCK_APOB=y
CONFIG_SOC_AMD_COMMON_BLOCK_APOB_HASH=y
CONFIG_SOC_AMD_COMMON_BLOCK_NONCAR=y
CONFIG_SOC_AMD_COMMON_BLOCK_MCA_COMMON=y
CONFIG_SOC_AMD_COMMON_BLOCK_MCAX=y
CONFIG_SOC_AMD_COMMON_BLOCK_SMM=y
CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H=y
CONFIG_SOC_AMD_COMMON_BLOCK_UCODE=y
CONFIG_SOC_AMD_COMMON_BLOCK_DATA_FABRIC=y
CONFIG_SOC_AMD_COMMON_BLOCK_EMMC=y
CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS=y
CONFIG_SOC_AMD_COMMON_BLOCK_GRAPHICS=y
CONFIG_SOC_AMD_COMMON_BLOCK_I2C=y
CONFIG_SOC_AMD_COMMON_BLOCK_I23C_PAD_CTRL=y
CONFIG_SOC_AMD_COMMON_BLOCK_IOMMU=y
CONFIG_SOC_AMD_COMMON_BLOCK_LPC=y
CONFIG_PROVIDES_ROM_SHARING=y
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_SOC_AMD_COMMON_BLOCK_HAS_ESPI=y
CONFIG_SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES=y
CONFIG_SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLE=y
CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI=y
CONFIG_SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN=y
CONFIG_SOC_AMD_COMMON_BLOCK_PCI=y
CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF=y
CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER=y
CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ=y
CONFIG_SOC_AMD_COMMON_BLOCK_PM=y
CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE=y
CONFIG_SOC_AMD_COMMON_BLOCK_PSP=y
CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2=y
# CONFIG_PSP_PLATFORM_SECURE_BOOT is not set
CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS=y
CONFIG_SOC_AMD_COMMON_BLOCK_SMI=y
CONFIG_SOC_AMD_COMMON_BLOCK_SMN=y
CONFIG_SOC_AMD_COMMON_BLOCK_SMU=y
CONFIG_SOC_AMD_COMMON_BLOCK_SPI=y
# CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG is not set
CONFIG_SOC_AMD_COMMON_BLOCK_UART=y
CONFIG_AMD_SOC_CONSOLE_UART=y
CONFIG_SOC_AMD_COMMON_FSP_DMI_TABLES=y
CONFIG_SOC_AMD_COMMON_FSP_CCX_CPPC_HOB=y
CONFIG_SOC_AMD_COMMON_FSP_PCI=y
#
# CPU
#
CONFIG_PARALLEL_MP=y
CONFIG_PARALLEL_MP_AP_WORK=y
CONFIG_X86_SMM_SKIP_RELOCATION_HANDLER=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_SYNC_LFENCE=y
CONFIG_LOGICAL_CPUS=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_X86_AMD_FIXED_MTRRS=y
CONFIG_X86_INIT_NEED_1_SIPI=y
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
#
# Northbridge
#
#
# Southbridge
#
# CONFIG_PCIEXP_HOTPLUG is not set
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_ACPI=y
CONFIG_UDK_BASE=y
CONFIG_UDK_2017_BINDING=y
CONFIG_UDK_2013_VERSION=2013
CONFIG_UDK_2017_VERSION=2017
CONFIG_UDK_202005_VERSION=202005
CONFIG_UDK_202111_VERSION=202111
CONFIG_UDK_VERSION=2017
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESET_VECTOR_IN_RAM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_NUM_IPI_STARTS=2
CONFIG_PC80_SYSTEM=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_NO_TSC=y
CONFIG_IDT_IN_EVERY_STAGE=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES=y
# end of Chipset
#
# Devices
#
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_HAVE_FSP_GOP=y
CONFIG_VGA_ROM_RUN_DEFAULT=y
# CONFIG_VGA_ROM_RUN is not set
CONFIG_RUN_FSP_GOP=y
# CONFIG_NO_GFX_INIT is not set
#
# Display
#
CONFIG_WANT_LINEAR_FRAMEBUFFER=y
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
CONFIG_BOOTSPLASH=y
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
# CONFIG_VGA_BIOS_DGPU is not set
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_XHCI_UTILS=y
CONFIG_NO_LPDDR4=y
CONFIG_NO_DDR4=y
CONFIG_NO_DDR3=y
CONFIG_NO_DDR2=y
CONFIG_USE_DDR5=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_DRIVERS_UART=y
CONFIG_NO_UART_ON_SUPERIO=y
CONFIG_UART_OVERRIDE_REFCLK=y
CONFIG_DRIVERS_UART_8250MEM=y
CONFIG_DRIVERS_UART_8250MEM_32=y
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_DISPLAY_HOBS=y
CONFIG_DISPLAY_UPD_DATA=y
CONFIG_PLATFORM_USES_FSP2_0=y
CONFIG_PLATFORM_USES_FSP2_X86_32=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_T_LOCATION=0xfffe0000
CONFIG_FSP_S_CBFS="MORGANA_SERIAL_S.fd"
CONFIG_FSP_M_CBFS="MORGANA_SERIAL_M.fd"
# CONFIG_FSP_FULL_FD is not set
CONFIG_FSP_T_RESERVED_SIZE=0x0
CONFIG_FSP_COMPRESS_FSP_S_LZ4=y
CONFIG_FSP_COMPRESS_FSP_M_LZMA=y
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
CONFIG_DISPLAY_FSP_TIMESTAMPS=y
CONFIG_INTEL_GMA_OPREGION_2_0=y
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_USB_ACPI=y
CONFIG_DRIVERS_USB_PCI_XHCI=y
CONFIG_DRIVERS_WIFI_GENERIC=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
# end of Memory initialization
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# end of Security
CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
#
# memory mapped, 8250-compatible
#
# CONFIG_CONSOLE_SERIAL_921600 is not set
# CONFIG_CONSOLE_SERIAL_460800 is not set
# CONFIG_CONSOLE_SERIAL_230400 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
CONFIG_TTYS0_BAUD=115200
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_SPI_FLASH is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_IOAPIC=y
CONFIG_GFXUMA=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
# CONFIG_PAYLOAD_NONE is not set
# CONFIG_PAYLOAD_ELF is not set
# CONFIG_PAYLOAD_BOOTBOOT is not set
# CONFIG_PAYLOAD_FILO is not set
# CONFIG_PAYLOAD_GRUB2 is not set
# CONFIG_PAYLOAD_SEAGRUB is not set
# CONFIG_PAYLOAD_LINUXBOOT is not set
# CONFIG_PAYLOAD_SEABIOS is not set
# CONFIG_PAYLOAD_UBOOT is not set
# CONFIG_PAYLOAD_YABITS is not set
CONFIG_PAYLOAD_EDK2=y
# CONFIG_PAYLOAD_LINUX is not set
CONFIG_PAYLOAD_FILE="build/UEFIPAYLOAD.fd"
CONFIG_PAYLOAD_OPTIONS=""
CONFIG_EDK2_UEFIPAYLOAD=y
# CONFIG_EDK2_REPO_MRCHROMEBOX is not set
CONFIG_EDK2_REPO_OFFICIAL=y
# CONFIG_EDK2_REPO_CUSTOM is not set
CONFIG_EDK2_REPOSITORY="https://github.com/tianocore/edk2"
CONFIG_EDK2_TAG_OR_REV="origin/master"
CONFIG_EDK2_DEBUG=y
# CONFIG_EDK2_RELEASE is not set
CONFIG_EDK2_VERBOSE_BUILD=y
# CONFIG_EDK2_ABOVE_4G_MEMORY is not set
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
# CONFIG_EDK2_CBMEM_LOGGING is not set
# CONFIG_EDK2_FOLLOW_BGRT_SPEC is not set
# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
CONFIG_EDK2_HAVE_EFI_SHELL=y
CONFIG_EDK2_PRIORITIZE_INTERNAL=y
CONFIG_EDK2_PS2_SUPPORT=y
CONFIG_EDK2_SD_MMC_TIMEOUT=10
CONFIG_EDK2_SERIAL_SUPPORT=y
CONFIG_EDK2_CUSTOM_BUILD_PARAMS=""
# CONFIG_PXE is not set
# CONFIG_COMPRESSED_PAYLOAD_NONE is not set
CONFIG_COMPRESSED_PAYLOAD_LZMA=y
# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set
CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
#
# Secondary Payloads
#
# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set
# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set
# CONFIG_TINT_SECONDARY_PAYLOAD is not set
# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set
# end of Secondary Payloads
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
CONFIG_DISPLAY_MTRRS=y
#
# BLOB Debug Settings
#
CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
CONFIG_DISPLAY_FSP_HEADER=y
# CONFIG_VERIFY_HOBS is not set
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
# CONFIG_FATAL_ASSERTS is not set
CONFIG_DEBUG_CBFS=y
CONFIG_DEBUG_SMI=y
# CONFIG_DEBUG_PERIODIC_SMI is not set
CONFIG_DEBUG_MALLOC=y
CONFIG_DEBUG_RESOURCES=y
CONFIG_DEBUG_CONSOLE_INIT=y
# CONFIG_DEBUG_SPI_FLASH is not set
CONFIG_DEBUG_FUNC=y
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_NO_XIP_EARLY_STAGES=y
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 18:27 ` ritul guru
@ 2023-02-07 20:35 ` Sean Rhodes
2023-02-07 20:49 ` ritul guru
0 siblings, 1 reply; 14+ messages in thread
From: Sean Rhodes @ 2023-02-07 20:35 UTC (permalink / raw)
To: devel, ritul.bits
[-- Attachment #1: Type: text/plain, Size: 3112 bytes --]
Why the edk2 changes? Just to fix this issue?
Have you seen L36 of payloads/external/edk2/Kconfig
On Tue, 7 Feb 2023 at 20:30, ritul guru <ritul.bits@gmail.com> wrote:
>
>
> Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
> Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
> ProtectUefiImageCommon - 0x51A3E1C0
> - 0x0000000051DD1000 - 0x0000000000008000
> SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
> (0x0000000000004008)
> SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
> (0x0000000000020008)
> SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
> (0x0000000000004008)
> PROGRESS CODE: V03040002 I0
>
> ASSERT_EFI_ERROR (Status = Device Error)
>
> *ASSERT [PcRtc]
> /home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
> getting above assert after changed to FD_BASE to below value,
> This error is coming while booting to coreboot with edk2 payload:
>
> UefiPayloadPkg/UefiPayloadPkg.fdf
> DEFINE FD_BASE = 0x02182000
>
> need to change FD_BASE, as it was going outside Available memory.
> any hint would be appreciated.
>
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
>
> On Tue, Feb 7, 2023 at 10:09 PM ritul guru <ritul.bits@gmail.com> wrote:
>
>> UefiPayloadPkg/UefiPayloadPkg.fdf
>> DEFINE FD_BASE = 0x00800000
>>
>> Is the above address correct in uefipaylaod?
>> As observing some regions are getting out of limit of FD limit,
>>
>> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert in
>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>
>>
>>
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>>
>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
>>
>>> Hi,
>>> I am building edk2 payload and getting below warning for
>>> PcdRtcIndexRegister,
>>> and if try to boot to then observing that there is assert at:
>>>
>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>
>>> DXE_ASSERT!:
>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>> (141): !EFI_ERROR (Status)
>>>
>>>
>>>
>>>
>>> build time warning:
>>> Active Platform =
>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>> .build: : warning: The PCD was not specified by any INF module in the
>>> platform for the given architecture.
>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>> Platform: [UefiPayloadPkg.dsc]
>>> Arch: ['IA32']
>>> build: : warning: The PCD was not specified by any INF module in the
>>> platform for the given architecture.
>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>> Platform: [UefiPayloadPkg.dsc]
>>> Arch: ['IA32']
>>> . done!
>>>
>>>
>>>
>>>
>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>
>>
>
>
[-- Attachment #2: Type: text/html, Size: 8875 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 20:35 ` [edk2-devel] " Sean Rhodes
@ 2023-02-07 20:49 ` ritul guru
2023-02-07 20:51 ` ritul guru
0 siblings, 1 reply; 14+ messages in thread
From: ritul guru @ 2023-02-07 20:49 UTC (permalink / raw)
To: Sean Rhodes; +Cc: devel
[-- Attachment #1: Type: text/plain, Size: 3641 bytes --]
I do not get debug logs from edk2 payload even though debug payload is
selected in menuconfig of coreboot.
and also updated FD_BASE, if not then getting GCD assert while adding
regions in phit table.
below path should be give at L36 for custom edk2 repo?
payloads/external/edk2/workspace/tianocore/
*Thanks & RegardsRitul Guru+91-9916513186*
On Wed, Feb 8, 2023 at 2:06 AM Sean Rhodes <sean@starlabs.systems> wrote:
> Why the edk2 changes? Just to fix this issue?
>
> Have you seen L36 of payloads/external/edk2/Kconfig
>
> On Tue, 7 Feb 2023 at 20:30, ritul guru <ritul.bits@gmail.com> wrote:
>
>>
>>
>> Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
>> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
>> Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
>> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
>> ProtectUefiImageCommon - 0x51A3E1C0
>> - 0x0000000051DD1000 - 0x0000000000008000
>> SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
>> (0x0000000000004008)
>> SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
>> (0x0000000000020008)
>> SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
>> (0x0000000000004008)
>> PROGRESS CODE: V03040002 I0
>>
>> ASSERT_EFI_ERROR (Status = Device Error)
>>
>> *ASSERT [PcRtc]
>> /home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
>> getting above assert after changed to FD_BASE to below value,
>> This error is coming while booting to coreboot with edk2 payload:
>>
>> UefiPayloadPkg/UefiPayloadPkg.fdf
>> DEFINE FD_BASE = 0x02182000
>>
>> need to change FD_BASE, as it was going outside Available memory.
>> any hint would be appreciated.
>>
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>>
>> On Tue, Feb 7, 2023 at 10:09 PM ritul guru <ritul.bits@gmail.com> wrote:
>>
>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>> DEFINE FD_BASE = 0x00800000
>>>
>>> Is the above address correct in uefipaylaod?
>>> As observing some regions are getting out of limit of FD limit,
>>>
>>> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert
>>> in
>>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>>
>>>
>>>
>>>
>>>
>>>
>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>
>>>
>>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
>>>
>>>> Hi,
>>>> I am building edk2 payload and getting below warning for
>>>> PcdRtcIndexRegister,
>>>> and if try to boot to then observing that there is assert at:
>>>>
>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>
>>>> DXE_ASSERT!:
>>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>>> (141): !EFI_ERROR (Status)
>>>>
>>>>
>>>>
>>>>
>>>> build time warning:
>>>> Active Platform =
>>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>>> .build: : warning: The PCD was not specified by any INF module in the
>>>> platform for the given architecture.
>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>>> Platform: [UefiPayloadPkg.dsc]
>>>> Arch: ['IA32']
>>>> build: : warning: The PCD was not specified by any INF module in the
>>>> platform for the given architecture.
>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>>> Platform: [UefiPayloadPkg.dsc]
>>>> Arch: ['IA32']
>>>> . done!
>>>>
>>>>
>>>>
>>>>
>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>
>>>
>>
>>
[-- Attachment #2: Type: text/html, Size: 10443 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 20:49 ` ritul guru
@ 2023-02-07 20:51 ` ritul guru
2023-02-07 22:10 ` Sean Rhodes
0 siblings, 1 reply; 14+ messages in thread
From: ritul guru @ 2023-02-07 20:51 UTC (permalink / raw)
To: Sean Rhodes; +Cc: devel
[-- Attachment #1: Type: text/plain, Size: 4161 bytes --]
fatal: repository 'payloads/external/edk2/workspace/tianocore' does not
exist
make[1]: *** [Makefile:123:
/home/amd/src/phx2/coreboot_phx2/coreboot/payloads/external/edk2/workspace/edk2]
Error 128
make: *** [payloads/external/Makefile.inc:158: build/UEFIPAYLOAD.fd] Error 2
*Thanks & RegardsRitul Guru+91-9916513186*
On Wed, Feb 8, 2023 at 2:19 AM ritul guru <ritul.bits@gmail.com> wrote:
> I do not get debug logs from edk2 payload even though debug payload is
> selected in menuconfig of coreboot.
> and also updated FD_BASE, if not then getting GCD assert while adding
> regions in phit table.
>
> below path should be give at L36 for custom edk2 repo?
> payloads/external/edk2/workspace/tianocore/
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
>
> On Wed, Feb 8, 2023 at 2:06 AM Sean Rhodes <sean@starlabs.systems> wrote:
>
>> Why the edk2 changes? Just to fix this issue?
>>
>> Have you seen L36 of payloads/external/edk2/Kconfig
>>
>> On Tue, 7 Feb 2023 at 20:30, ritul guru <ritul.bits@gmail.com> wrote:
>>
>>>
>>>
>>> Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
>>> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
>>> Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
>>> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
>>> ProtectUefiImageCommon - 0x51A3E1C0
>>> - 0x0000000051DD1000 - 0x0000000000008000
>>> SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
>>> (0x0000000000004008)
>>> SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
>>> (0x0000000000020008)
>>> SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
>>> (0x0000000000004008)
>>> PROGRESS CODE: V03040002 I0
>>>
>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>
>>> *ASSERT [PcRtc]
>>> /home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
>>> getting above assert after changed to FD_BASE to below value,
>>> This error is coming while booting to coreboot with edk2 payload:
>>>
>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>> DEFINE FD_BASE = 0x02182000
>>>
>>> need to change FD_BASE, as it was going outside Available memory.
>>> any hint would be appreciated.
>>>
>>>
>>>
>>>
>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>
>>>
>>> On Tue, Feb 7, 2023 at 10:09 PM ritul guru <ritul.bits@gmail.com> wrote:
>>>
>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>> DEFINE FD_BASE = 0x00800000
>>>>
>>>> Is the above address correct in uefipaylaod?
>>>> As observing some regions are getting out of limit of FD limit,
>>>>
>>>> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert
>>>> in
>>>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>
>>>>
>>>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com> wrote:
>>>>
>>>>> Hi,
>>>>> I am building edk2 payload and getting below warning for
>>>>> PcdRtcIndexRegister,
>>>>> and if try to boot to then observing that there is assert at:
>>>>>
>>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>>
>>>>> DXE_ASSERT!:
>>>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>>>> (141): !EFI_ERROR (Status)
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> build time warning:
>>>>> Active Platform =
>>>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>>>> .build: : warning: The PCD was not specified by any INF module in the
>>>>> platform for the given architecture.
>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>> Arch: ['IA32']
>>>>> build: : warning: The PCD was not specified by any INF module in the
>>>>> platform for the given architecture.
>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>> Arch: ['IA32']
>>>>> . done!
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>
>>>>
>>>
>>>
[-- Attachment #2: Type: text/html, Size: 11766 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 20:51 ` ritul guru
@ 2023-02-07 22:10 ` Sean Rhodes
2023-02-08 3:13 ` ritul guru
0 siblings, 1 reply; 14+ messages in thread
From: Sean Rhodes @ 2023-02-07 22:10 UTC (permalink / raw)
To: ritul guru; +Cc: devel
[-- Attachment #1: Type: text/plain, Size: 4449 bytes --]
L36 is help text that says what you are trying to do, wont work
On Tue, 7 Feb 2023 at 20:51, ritul guru <ritul.bits@gmail.com> wrote:
> fatal: repository 'payloads/external/edk2/workspace/tianocore' does not
> exist
> make[1]: *** [Makefile:123:
> /home/amd/src/phx2/coreboot_phx2/coreboot/payloads/external/edk2/workspace/edk2]
> Error 128
> make: *** [payloads/external/Makefile.inc:158: build/UEFIPAYLOAD.fd] Error
> 2
>
>
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
>
> On Wed, Feb 8, 2023 at 2:19 AM ritul guru <ritul.bits@gmail.com> wrote:
>
>> I do not get debug logs from edk2 payload even though debug payload is
>> selected in menuconfig of coreboot.
>> and also updated FD_BASE, if not then getting GCD assert while adding
>> regions in phit table.
>>
>> below path should be give at L36 for custom edk2 repo?
>> payloads/external/edk2/workspace/tianocore/
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>>
>> On Wed, Feb 8, 2023 at 2:06 AM Sean Rhodes <sean@starlabs.systems> wrote:
>>
>>> Why the edk2 changes? Just to fix this issue?
>>>
>>> Have you seen L36 of payloads/external/edk2/Kconfig
>>>
>>> On Tue, 7 Feb 2023 at 20:30, ritul guru <ritul.bits@gmail.com> wrote:
>>>
>>>>
>>>>
>>>> Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
>>>> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
>>>> Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
>>>> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
>>>> ProtectUefiImageCommon - 0x51A3E1C0
>>>> - 0x0000000051DD1000 - 0x0000000000008000
>>>> SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
>>>> (0x0000000000004008)
>>>> SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
>>>> (0x0000000000020008)
>>>> SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
>>>> (0x0000000000004008)
>>>> PROGRESS CODE: V03040002 I0
>>>>
>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>
>>>> *ASSERT [PcRtc]
>>>> /home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
>>>> getting above assert after changed to FD_BASE to below value,
>>>> This error is coming while booting to coreboot with edk2 payload:
>>>>
>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>> DEFINE FD_BASE = 0x02182000
>>>>
>>>> need to change FD_BASE, as it was going outside Available memory.
>>>> any hint would be appreciated.
>>>>
>>>>
>>>>
>>>>
>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>
>>>>
>>>> On Tue, Feb 7, 2023 at 10:09 PM ritul guru <ritul.bits@gmail.com>
>>>> wrote:
>>>>
>>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>>> DEFINE FD_BASE = 0x00800000
>>>>>
>>>>> Is the above address correct in uefipaylaod?
>>>>> As observing some regions are getting out of limit of FD limit,
>>>>>
>>>>> and when setting DEFINE FD_BASE = 0x02200000, then seeing assert
>>>>> in
>>>>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>
>>>>>
>>>>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com>
>>>>> wrote:
>>>>>
>>>>>> Hi,
>>>>>> I am building edk2 payload and getting below warning for
>>>>>> PcdRtcIndexRegister,
>>>>>> and if try to boot to then observing that there is assert at:
>>>>>>
>>>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>>>
>>>>>> DXE_ASSERT!:
>>>>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>>>>> (141): !EFI_ERROR (Status)
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> build time warning:
>>>>>> Active Platform =
>>>>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>>>>> .build: : warning: The PCD was not specified by any INF module in the
>>>>>> platform for the given architecture.
>>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>>> Arch: ['IA32']
>>>>>> build: : warning: The PCD was not specified by any INF module in the
>>>>>> platform for the given architecture.
>>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>>> Arch: ['IA32']
>>>>>> . done!
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>>
>>>>>
>>>>
>>>>
[-- Attachment #2: Type: text/html, Size: 12239 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-07 22:10 ` Sean Rhodes
@ 2023-02-08 3:13 ` ritul guru
2023-02-09 5:20 ` ritul guru
0 siblings, 1 reply; 14+ messages in thread
From: ritul guru @ 2023-02-08 3:13 UTC (permalink / raw)
To: Sean Rhodes; +Cc: devel
[-- Attachment #1: Type: text/plain, Size: 6241 bytes --]
Any idea why the below error comes?
Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
ProtectUefiImageCommon - 0x51A3E1C0
- 0x0000000051DD1000 - 0x0000000000008000
SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
(0x0000000000004008)
SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
(0x0000000000020008)
SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
(0x0000000000004008)
PROGRESS CODE: V03040002 I0
ASSERT_EFI_ERROR (Status = Device Error)
*ASSERT [PcRtc]
/home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
*anything to do with warning:*
build time warning:
Active Platform =
/home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
.build: : warning: The PCD was not specified by any INF module in the
platform for the given architecture.
PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
Platform: [UefiPayloadPkg.dsc]
Arch: ['IA32']
build: : warning: The PCD was not specified by any INF module in the
platform for the given architecture.
PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
Platform: [UefiPayloadPkg.dsc]
Arch: ['IA32']
. done!
*Thanks & RegardsRitul Guru+91-9916513186*
On Wed, Feb 8, 2023 at 3:40 AM Sean Rhodes <sean@starlabs.systems> wrote:
> L36 is help text that says what you are trying to do, wont work
>
> On Tue, 7 Feb 2023 at 20:51, ritul guru <ritul.bits@gmail.com> wrote:
>
>> fatal: repository 'payloads/external/edk2/workspace/tianocore' does not
>> exist
>> make[1]: *** [Makefile:123:
>> /home/amd/src/phx2/coreboot_phx2/coreboot/payloads/external/edk2/workspace/edk2]
>> Error 128
>> make: *** [payloads/external/Makefile.inc:158: build/UEFIPAYLOAD.fd]
>> Error 2
>>
>>
>>
>>
>>
>> *Thanks & RegardsRitul Guru+91-9916513186*
>>
>>
>> On Wed, Feb 8, 2023 at 2:19 AM ritul guru <ritul.bits@gmail.com> wrote:
>>
>>> I do not get debug logs from edk2 payload even though debug payload is
>>> selected in menuconfig of coreboot.
>>> and also updated FD_BASE, if not then getting GCD assert while adding
>>> regions in phit table.
>>>
>>> below path should be give at L36 for custom edk2 repo?
>>> payloads/external/edk2/workspace/tianocore/
>>>
>>>
>>>
>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>
>>>
>>> On Wed, Feb 8, 2023 at 2:06 AM Sean Rhodes <sean@starlabs.systems>
>>> wrote:
>>>
>>>> Why the edk2 changes? Just to fix this issue?
>>>>
>>>> Have you seen L36 of payloads/external/edk2/Kconfig
>>>>
>>>> On Tue, 7 Feb 2023 at 20:30, ritul guru <ritul.bits@gmail.com> wrote:
>>>>
>>>>>
>>>>>
>>>>> Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
>>>>> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
>>>>> Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
>>>>> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
>>>>> ProtectUefiImageCommon - 0x51A3E1C0
>>>>> - 0x0000000051DD1000 - 0x0000000000008000
>>>>> SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
>>>>> (0x0000000000004008)
>>>>> SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
>>>>> (0x0000000000020008)
>>>>> SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
>>>>> (0x0000000000004008)
>>>>> PROGRESS CODE: V03040002 I0
>>>>>
>>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>>
>>>>> *ASSERT [PcRtc]
>>>>> /home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
>>>>> getting above assert after changed to FD_BASE to below value,
>>>>> This error is coming while booting to coreboot with edk2 payload:
>>>>>
>>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>>> DEFINE FD_BASE = 0x02182000
>>>>>
>>>>> need to change FD_BASE, as it was going outside Available memory.
>>>>> any hint would be appreciated.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>
>>>>>
>>>>> On Tue, Feb 7, 2023 at 10:09 PM ritul guru <ritul.bits@gmail.com>
>>>>> wrote:
>>>>>
>>>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>>>> DEFINE FD_BASE = 0x00800000
>>>>>>
>>>>>> Is the above address correct in uefipaylaod?
>>>>>> As observing some regions are getting out of limit of FD limit,
>>>>>>
>>>>>> and when setting DEFINE FD_BASE = 0x02200000, then seeing
>>>>>> assert in
>>>>>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>>
>>>>>>
>>>>>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>> Hi,
>>>>>>> I am building edk2 payload and getting below warning for
>>>>>>> PcdRtcIndexRegister,
>>>>>>> and if try to boot to then observing that there is assert at:
>>>>>>>
>>>>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>>>>
>>>>>>> DXE_ASSERT!:
>>>>>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>>>>>> (141): !EFI_ERROR (Status)
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> build time warning:
>>>>>>> Active Platform =
>>>>>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>>>>>> .build: : warning: The PCD was not specified by any INF module in
>>>>>>> the platform for the given architecture.
>>>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>>>> Arch: ['IA32']
>>>>>>> build: : warning: The PCD was not specified by any INF module in the
>>>>>>> platform for the given architecture.
>>>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>>>> Arch: ['IA32']
>>>>>>> . done!
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>>>
>>>>>>
>>>>>
>>>>>
[-- Attachment #2: Type: text/html, Size: 15659 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] regarding uefipayload build warning for pcd
2023-02-08 3:13 ` ritul guru
@ 2023-02-09 5:20 ` ritul guru
0 siblings, 0 replies; 14+ messages in thread
From: ritul guru @ 2023-02-09 5:20 UTC (permalink / raw)
To: Sean Rhodes; +Cc: devel
[-- Attachment #1: Type: text/plain, Size: 7510 bytes --]
Any idea, what is the cause of below error?
any workaround can be tried for this?
Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
ProtectUefiImageCommon - 0x51A3E1C0
- 0x0000000051DD1000 - 0x0000000000008000
SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
(0x0000000000004008)
SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
(0x0000000000020008)
SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
(0x0000000000004008)
PROGRESS CODE: V03040002 I0
ASSERT_EFI_ERROR (Status = Device Error)
*ASSERT [PcRtc]
/home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
*Thanks & RegardsRitul Guru+91-9916513186*
On Wed, Feb 8, 2023 at 8:43 AM ritul guru <ritul.bits@gmail.com> wrote:
> Any idea why the below error comes?
>
> Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 51A3E1C0
> Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 51A3ED98
> ProtectUefiImageCommon - 0x51A3E1C0
> - 0x0000000051DD1000 - 0x0000000000008000
> SetUefiImageMemoryAttributes - 0x0000000051DD1000 - 0x0000000000001000
> (0x0000000000004008)
> SetUefiImageMemoryAttributes - 0x0000000051DD2000 - 0x0000000000006000
> (0x0000000000020008)
> SetUefiImageMemoryAttributes - 0x0000000051DD8000 - 0x0000000000001000
> (0x0000000000004008)
> PROGRESS CODE: V03040002 I0
>
> ASSERT_EFI_ERROR (Status = Device Error)
> *ASSERT [PcRtc]
> /home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
>
>
> *anything to do with warning:*
>
> build time warning:
> Active Platform =
> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
> .build: : warning: The PCD was not specified by any INF module in the
> platform for the given architecture.
> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
> Platform: [UefiPayloadPkg.dsc]
> Arch: ['IA32']
> build: : warning: The PCD was not specified by any INF module in the
> platform for the given architecture.
> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
> Platform: [UefiPayloadPkg.dsc]
> Arch: ['IA32']
> . done!
>
>
>
>
>
> *Thanks & RegardsRitul Guru+91-9916513186*
>
>
> On Wed, Feb 8, 2023 at 3:40 AM Sean Rhodes <sean@starlabs.systems> wrote:
>
>> L36 is help text that says what you are trying to do, wont work
>>
>> On Tue, 7 Feb 2023 at 20:51, ritul guru <ritul.bits@gmail.com> wrote:
>>
>>> fatal: repository 'payloads/external/edk2/workspace/tianocore' does not
>>> exist
>>> make[1]: *** [Makefile:123:
>>> /home/amd/src/phx2/coreboot_phx2/coreboot/payloads/external/edk2/workspace/edk2]
>>> Error 128
>>> make: *** [payloads/external/Makefile.inc:158: build/UEFIPAYLOAD.fd]
>>> Error 2
>>>
>>>
>>>
>>>
>>>
>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>
>>>
>>> On Wed, Feb 8, 2023 at 2:19 AM ritul guru <ritul.bits@gmail.com> wrote:
>>>
>>>> I do not get debug logs from edk2 payload even though debug payload is
>>>> selected in menuconfig of coreboot.
>>>> and also updated FD_BASE, if not then getting GCD assert while adding
>>>> regions in phit table.
>>>>
>>>> below path should be give at L36 for custom edk2 repo?
>>>> payloads/external/edk2/workspace/tianocore/
>>>>
>>>>
>>>>
>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>
>>>>
>>>> On Wed, Feb 8, 2023 at 2:06 AM Sean Rhodes <sean@starlabs.systems>
>>>> wrote:
>>>>
>>>>> Why the edk2 changes? Just to fix this issue?
>>>>>
>>>>> Have you seen L36 of payloads/external/edk2/Kconfig
>>>>>
>>>>> On Tue, 7 Feb 2023 at 20:30, ritul guru <ritul.bits@gmail.com> wrote:
>>>>>
>>>>>>
>>>>>>
>>>>>> Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1
>>>>>> InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B
>>>>>> 51A3E1C0
>>>>>> Loading driver at 0x00051DD1000 EntryPoint=0x00051DD5670 PcRtc.efi
>>>>>> InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF
>>>>>> 51A3ED98
>>>>>> ProtectUefiImageCommon - 0x51A3E1C0
>>>>>> - 0x0000000051DD1000 - 0x0000000000008000
>>>>>> SetUefiImageMemoryAttributes - 0x0000000051DD1000 -
>>>>>> 0x0000000000001000 (0x0000000000004008)
>>>>>> SetUefiImageMemoryAttributes - 0x0000000051DD2000 -
>>>>>> 0x0000000000006000 (0x0000000000020008)
>>>>>> SetUefiImageMemoryAttributes - 0x0000000051DD8000 -
>>>>>> 0x0000000000001000 (0x0000000000004008)
>>>>>> PROGRESS CODE: V03040002 I0
>>>>>>
>>>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>>>
>>>>>> *ASSERT [PcRtc]
>>>>>> /home//src/p/coreboot/payloads/external/edk2/workspace/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c(1)*
>>>>>> getting above assert after changed to FD_BASE to below value,
>>>>>> This error is coming while booting to coreboot with edk2 payload:
>>>>>>
>>>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>>>> DEFINE FD_BASE = 0x02182000
>>>>>>
>>>>>> need to change FD_BASE, as it was going outside Available memory.
>>>>>> any hint would be appreciated.
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>>
>>>>>>
>>>>>> On Tue, Feb 7, 2023 at 10:09 PM ritul guru <ritul.bits@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>> UefiPayloadPkg/UefiPayloadPkg.fdf
>>>>>>> DEFINE FD_BASE = 0x00800000
>>>>>>>
>>>>>>> Is the above address correct in uefipaylaod?
>>>>>>> As observing some regions are getting out of limit of FD limit,
>>>>>>>
>>>>>>> and when setting DEFINE FD_BASE = 0x02200000, then seeing
>>>>>>> assert in
>>>>>>> [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister].
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>>>
>>>>>>>
>>>>>>> On Tue, Feb 7, 2023 at 8:29 PM ritul guru <ritul.bits@gmail.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> Hi,
>>>>>>>> I am building edk2 payload and getting below warning for
>>>>>>>> PcdRtcIndexRegister,
>>>>>>>> and if try to boot to then observing that there is assert at:
>>>>>>>>
>>>>>>>> ASSERT_EFI_ERROR (Status = Device Error)
>>>>>>>>
>>>>>>>> DXE_ASSERT!:
>>>>>>>> /home/amd/src///coreboot/payloads/external/tianocore/tianocore/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
>>>>>>>> (141): !EFI_ERROR (Status)
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> build time warning:
>>>>>>>> Active Platform =
>>>>>>>> /home//src///coreboot/payloads/external/edk2/workspace/tianocore/UefiPayloadPkg/UefiPayloadPkg.dsc
>>>>>>>> .build: : warning: The PCD was not specified by any INF module in
>>>>>>>> the platform for the given architecture.
>>>>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister]
>>>>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>>>>> Arch: ['IA32']
>>>>>>>> build: : warning: The PCD was not specified by any INF module in
>>>>>>>> the platform for the given architecture.
>>>>>>>> PCD: [gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister]
>>>>>>>> Platform: [UefiPayloadPkg.dsc]
>>>>>>>> Arch: ['IA32']
>>>>>>>> . done!
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> *Thanks & RegardsRitul Guru+91-9916513186*
>>>>>>>>
>>>>>>>
>>>>>>
>>>>>>
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-02-09 5:20 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-02-07 14:59 regarding uefipayload build warning for pcd ritul guru
2023-02-07 16:39 ` ritul guru
2023-02-07 18:27 ` ritul guru
2023-02-07 20:35 ` [edk2-devel] " Sean Rhodes
2023-02-07 20:49 ` ritul guru
2023-02-07 20:51 ` ritul guru
2023-02-07 22:10 ` Sean Rhodes
2023-02-08 3:13 ` ritul guru
2023-02-09 5:20 ` ritul guru
2023-02-07 18:30 ` Sean Rhodes
2023-02-07 19:01 ` ritul guru
2023-02-07 19:02 ` ritul guru
2023-02-07 19:53 ` Sean Rhodes
2023-02-07 20:25 ` ritul guru
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