From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt0-x22b.google.com (mail-qt0-x22b.google.com [IPv6:2607:f8b0:400d:c0d::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D4BCD21CAD9A0 for ; Sun, 2 Jul 2017 19:27:49 -0700 (PDT) Received: by mail-qt0-x22b.google.com with SMTP id 32so133627177qtv.1 for ; Sun, 02 Jul 2017 19:29:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=zuCkWPg3+VDZb/qHVLsePoyRSLBMkU5mnqMI6CJ9ln4=; b=K2AlvgzJ6neVxv07X0LlvwFhkq/O/qnVCbg8LIrd9LwRrJMieoiz9IIkNqO0PLHklD OBgXwhyUq969pnq5N+Q5QQgEVKfSoYzgJEmlEhfjPQgoG8QVZZZDzeC2+SyuWox89PHV M78/k3tl/oaJnT7X5tU6OmhzrXCRZ4wSztD8c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=zuCkWPg3+VDZb/qHVLsePoyRSLBMkU5mnqMI6CJ9ln4=; b=nGy+GcMTx9DUKrP3B+45gJN59Db7RHbrVHGLBLkqCAPBBxGd9GwhRFR7TJUW2hBxcH aw0j+HxfAcAN1nZ3hNFU1aRB7g1KCk8Ob4HtT+0n0r0Yd8C9FUSrXAgeHoa+4aTTxbZZ 0FsNxeS1i7JVHptNjxW5LXwGRK37PlNSYURDy2drDj9EeFRIWDnSldvFmcNhMqCTrzrk TUnEMug9enj4EIlz6c6CbOlpaWj9ezLrDGaVP5PMjekz9pvL1B6n+ITFTAVn2UukaZ+T KCHQ+tdNGJ0Q9EAY6KUFdaowGPdmtoGfVJCccv29lncR22aPmJHslEI0uppo8kPWPfvs JbkQ== X-Gm-Message-State: AKS2vOzT2RNe9vzdMa2yMEaAXlgxeHm2S3c3IRGspqRFGr9pgF57x11n f85Ut79s87+bZHhp0W8RwygR5g518iDX X-Received: by 10.200.53.243 with SMTP id l48mr41741199qtb.7.1499048965459; Sun, 02 Jul 2017 19:29:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.55.110.66 with HTTP; Sun, 2 Jul 2017 19:29:25 -0700 (PDT) In-Reply-To: <4A89E2EF3DFEDB4C8BFDE51014F606A14D750466@shsmsx102.ccr.corp.intel.com> References: <4A89E2EF3DFEDB4C8BFDE51014F606A14D750466@shsmsx102.ccr.corp.intel.com> From: Jun Nie Date: Mon, 3 Jul 2017 10:29:25 +0800 Message-ID: To: "Gao, Liming" Cc: Leif Lindholm , Ard Biesheuvel , "edk2-devel@lists.01.org" , "linaro-uefi@lists.linaro.org" , "Alexei.Fedorov@arm.com" , "evan.lloyd@arm.com" Subject: Re: How to add support to different reg offset definition to share the same driver code? X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 03 Jul 2017 02:27:50 -0000 Content-Type: text/plain; charset="UTF-8" 2017-06-30 21:29 GMT+08:00 Gao, Liming : > Jun: > You can add C MACRO in [BuildOptions] of Platform.dsc, then use DSC flag to control it. > > For example: Platform.dsc > [Defines] > DEFINE ZX_PL011_FLAG = FALSE > > [BuildOptions] > !if $(ZX_PL011_FLAG) == TRUE > *_*_*_CC_FLAGS = -D ZX_PL011_FLAG > !endif > > Thanks > Liming Thanks for your demo code. It help a lot to a new comer. Jun >> -----Original Message----- >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jun Nie >> Sent: Friday, June 30, 2017 11:35 AM >> To: Leif Lindholm ; Ard Biesheuvel ; edk2-devel@lists.01.org; >> linaro-uefi@lists.linaro.org; Alexei.Fedorov@arm.com; evan.lloyd@arm.com >> Subject: [edk2] How to add support to different reg offset definition to share the same driver code? >> >> Hi, >> >> I am trying to add support to different reg offset and bit offset in >> PL011 UART. It seems impossible to add macro in platform.dsc to enable >> undef/redef in the header file with "#ifdef ZX_PL011_FLAG". Is there >> any proper way to control the reg/bit offset definition? Or we have to >> adopt the Linux driver method with a structure to hold different >> offset value and wrap register access function as below? If so, >> another Pcd is needed to specify the offset structure index for the >> platforms. >> >> >> static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { >> [REG_DR] = UART01x_DR, >> [REG_ST_DMAWM] = ST_UART011_DMAWM, >> [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, >> ... >> } >> >> static unsigned int pl011_read(const struct uart_amba_port *uap, >> unsigned int reg) >> { >> void __iomem *addr = uap->port.membase + uap->reg_offset[reg]; >> >> return (uap->port.iotype == UPIO_MEM32) ? >> readl_relaxed(addr) : readw_relaxed(addr); >> } >> >> Jun >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel