From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt0-x231.google.com (mail-qt0-x231.google.com [IPv6:2607:f8b0:400d:c0d::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D3C521B02B97 for ; Thu, 29 Jun 2017 20:33:54 -0700 (PDT) Received: by mail-qt0-x231.google.com with SMTP id i2so89786513qta.3 for ; Thu, 29 Jun 2017 20:35:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:from:date:message-id:subject:to; bh=n6C3tXTgfZSUgf5nu5oEjTfqanIxwOaObUBuQHPujro=; b=WPz2pAccUs6CRmAWel3jEXb1fi7PFgw/9NsvazooCzz7iqvN/L/eIGkCN2AilkwTPS Gshzbd9ZaiuEYKl76m0v07FASbzbCUJaYDoiIJsnjVOUTSpTu3ZUeuiNZAIL5Tykf7Q1 3k3Zgib78diYh1Q5U3QdP9CAhtYJ/X/T1eV8Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=n6C3tXTgfZSUgf5nu5oEjTfqanIxwOaObUBuQHPujro=; b=MXlAApW6IurGuIpfFrQ3qCZ9p16VZ4Uz9zTzl49vmRHhO5OL1ob5LF4C463OTkdyro HxIe+/IFzGVubi9b7f5L48CBTlOrxGAPfnSPjXcGeklpSw/AvY0ESZSrblZWP4HrZMmQ PwwafQrd2EBQO9fP9W6UMWrG8oJq6KS0RatvxVrlWrVqRq8BZxB66eN8Y8bxBtw4dU6T KRHL1KUCL6HcbjcKZoi1O4TM9LJfRC1Dz8a7IPbwUwrhaSJKDTHLKRD8hMrLCR24p306 j5c5gibCmf9z2sijWmkijzoc7bun32RDsERTUtogzJVP132rdgoe0jMdm1XbPFeNdOv1 MNwA== X-Gm-Message-State: AKS2vOyISE8S6v/lh5HiwV4Cb9ZeTAS2gCU4p3CUY1hnn9jf6u8BSIL5 zACOsNvB76oyFTvLC1sl7oaz9clhTnvr X-Received: by 10.200.54.38 with SMTP id m35mr24639237qtb.220.1498793727029; Thu, 29 Jun 2017 20:35:27 -0700 (PDT) MIME-Version: 1.0 Received: by 10.55.110.66 with HTTP; Thu, 29 Jun 2017 20:35:26 -0700 (PDT) From: Jun Nie Date: Fri, 30 Jun 2017 11:35:26 +0800 Message-ID: To: Leif Lindholm , Ard Biesheuvel , edk2-devel@lists.01.org, linaro-uefi@lists.linaro.org, Alexei.Fedorov@arm.com, evan.lloyd@arm.com Subject: How to add support to different reg offset definition to share the same driver code? X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Jun 2017 03:33:54 -0000 Content-Type: text/plain; charset="UTF-8" Hi, I am trying to add support to different reg offset and bit offset in PL011 UART. It seems impossible to add macro in platform.dsc to enable undef/redef in the header file with "#ifdef ZX_PL011_FLAG". Is there any proper way to control the reg/bit offset definition? Or we have to adopt the Linux driver method with a structure to hold different offset value and wrap register access function as below? If so, another Pcd is needed to specify the offset structure index for the platforms. static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { [REG_DR] = UART01x_DR, [REG_ST_DMAWM] = ST_UART011_DMAWM, [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, ... } static unsigned int pl011_read(const struct uart_amba_port *uap, unsigned int reg) { void __iomem *addr = uap->port.membase + uap->reg_offset[reg]; return (uap->port.iotype == UPIO_MEM32) ? readl_relaxed(addr) : readw_relaxed(addr); } Jun