* [edk2-platforms] [PATCH v1 1/3] Platform/ARM/SgiPkg: Add helper macros for HMAT table
2021-01-28 13:42 [edk2-platforms] [PATCH v1 0/3] Add HMAT tables for RD multi-chip platforms Vijayenthiran Subramaniam
@ 2021-01-28 13:42 ` Vijayenthiran Subramaniam
2021-01-28 13:42 ` [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2 Vijayenthiran Subramaniam
2021-01-28 13:42 ` [edk2-platforms] [PATCH v1 3/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RD-V1-MC Vijayenthiran Subramaniam
2 siblings, 0 replies; 10+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-01-28 13:42 UTC (permalink / raw)
To: devel, leif, ardb+tianocore, sami.mujawar; +Cc: thomas.abraham
Add helper macros to create Memory Proximity Domain, System Locality
Latency and Bandwidth Information, Memory Side Cache Information
structures in the HMAT table.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
---
| 110 ++++++++++++++++++++
1 file changed, 110 insertions(+)
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index 8d715de173c9..181d9d771d1e 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -119,4 +119,114 @@
ACPIProcessorUID, Flags, ClockDomain \
}
+//
+// HMAT related structures
+//
+// Memory Proximity Domain Attributes Structure
+// Refer Section 5.2.27.3 in ACPI Specification, Version 6.3
+#define EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT( \
+ Flags, ProximityDomainForAttachedIntiator, ProximityDomainForMemory) \
+ { \
+ 0, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES), \
+ { \
+ Flags, \
+ 0 \
+ }, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ ProximityDomainForAttachedIntiator, \
+ ProximityDomainForMemory, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ } \
+ }
+
+// System Locality Latency and Bandwidth Information Structure
+// Refer Section 5.2.27.4 in ACPI Specification, Version 6.3
+#define EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT( \
+ Flags, DataType, NumInitiatorProximityDomains, \
+ NumTargetProximityDomains, EntryBaseUnit) \
+ { \
+ 1, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO) + \
+ (4 * NumInitiatorProximityDomains) + (4 * NumTargetProximityDomains) + \
+ (2 * NumInitiatorProximityDomains * NumTargetProximityDomains), \
+ { \
+ Flags, 0 \
+ }, \
+ DataType, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ NumInitiatorProximityDomains, \
+ NumTargetProximityDomains, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ EntryBaseUnit \
+ }
+
+// Memory Side Cache Information Structure
+// Refer Section 5.2.27.5 in ACPI Specification, Version 6.3
+#define EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT( \
+ MemoryProximityDomain, MemorySideCacheSize, CacheAttributes, \
+ NumberOfSmbiosHandles) \
+ { \
+ 2, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ sizeof (EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO) + \
+ (NumberOfSmbiosHandles * 2), \
+ MemoryProximityDomain, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ MemorySideCacheSize, \
+ CacheAttributes, \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE \
+ }, \
+ NumberOfSmbiosHandles \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-01-28 13:42 [edk2-platforms] [PATCH v1 0/3] Add HMAT tables for RD multi-chip platforms Vijayenthiran Subramaniam
2021-01-28 13:42 ` [edk2-platforms] [PATCH v1 1/3] Platform/ARM/SgiPkg: Add helper macros for HMAT table Vijayenthiran Subramaniam
@ 2021-01-28 13:42 ` Vijayenthiran Subramaniam
2021-01-28 15:58 ` [edk2-devel] " Jonathan Cameron
` (2 more replies)
2021-01-28 13:42 ` [edk2-platforms] [PATCH v1 3/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RD-V1-MC Vijayenthiran Subramaniam
2 siblings, 3 replies; 10+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-01-28 13:42 UTC (permalink / raw)
To: devel, leif, ardb+tianocore, sami.mujawar; +Cc: thomas.abraham
Add HMAT table support for RD-N1-Edge Dual-chip platform.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 108 ++++++++++++++++++++
2 files changed, 109 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index d44f02ab0c16..36d41281439d 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -22,6 +22,7 @@ [Sources]
Iort.aslc
Mcfg.aslc
RdN1Edge/Dsdt.asl
+ RdN1EdgeX2/Hmat.aslc
RdN1EdgeX2/Madt.aslc
RdN1EdgeX2/Srat.aslc
Spcr.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
new file mode 100644
index 000000000000..29d089aed053
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -0,0 +1,108 @@
+/** @file
+* Heterogeneous Memory Attribute Table (HMAT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+
+#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
+#define INITATOR_PROXIMITY_DOMAIN_CNT 2
+#define TARGET_PROXIMITY_DOMIAIN_CNT 2
+
+//
+// HMAT Table
+//
+#pragma pack (1)
+
+typedef struct {
+ UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
+ UINT32 TargetProximityDomiain[TARGET_PROXIMITY_DOMIAIN_CNT];
+ UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOMIAIN_CNT];
+} InitiatorTargetProximityMatrix;
+
+typedef struct {
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
+ InitiatorTargetProximityMatrix Matrix;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
+
+#pragma pack ()
+
+#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+ ) \
+{ \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+}
+
+EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
+ // Header
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ ),
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ },
+
+ // Memory Proximity Domain
+ {
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x0, 0x0),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x1, 0x1),
+ },
+
+ // Latency Info
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+ 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMIAIN_CNT, 100),
+ {
+ {0, 1}, {0, 1},
+ {
+ 10, 20,
+ 20, 10,
+ }
+ },
+
+ // Memory Side Cache
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x0, SIZE_8MB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x1, SIZE_8MB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+};
+
+VOID* CONST ReferenceAcpiTable = &Hmat;
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [edk2-devel] [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-01-28 13:42 ` [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2 Vijayenthiran Subramaniam
@ 2021-01-28 15:58 ` Jonathan Cameron
[not found] ` <165E70A6BEEFF3E5.24597@groups.io>
2021-02-12 17:28 ` Sami Mujawar
2 siblings, 0 replies; 10+ messages in thread
From: Jonathan Cameron @ 2021-01-28 15:58 UTC (permalink / raw)
To: Vijayenthiran Subramaniam
Cc: devel, leif, ardb+tianocore, sami.mujawar, thomas.abraham
On Thu, 28 Jan 2021 19:12:30 +0530
Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> wrote:
> Add HMAT table support for RD-N1-Edge Dual-chip platform.
>
> Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
> ---
> Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
> Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 108 ++++++++++++++++++++
> 2 files changed, 109 insertions(+)
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> index d44f02ab0c16..36d41281439d 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> @@ -22,6 +22,7 @@ [Sources]
> Iort.aslc
> Mcfg.aslc
> RdN1Edge/Dsdt.asl
> + RdN1EdgeX2/Hmat.aslc
> RdN1EdgeX2/Madt.aslc
> RdN1EdgeX2/Srat.aslc
> Spcr.aslc
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
> new file mode 100644
> index 000000000000..29d089aed053
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
> @@ -0,0 +1,108 @@
> +/** @file
> +* Heterogeneous Memory Attribute Table (HMAT)
> +*
> +* Copyright (c) 2020, ARM Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +**/
> +
> +#include "SgiAcpiHeader.h"
> +#include "SgiPlatform.h"
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +
> +#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
> +#define INITATOR_PROXIMITY_DOMAIN_CNT 2
> +#define TARGET_PROXIMITY_DOMIAIN_CNT 2
DOMAIN
> +
> +//
> +// HMAT Table
> +//
> +#pragma pack (1)
> +
> +typedef struct {
> + UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
> + UINT32 TargetProximityDomiain[TARGET_PROXIMITY_DOMIAIN_CNT];
> + UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOMIAIN_CNT];
> +} InitiatorTargetProximityMatrix;
> +
> +typedef struct {
> + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
> + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
> + InitiatorTargetProximityMatrix Matrix;
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
> +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
> +
> +#pragma pack ()
> +
> +#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
> + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
> + ) \
> +{ \
> + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
> +}
> +
> +EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
> + // Header
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
> + EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
> + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
> + ),
> + {
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE,
> + EFI_ACPI_RESERVED_BYTE
> + },
> + },
> +
> + // Memory Proximity Domain
> + {
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> + 1, 0x0, 0x0),
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> + 1, 0x1, 0x1),
> + },
> +
> + // Latency Info
> + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
> + 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMIAIN_CNT, 100),
> + {
> + {0, 1}, {0, 1},
> + {
> + 10, 20,
> + 20, 10,
> + }
> + },
> +
> + // Memory Side Cache
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> + 0x0, SIZE_8MB,
> + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> + 1,
> + 1,
> + 2,
> + 2,
> + 64 // 64 bytes cache line length
> + ),
> + 0),
> +
> + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> + 0x1, SIZE_8MB,
> + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> + 1,
> + 1,
> + 2,
> + 2,
> + 64 // 64 bytes cache line length
> + ),
> + 0),
> +};
> +
> +VOID* CONST ReferenceAcpiTable = &Hmat;
^ permalink raw reply [flat|nested] 10+ messages in thread[parent not found: <165E70A6BEEFF3E5.24597@groups.io>]
* Re: [edk2-devel] [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
[not found] ` <165E70A6BEEFF3E5.24597@groups.io>
@ 2021-01-29 9:49 ` Jonathan Cameron
2021-01-29 17:11 ` Vijayenthiran Subramaniam
0 siblings, 1 reply; 10+ messages in thread
From: Jonathan Cameron @ 2021-01-29 9:49 UTC (permalink / raw)
To: Jonathan Cameron via groups.io
Cc: devel, jonathan.cameron, Vijayenthiran Subramaniam, leif,
ardb+tianocore, sami.mujawar, thomas.abraham
On Thu, 28 Jan 2021 15:58:48 +0000
Jonathan Cameron via groups.io <jonathan.cameron=huawei.com@groups.io> wrote:
> On Thu, 28 Jan 2021 19:12:30 +0530
> Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> wrote:
>
> > Add HMAT table support for RD-N1-Edge Dual-chip platform.
> >
> > Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
> > ---
> > Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
> > Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 108 ++++++++++++++++++++
> > 2 files changed, 109 insertions(+)
> >
> > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> > index d44f02ab0c16..36d41281439d 100644
> > --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> > @@ -22,6 +22,7 @@ [Sources]
> > Iort.aslc
> > Mcfg.aslc
> > RdN1Edge/Dsdt.asl
> > + RdN1EdgeX2/Hmat.aslc
> > RdN1EdgeX2/Madt.aslc
> > RdN1EdgeX2/Srat.aslc
> > Spcr.aslc
> > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
> > new file mode 100644
> > index 000000000000..29d089aed053
> > --- /dev/null
> > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
> > @@ -0,0 +1,108 @@
> > +/** @file
> > +* Heterogeneous Memory Attribute Table (HMAT)
> > +*
> > +* Copyright (c) 2020, ARM Limited. All rights reserved.
> > +*
> > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > +*
> > +**/
> > +
> > +#include "SgiAcpiHeader.h"
> > +#include "SgiPlatform.h"
> > +#include <IndustryStandard/Acpi.h>
> > +#include <Library/AcpiLib.h>
> > +#include <Library/ArmLib.h>
> > +
> > +#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
> > +#define INITATOR_PROXIMITY_DOMAIN_CNT 2
> > +#define TARGET_PROXIMITY_DOMIAIN_CNT 2
>
> DOMAIN
>
> > +
> > +//
> > +// HMAT Table
> > +//
> > +#pragma pack (1)
> > +
> > +typedef struct {
> > + UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
> > + UINT32 TargetProximityDomiain[TARGET_PROXIMITY_DOMIAIN_CNT];
> > + UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOMIAIN_CNT];
> > +} InitiatorTargetProximityMatrix;
> > +
> > +typedef struct {
> > + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
> > + InitiatorTargetProximityMatrix Matrix;
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
> > +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
> > +
> > +#pragma pack ()
> > +
> > +#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
> > + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
> > + ) \
> > +{ \
> > + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
> > +}
> > +
> > +EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
> > + // Header
> > + {
> > + ARM_ACPI_HEADER (
> > + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
> > + EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
> > + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
> > + ),
> > + {
> > + EFI_ACPI_RESERVED_BYTE,
> > + EFI_ACPI_RESERVED_BYTE,
> > + EFI_ACPI_RESERVED_BYTE,
> > + EFI_ACPI_RESERVED_BYTE
> > + },
> > + },
> > +
> > + // Memory Proximity Domain
> > + {
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> > + 1, 0x0, 0x0),
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> > + 1, 0x1, 0x1),
> > + },
> > +
> > + // Latency Info
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
> > + 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMIAIN_CNT, 100),
> > + {
> > + {0, 1}, {0, 1},
> > + {
> > + 10, 20,
> > + 20, 10,
> > + }
> > + },
Hi,
Now either you have a very odd machine in which latencies are round numbers that happen
to look like the values in SLIT or ... ?
HMAT has very carefully defined real world units to overcome the fact that there
was no standard scaling etc for SLIT. It is not a good idea to put tables out
there which don't do this right as someone may copy this for a real system
and we end up with HMAT being roughly as useless for performance prediction as
SLIT is. That is not something I would want to see.
Jonathan
> > +
> > + // Memory Side Cache
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> > + 0x0, SIZE_8MB,
> > + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> > + 1,
> > + 1,
> > + 2,
> > + 2,
> > + 64 // 64 bytes cache line length
> > + ),
> > + 0),
> > +
> > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> > + 0x1, SIZE_8MB,
> > + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> > + 1,
> > + 1,
> > + 2,
> > + 2,
> > + 64 // 64 bytes cache line length
> > + ),
> > + 0),
> > +};
> > +
> > +VOID* CONST ReferenceAcpiTable = &Hmat;
>
>
>
>
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [edk2-devel] [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-01-29 9:49 ` Jonathan Cameron
@ 2021-01-29 17:11 ` Vijayenthiran Subramaniam
2021-02-01 11:16 ` Jonathan Cameron
0 siblings, 1 reply; 10+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-01-29 17:11 UTC (permalink / raw)
To: devel, jonathan.cameron
Cc: Jonathan Cameron via groups.io, Vijayenthiran Subramaniam, leif,
ardb+tianocore, Sami Mujawar, Thomas Abraham
Hi Jonathan,
On Fri, Jan 29, 2021 at 9:50 AM Jonathan Cameron via groups.io
<jonathan.cameron=huawei.com@groups.io> wrote:
>
> On Thu, 28 Jan 2021 15:58:48 +0000
> Jonathan Cameron via groups.io <jonathan.cameron=huawei.com@groups.io> wrote:
>
> > On Thu, 28 Jan 2021 19:12:30 +0530
> > Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> wrote:
> >
> > > Add HMAT table support for RD-N1-Edge Dual-chip platform.
> > >
> > > Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
> > > ---
> > > Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
> > > Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 108 ++++++++++++++++++++
> > > 2 files changed, 109 insertions(+)
> > >
> > > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> > > index d44f02ab0c16..36d41281439d 100644
> > > --- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> > > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
> > > @@ -22,6 +22,7 @@ [Sources]
> > > Iort.aslc
> > > Mcfg.aslc
> > > RdN1Edge/Dsdt.asl
> > > + RdN1EdgeX2/Hmat.aslc
> > > RdN1EdgeX2/Madt.aslc
> > > RdN1EdgeX2/Srat.aslc
> > > Spcr.aslc
> > > diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
> > > new file mode 100644
> > > index 000000000000..29d089aed053
> > > --- /dev/null
> > > +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
> > > @@ -0,0 +1,108 @@
> > > +/** @file
> > > +* Heterogeneous Memory Attribute Table (HMAT)
> > > +*
> > > +* Copyright (c) 2020, ARM Limited. All rights reserved.
> > > +*
> > > +* SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +*
> > > +**/
> > > +
> > > +#include "SgiAcpiHeader.h"
> > > +#include "SgiPlatform.h"
> > > +#include <IndustryStandard/Acpi.h>
> > > +#include <Library/AcpiLib.h>
> > > +#include <Library/ArmLib.h>
> > > +
> > > +#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
> > > +#define INITATOR_PROXIMITY_DOMAIN_CNT 2
> > > +#define TARGET_PROXIMITY_DOMIAIN_CNT 2
> >
> > DOMAIN
Ack, will fix in v2.
> >
> > > +
> > > +//
> > > +// HMAT Table
> > > +//
> > > +#pragma pack (1)
> > > +
> > > +typedef struct {
> > > + UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
> > > + UINT32 TargetProximityDomiain[TARGET_PROXIMITY_DOMIAIN_CNT];
> > > + UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOMIAIN_CNT];
> > > +} InitiatorTargetProximityMatrix;
> > > +
> > > +typedef struct {
> > > + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
> > > + InitiatorTargetProximityMatrix Matrix;
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
> > > +} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
> > > +
> > > +#pragma pack ()
> > > +
> > > +#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
> > > + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
> > > + ) \
> > > +{ \
> > > + TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
> > > +}
> > > +
> > > +EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
> > > + // Header
> > > + {
> > > + ARM_ACPI_HEADER (
> > > + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
> > > + EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
> > > + EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
> > > + ),
> > > + {
> > > + EFI_ACPI_RESERVED_BYTE,
> > > + EFI_ACPI_RESERVED_BYTE,
> > > + EFI_ACPI_RESERVED_BYTE,
> > > + EFI_ACPI_RESERVED_BYTE
> > > + },
> > > + },
> > > +
> > > + // Memory Proximity Domain
> > > + {
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> > > + 1, 0x0, 0x0),
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> > > + 1, 0x1, 0x1),
> > > + },
> > > +
> > > + // Latency Info
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
> > > + 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMIAIN_CNT, 100),
> > > + {
> > > + {0, 1}, {0, 1},
> > > + {
> > > + 10, 20,
> > > + 20, 10,
> > > + }
> > > + },
>
> Hi,
>
> Now either you have a very odd machine in which latencies are round numbers that happen
> to look like the values in SLIT or ... ?
>
> HMAT has very carefully defined real world units to overcome the fact that there
> was no standard scaling etc for SLIT. It is not a good idea to put tables out
> there which don't do this right as someone may copy this for a real system
> and we end up with HMAT being roughly as useless for performance prediction as
> SLIT is. That is not something I would want to see.
>
> Jonathan
This patch is for a platform that is modelled and not for an actual board. So
the latencies are hypothetical but ensure that the typical latency between two
chips is represented. These tables are not expected to be copied for another
platform without understanding what these values mean. Such a copy, without
understanding what is being copied, would be an error in judgement on the part
of the person doing it. The commit message of this patch (in v2) can be updated
to exercise caution on reusing these values.
[1]: https://developer.arm.com/products/system-design/fixed-virtual-platforms
Best Regards,
Vijayenthiran
>
> > > +
> > > + // Memory Side Cache
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> > > + 0x0, SIZE_8MB,
> > > + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> > > + 1,
> > > + 1,
> > > + 2,
> > > + 2,
> > > + 64 // 64 bytes cache line length
> > > + ),
> > > + 0),
> > > +
> > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> > > + 0x1, SIZE_8MB,
> > > + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> > > + 1,
> > > + 1,
> > > + 2,
> > > + 2,
> > > + 64 // 64 bytes cache line length
> > > + ),
> > > + 0),
> > > +};
> > > +
> > > +VOID* CONST ReferenceAcpiTable = &Hmat;
> >
> >
> >
> >
> >
> >
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [edk2-devel] [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-01-29 17:11 ` Vijayenthiran Subramaniam
@ 2021-02-01 11:16 ` Jonathan Cameron
2021-02-01 12:53 ` Vijayenthiran Subramaniam
0 siblings, 1 reply; 10+ messages in thread
From: Jonathan Cameron @ 2021-02-01 11:16 UTC (permalink / raw)
To: Vijayenthiran Subramanian
Cc: devel, Jonathan Cameron via groups.io, leif, ardb+tianocore,
Sami Mujawar, Thomas Abraham
On Fri, 29 Jan 2021 17:11:03 +0000
Vijayenthiran Subramanian <vijayenthiran.subramaniam@arm.com> wrote:
Hi Vijayenthiran,
....
> > > > + // Memory Proximity Domain
> > > > + {
> > > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> > > > + 1, 0x0, 0x0),
> > > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> > > > + 1, 0x1, 0x1),
> > > > + },
> > > > +
> > > > + // Latency Info
> > > > + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
> > > > + 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMIAIN_CNT, 100),
> > > > + {
> > > > + {0, 1}, {0, 1},
> > > > + {
> > > > + 10, 20,
> > > > + 20, 10,
> > > > + }
> > > > + },
> >
> > Hi,
> >
> > Now either you have a very odd machine in which latencies are round numbers that happen
> > to look like the values in SLIT or ... ?
> >
> > HMAT has very carefully defined real world units to overcome the fact that there
> > was no standard scaling etc for SLIT. It is not a good idea to put tables out
> > there which don't do this right as someone may copy this for a real system
> > and we end up with HMAT being roughly as useless for performance prediction as
> > SLIT is. That is not something I would want to see.
> >
> > Jonathan
>
> This patch is for a platform that is modelled and not for an actual board. So
> the latencies are hypothetical but ensure that the typical latency between two
> chips is represented. These tables are not expected to be copied for another
> platform without understanding what these values mean. Such a copy, without
> understanding what is being copied, would be an error in judgement on the part
> of the person doing it. The commit message of this patch (in v2) can be updated
> to exercise caution on reusing these values.
>
> [1]: https://developer.arm.com/products/system-design/fixed-virtual-platforms
No one reads commit messages. So if you want to avoid people copying them put a
comment in the actual file. Or just make up some more plausible numbers :)
All we really need here is to avoid giving the impression that copying numbers from
SLIT is valid.
Jonathan
>
> Best Regards,
> Vijayenthiran
>
> >
> > > > +
> > > > + // Memory Side Cache
> > > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> > > > + 0x0, SIZE_8MB,
> > > > + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> > > > + 1,
> > > > + 1,
> > > > + 2,
> > > > + 2,
> > > > + 64 // 64 bytes cache line length
> > > > + ),
> > > > + 0),
> > > > +
> > > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
> > > > + 0x1, SIZE_8MB,
> > > > + HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
> > > > + 1,
> > > > + 1,
> > > > + 2,
> > > > + 2,
> > > > + 64 // 64 bytes cache line length
> > > > + ),
> > > > + 0),
> > > > +};
> > > > +
> > > > +VOID* CONST ReferenceAcpiTable = &Hmat;
> > >
> > >
> > >
> > >
> > >
> > >
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [edk2-devel] [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-02-01 11:16 ` Jonathan Cameron
@ 2021-02-01 12:53 ` Vijayenthiran Subramaniam
0 siblings, 0 replies; 10+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-02-01 12:53 UTC (permalink / raw)
To: devel, jonathan.cameron
Cc: Vijayenthiran Subramanian, leif, ardb+tianocore, Sami Mujawar,
Thomas Abraham
Hi Jonathan,
On Mon, Feb 1, 2021 at 11:16 AM Jonathan Cameron via groups.io
<jonathan.cameron=huawei.com@groups.io> wrote:
>
> On Fri, 29 Jan 2021 17:11:03 +0000
> Vijayenthiran Subramanian <vijayenthiran.subramaniam@arm.com> wrote:
>
> Hi Vijayenthiran,
>
> ....
>
> > > > > + // Memory Proximity Domain
> > > > > + {
> > > > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> > > > > + 1, 0x0, 0x0),
> > > > > + EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
> > > > > + 1, 0x1, 0x1),
> > > > > + },
> > > > > +
> > > > > + // Latency Info
> > > > > + EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
> > > > > + 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMIAIN_CNT, 100),
> > > > > + {
> > > > > + {0, 1}, {0, 1},
> > > > > + {
> > > > > + 10, 20,
> > > > > + 20, 10,
> > > > > + }
> > > > > + },
> > >
> > > Hi,
> > >
> > > Now either you have a very odd machine in which latencies are round numbers that happen
> > > to look like the values in SLIT or ... ?
> > >
> > > HMAT has very carefully defined real world units to overcome the fact that there
> > > was no standard scaling etc for SLIT. It is not a good idea to put tables out
> > > there which don't do this right as someone may copy this for a real system
> > > and we end up with HMAT being roughly as useless for performance prediction as
> > > SLIT is. That is not something I would want to see.
> > >
> > > Jonathan
> >
> > This patch is for a platform that is modelled and not for an actual board. So
> > the latencies are hypothetical but ensure that the typical latency between two
> > chips is represented. These tables are not expected to be copied for another
> > platform without understanding what these values mean. Such a copy, without
> > understanding what is being copied, would be an error in judgement on the part
> > of the person doing it. The commit message of this patch (in v2) can be updated
> > to exercise caution on reusing these values.
> >
> > [1]: https://developer.arm.com/products/system-design/fixed-virtual-platforms
>
> No one reads commit messages. So if you want to avoid people copying them put a
> comment in the actual file. Or just make up some more plausible numbers :)
> All we really need here is to avoid giving the impression that copying numbers from
> SLIT is valid.
>
> Jonathan
>
Sure, I will add a comment in the file as well.
Regards,
Vijayenthiran
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
2021-01-28 13:42 ` [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2 Vijayenthiran Subramaniam
2021-01-28 15:58 ` [edk2-devel] " Jonathan Cameron
[not found] ` <165E70A6BEEFF3E5.24597@groups.io>
@ 2021-02-12 17:28 ` Sami Mujawar
2 siblings, 0 replies; 10+ messages in thread
From: Sami Mujawar @ 2021-02-12 17:28 UTC (permalink / raw)
To: Vijayenthiran Subramaniam, devel@edk2.groups.io,
leif@nuviainc.com, ardb+tianocore@kernel.org
Cc: Thomas Abraham, nd
Hi Vijay,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
-----Original Message-----
From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Sent: 28 January 2021 01:43 PM
To: devel@edk2.groups.io; leif@nuviainc.com; ardb+tianocore@kernel.org; Sami Mujawar <Sami.Mujawar@arm.com>
Cc: Thomas Abraham <thomas.abraham@arm.com>
Subject: [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2
Add HMAT table support for RD-N1-Edge Dual-chip platform.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc | 108 ++++++++++++++++++++
2 files changed, 109 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index d44f02ab0c16..36d41281439d 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -22,6 +22,7 @@ [Sources]
Iort.aslc
Mcfg.aslc
RdN1Edge/Dsdt.asl
+ RdN1EdgeX2/Hmat.aslc
RdN1EdgeX2/Madt.aslc
RdN1EdgeX2/Srat.aslc
Spcr.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
new file mode 100644
index 000000000000..29d089aed053
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Hmat.aslc
@@ -0,0 +1,108 @@
+/** @file
+* Heterogeneous Memory Attribute Table (HMAT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
[SAMI] Use <Sgixx.h> for Sgi headers. See https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/55_preprocessor_directives#5-5-1-1-use-the-proper-file-delimiters-when-including-files
Also, it should be possible to move the Sgi headers here.
[/SAMI]
+
+#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
+#define INITATOR_PROXIMITY_DOMAIN_CNT 2
+#define TARGET_PROXIMITY_DOMIAIN_CNT 2
+
+//
+// HMAT Table
+//
+#pragma pack (1)
+
+typedef struct {
+ UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
+ UINT32 TargetProximityDomiain[TARGET_PROXIMITY_DOMIAIN_CNT];
+ UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOMIAIN_CNT];
+} InitiatorTargetProximityMatrix;
[SAMI] Please follow structure typedef and tag naming convention.
See https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/4_naming_conventions/45_name_space_rules#4-5-1-names-shall-be-used-consistently-within-the-same-type
[/SAMI]
+
+typedef struct {
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
+ InitiatorTargetProximityMatrix Matrix;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
+
+#pragma pack ()
+
+#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+ ) \
[SAMI] Align ). It would be preferable to follow the alignment style of a function. Indeed, a space before the starting parenthesis would not work.
[/SAMI]
+{ \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+}
+
+EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
+ // Header
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ ),
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ },
+
+ // Memory Proximity Domain
+ {
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x0, 0x0),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x1, 0x1),
+ },
+
+ // Latency Info
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+ 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMIAIN_CNT, 100),
+ {
+ {0, 1}, {0, 1},
+ {
+ 10, 20,
+ 20, 10,
+ }
+ },
+
+ // Memory Side Cache
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x0, SIZE_8MB,
[SAMI] Alignment. See https://edk2-docs.gitbook.io/edk-ii-c-coding-standards-specification/5_source_files/52_spacing#5-2-2-4-subsequent-lines-of-multi-line-function-calls-should-line-up-two-spaces-from-the-beginning-of-the-function-name
[/SAMI]
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x1, SIZE_8MB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+};
+
+VOID* CONST ReferenceAcpiTable = &Hmat;
[SAMI] Add a comment to indicate that the above line is to prevent the optimiser from discarding the table.
[/SAMI]
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [edk2-platforms] [PATCH v1 3/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RD-V1-MC
2021-01-28 13:42 [edk2-platforms] [PATCH v1 0/3] Add HMAT tables for RD multi-chip platforms Vijayenthiran Subramaniam
2021-01-28 13:42 ` [edk2-platforms] [PATCH v1 1/3] Platform/ARM/SgiPkg: Add helper macros for HMAT table Vijayenthiran Subramaniam
2021-01-28 13:42 ` [edk2-platforms] [PATCH v1 2/3] Platform/ARM/SgiPkg: Add HMAT ACPI table for RdN1EdgeX2 Vijayenthiran Subramaniam
@ 2021-01-28 13:42 ` Vijayenthiran Subramaniam
2 siblings, 0 replies; 10+ messages in thread
From: Vijayenthiran Subramaniam @ 2021-01-28 13:42 UTC (permalink / raw)
To: devel, leif, ardb+tianocore, sami.mujawar; +Cc: thomas.abraham
Add HMAT ACPI tables that is specific for RD-V1-MC quad-chip platform.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 138 ++++++++++++++++++++
2 files changed, 139 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index 051825993af0..f3552bc49003 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -22,6 +22,7 @@ [Sources]
Iort.aslc
Mcfg.aslc
RdV1Mc/Dsdt.asl
+ RdV1Mc/Hmat.aslc
RdV1Mc/Madt.aslc
RdV1Mc/Srat.aslc
Spcr.aslc
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
new file mode 100644
index 000000000000..a3218b9e2f0d
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
@@ -0,0 +1,138 @@
+/** @file
+* Heterogeneous Memory Attribute Table (HMAT)
+*
+* Copyright (c) 2020, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+
+#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
+#define INITATOR_PROXIMITY_DOMAIN_CNT 4
+#define TARGET_PROXIMITY_DOMIAIN_CNT 4
+
+//
+// HMAT Table
+//
+#pragma pack (1)
+
+typedef struct {
+ UINT32 InitatorProximityDomain[INITATOR_PROXIMITY_DOMAIN_CNT];
+ UINT32 TargetProximityDomiain[TARGET_PROXIMITY_DOMIAIN_CNT];
+ UINT16 MatrixEntry[INITATOR_PROXIMITY_DOMAIN_CNT * TARGET_PROXIMITY_DOMIAIN_CNT];
+} InitiatorTargetProximityMatrix;
+
+typedef struct {
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER Header;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES Proximity[CHIP_CNT];
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO LatencyInfo;
+ InitiatorTargetProximityMatrix Matrix;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache0;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache1;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache2;
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO MemSideCache3;
+} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
+
+#pragma pack ()
+
+#define HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT( \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+ ) \
+{ \
+ TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
+}
+
+EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat = {
+ // Header
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
+ EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ ),
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ },
+
+ // Memory Proximity Domain
+ {
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x0, 0x0),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x1, 0x1),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x2, 0x2),
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT (
+ 1, 0x3, 0x3),
+ },
+
+ // Latency Info
+ EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_INIT (
+ 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMIAIN_CNT, 100),
+ {
+ {0, 1, 2, 3}, {0, 1, 2, 3},
+ {
+ 10, 20, 20, 20,
+ 20, 10, 20, 20,
+ 20, 20, 10, 20,
+ 20, 20, 20, 10,
+ }
+ },
+
+ // Memory Side Cache
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x0, SIZE_1GB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x1, SIZE_1GB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x2, SIZE_1GB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+
+ EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ 0x3, SIZE_1GB,
+ HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
+ 1,
+ 1,
+ 2,
+ 2,
+ 64 // 64 bytes cache line length
+ ),
+ 0),
+};
+
+VOID* CONST ReferenceAcpiTable = &Hmat;
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread