Sec and Reset vector

[Rafael Machado <rafaelrodrigues.machado@gmail.com>]

Hi eveyrone

I'm doing some studies on edk2 and coreboot, but I'm having some questions
that I believe you can help.

On the journey to try to understand things since the beginning, so they
make sense in future, I'm trying to understand how does the Initial phases
of UEFI  / PI firmware work. To do that I got a bios image and start to
reverse it to check the modules and everything present at that bios. Now I
understand, at least the basics, about DXE and PEI phase.

The main question that I have now is about the SEC phase.
To try to understand the SEC phase I tried to reverse this firmware so I
could check the reset vector's first jump or something like that.
The surprise I have is that I was not able to find this code.

To be sure I was reversing on the correct way I generated a coreboot image.
On the image below we can see the initial code of a firmware generated
using coreboot

[image: pasted1]

But at the UEFI firmware I'm studying I'm not able to find anything similar
to that.
My guess before starting this was that at least the SEC initial code should
be similar to the legacy way of doing things, a jmp at 0xfff:fff0
and after that the magic should get started with all uefi phases.

Could someone please give me some light on that?


Thanks and Regards
Rafael R. Machado