From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt0-x232.google.com (mail-qt0-x232.google.com [IPv6:2607:f8b0:400d:c0d::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 296BA1A1E24 for ; Sat, 22 Oct 2016 09:28:28 -0700 (PDT) Received: by mail-qt0-x232.google.com with SMTP id f6so108349761qtd.2 for ; Sat, 22 Oct 2016 09:28:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:from:date:message-id:subject:to; bh=dYu7NBxcASPZ1fkwRMBlzGqBXBNhL6AMnPs5iGKoV1o=; b=d8TGtj2lnuGv1tbNycibuZ/4xzmGA669i0HvB32eejOZcfnU1APPTbNnD0EMtjl18E zO9ElrNBxu2H57MBARZ698XvgKylPQBIwFROThVKiFYdOIJRxRzocp3Qb830he3q83pk dN8LUeucw0h37ZSQ8+EepHkPpHykcCVmb3dr63Vg6ZvcneBk8QO2eD4+UbMT1ytl5v0j P154AnYroo+8LU4DC+pA+XbSRaDRqBsTiVqBDtz9JJ3NUY6ftS6Bmg0G1LBl0WM96ECm EzVhEfh7yKhxp0Yx4eFCWoVJKdaZYvksNYac+SCN/Cj9AiORsykCtyC4fTQJ02H4byRx SaPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=dYu7NBxcASPZ1fkwRMBlzGqBXBNhL6AMnPs5iGKoV1o=; b=Jb/EjjESPFi4XS2BtLphOzeWp3Kpq45yyRYurn3FNb5S7nkXHFeoPCA68Hl6TiyoV3 e42xoCAYMA448E68o9Ma9gUqcd8iScPUsDDWxBOqa17jlBCd5oXXy1tcq77c2RA6JjM2 4LSesriLZrvrCDL20VuNCFMBUc0zF/OZarrnR4VO0eiVswZCpgzkHyqU9qMbVFVtmA95 bbTmZ9BNB8s4XmSI0JRoM6tHorpmh8qHjmfyGBeg8HdITChl/9hkpNpxBaki9ylYeika Lv/cHPIL58lbPyrCX1jhZ3w9bSZfHj0ZYUXpzJKOQBVJTiGwJli8Ppc9uqdFA6D8+5Fk ZTWg== X-Gm-Message-State: ABUngvfG5QMIIDzA/3ZcNmD20xZO2LMa4PAXloO+943frM2YXJ/1a6rtcEhG3QDz6SktTSnpM4oQjZg01SzWJA== X-Received: by 10.200.48.49 with SMTP id f46mr7285108qte.64.1477153706307; Sat, 22 Oct 2016 09:28:26 -0700 (PDT) MIME-Version: 1.0 From: Rafael Machado Date: Sat, 22 Oct 2016 16:28:15 +0000 Message-ID: To: "edk2-devel@lists.01.org" X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: Sec and Reset vector X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 22 Oct 2016 16:28:28 -0000 Content-Type: text/plain; charset=UTF-8 Hi eveyrone I'm doing some studies on edk2 and coreboot, but I'm having some questions that I believe you can help. On the journey to try to understand things since the beginning, so they make sense in future, I'm trying to understand how does the Initial phases of UEFI / PI firmware work. To do that I got a bios image and start to reverse it to check the modules and everything present at that bios. Now I understand, at least the basics, about DXE and PEI phase. The main question that I have now is about the SEC phase. To try to understand the SEC phase I tried to reverse this firmware so I could check the reset vector's first jump or something like that. The surprise I have is that I was not able to find this code. To be sure I was reversing on the correct way I generated a coreboot image. On the image below we can see the initial code of a firmware generated using coreboot [image: pasted1] But at the UEFI firmware I'm studying I'm not able to find anything similar to that. My guess before starting this was that at least the SEC initial code should be similar to the legacy way of doing things, a jmp at 0xfff:fff0 and after that the magic should get started with all uefi phases. Could someone please give me some light on that? Thanks and Regards Rafael R. Machado