From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk0-x22d.google.com (mail-qk0-x22d.google.com [IPv6:2607:f8b0:400d:c09::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7BAFF21942335 for ; Thu, 6 Apr 2017 04:15:24 -0700 (PDT) Received: by mail-qk0-x22d.google.com with SMTP id h67so34114472qke.0 for ; Thu, 06 Apr 2017 04:15:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=El6nsW3ZVKRqhA1qBRxTeu+KjQcTjlTl25InxRtLFe8=; b=Xz52qu4dWcggqdG72wfMOOxD49/dZlg0/Kn1NTq/ctntgVqPyJUySJZsPBagJ8mbuk 4sHg7kkdY3fJWlVd+vYw+7C4/y7JJvZFt+BdCOkWTskqx7AvUhKeb892wOq42SH/L1+H g4lKXBdnrAN5f9oRlmjz8jLvi7u2Pc3SO3t88= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=El6nsW3ZVKRqhA1qBRxTeu+KjQcTjlTl25InxRtLFe8=; b=KwPaj4Kg+qedjpxuBoKT1h+PqI3T87rUeL3TGWk4o8K0BHZhmYX5MguFz8N4nYNH7Z m3f0Tr+t/27Tv9UbyrcNIocS+VadOhtrnBT6flWTgqFYJ6oKiaamCy7zQP6+Bmy443Ks AYQ5R4l5sexLWic1zU+fSFtHvZoVbMwc4bLNgjRIiQMZ+rToYPpZDoirgyFLmx6seDZN AulJAp8LJCbl+uIcnvTItFEcs1Rw8l/KBHmggEnyn9m8GXnNdZo1hffjU2VjUdM33V/x fsmFyabKNH+xU9IQikgH6aJtgmijrUvh7dyby0yi5lV130huNSH/dHo77sQqc/SttdNW p/wA== X-Gm-Message-State: AFeK/H1oZzi79XGrkrmnXGC+5gGndX1IYNchsJJ3j/Rw50LS9cTvgDiBuKuCv3Bolg8cHHyWun/mNj8QczCoKz5N X-Received: by 10.55.108.131 with SMTP id h125mr30414802qkc.199.1491477323534; Thu, 06 Apr 2017 04:15:23 -0700 (PDT) MIME-Version: 1.0 Received: by 10.140.36.138 with HTTP; Thu, 6 Apr 2017 04:15:22 -0700 (PDT) In-Reply-To: References: <1491424713-5203-1-git-send-email-ard.biesheuvel@linaro.org> <20170406093742.GS25239@bivouac.eciton.net> From: Ryan Harkin Date: Thu, 6 Apr 2017 12:15:22 +0100 Message-ID: To: Ard Biesheuvel Cc: Leif Lindholm , "edk2-devel@lists.01.org" , Jeremy Linton , Evan Lloyd Subject: Re: [PATCH 1/2] ArmPlatformPkg/HdLcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 11:15:24 -0000 Content-Type: text/plain; charset=UTF-8 On 6 April 2017 at 11:40, Ard Biesheuvel wrote: > On 6 April 2017 at 10:37, Leif Lindholm wrote: >> On Wed, Apr 05, 2017 at 09:38:32PM +0100, Ard Biesheuvel wrote: >>> Replace the uncached memory mapping of the framebuffer with a write- >>> combining one. This improves performance, and avoids issues with >>> unaligned accesses and DC ZVA instructions performed by the accelerated >>> memcpy/memset routines. >>> >>> Contributed-under: TianoCore Contribution Agreement 1.0 >>> Signed-off-by: Ard Biesheuvel >> >> If you can get a nod each from Ryan and Evan, for the series: >> Reviewed-by: Leif Lindholm >> >>> --- >>> ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c >>> index a57846715ed7..d6d47545c824 100644 >>> --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c >>> +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c >>> @@ -143,7 +143,7 @@ LcdPlatformGetVram ( >>> ASSERT_EFI_ERROR(Status); >>> >>> // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable. >>> - Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); >>> + Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_WC); >>> ASSERT_EFI_ERROR(Status); >>> if (EFI_ERROR(Status)) { >>> gBS->FreePool (VramBaseAddress); > > Actually, it would be more appropriate for this code to use DXE services, i.e., > > gDS->SetMemorySpaceAttributes (xxx) > > which internally calls Cpu->SetMemoryAttributes(), but also checks the > validity of the request against the capabilities of the region Ach! I've just tested this patch :-) Anyway, it works fine on TC2.