From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-x22b.google.com (mail-lf0-x22b.google.com [IPv6:2a00:1450:4010:c07::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7BA311A1E3A for ; Mon, 24 Oct 2016 04:47:25 -0700 (PDT) Received: by mail-lf0-x22b.google.com with SMTP id x79so200950607lff.0 for ; Mon, 24 Oct 2016 04:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=lgwc2IYXar4i9Pn7J/FGBNT2bZ/Gi0oU92xfogNFI8M=; b=bAwN5ItYVWqNgHDoGAhq4epPwofOvnILPNCex+5/62XagDHQU/k8f1VD3JPkzAhHf2 P6SpJSVqsEEElVEBf4ElhO8YR3zkb5EKk64zjDQshMg9ecUM8Dz4Gr+ppeAdgtL9H9Kj 08uWaGTzKnhnng/3Q3MTw3HLyMnSgNQV7PM5g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=lgwc2IYXar4i9Pn7J/FGBNT2bZ/Gi0oU92xfogNFI8M=; b=SkNdr6DH6qr5pxw/EeQ4XU/VlOGDXGxXf3B37/MjrfvissBLJSsT3RHfp+Xfa+iCnt Ylwwkyq6YxuZylbz1grsfaSZ0keFcywt7LIvaC1JQUl6yyIm0tnrsG308PYkMZXXNKv2 bMYwzDdKzQifzJHNhTtY0wTeatcRao2eiJYxBTUVDqucYlHj6PYGfexB8WhDVn4NduaS Kkgi7q/rktSsz2cS+8aIt7WQoxp6lqOkRL4KVmvJc6Sxa83oVRMhBWivwxn9QrVXIt8+ ai9pvE4x0q/GG3F6aHy3ILKcv6lPTwSPzSpcZvL/3ByoIdGfs5HegMsRU/SmWxY6j48q tl7A== X-Gm-Message-State: ABUngvcwRh4znR2RgAXhRUkjIg+5IrWQwKvdKnNFcMv+hDVbX53ZG/0uKBR2YJDwsW7xKml73eZ+/g54Nw1ZSsSZ X-Received: by 10.25.201.135 with SMTP id z129mr169976lff.144.1477309642799; Mon, 24 Oct 2016 04:47:22 -0700 (PDT) MIME-Version: 1.0 Received: by 10.25.28.78 with HTTP; Mon, 24 Oct 2016 04:47:21 -0700 (PDT) In-Reply-To: <1477278296-24809-1-git-send-email-dennis.chen@arm.com> References: <1477278296-24809-1-git-send-email-dennis.chen@arm.com> From: Ryan Harkin Date: Mon, 24 Oct 2016 12:47:21 +0100 Message-ID: To: Dennis Chen Cc: edk2-devel-01 , nd@arm.com, Laszlo Ersek , Leif Lindholm , Ard Biesheuvel Subject: Re: [PATCH] ARMPkg: Unified the GIC base address variables as 64-bit width X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 24 Oct 2016 11:47:26 -0000 Content-Type: text/plain; charset=UTF-8 On 24 October 2016 at 04:04, Dennis Chen wrote: > Since ACPI spec defines the GIC base addresses (CPU interface, > Distributor and Redistributor*GICv3 only*) as 64-bit, so we should > define these corresponding base address variables as 64-bit instead of > 32-bit. This patch redefines them according to the ACPI spec. > Following on with Ard's comment on the earlier version, what happens if you want to use GICv3 on a 32bit system, eg the Cortex-A32 FVP models, which I believe [1] has GICv3? [1] Go here and search for "gicv3" http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0834i/Chunk1955773768.html > Contributed-under: TianoCore Contribution Agreement 1.0 > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Laszlo Ersek > Signed-off-by: Dennis Chen > --- > ArmPkg/Drivers/ArmGic/ArmGicLib.c | 64 ++++++++++---------- > ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c | 2 +- > ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 4 +- > ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c | 6 +- > ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c | 4 +- > ArmPkg/Include/Library/ArmGicLib.h | 78 ++++++++++++------------- > 6 files changed, 79 insertions(+), 79 deletions(-) > > diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c > index e658e9b..733488c 100644 > --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c > +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c > @@ -41,18 +41,18 @@ SourceIsSpi ( > * @retval Base address of the associated GIC Redistributor > */ > STATIC > -UINTN > +UINT64 > GicGetCpuRedistributorBase ( > - IN UINTN GicRedistributorBase, > - IN ARM_GIC_ARCH_REVISION Revision > + IN UINT64 GicRedistributorBase, > + IN ARM_GIC_ARCH_REVISION Revision > ) > { > - UINTN Index; > - UINTN MpId; > - UINTN CpuAffinity; > - UINTN Affinity; > - UINTN GicRedistributorGranularity; > - UINTN GicCpuRedistributorBase; > + UINTN Index; > + UINTN MpId; > + UINTN CpuAffinity; > + UINTN Affinity; > + UINTN GicRedistributorGranularity; > + UINT64 GicCpuRedistributorBase; > > MpId = ArmReadMpidr (); > // Define CPU affinity as Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32] > @@ -87,7 +87,7 @@ GicGetCpuRedistributorBase ( > UINTN > EFIAPI > ArmGicGetInterfaceIdentification ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ) > { > // Read the GIC Identification Register > @@ -97,7 +97,7 @@ ArmGicGetInterfaceIdentification ( > UINTN > EFIAPI > ArmGicGetMaxNumInterrupts ( > - IN INTN GicDistributorBase > + IN UINT64 GicDistributorBase > ) > { > return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1); > @@ -106,10 +106,10 @@ ArmGicGetMaxNumInterrupts ( > VOID > EFIAPI > ArmGicSendSgiTo ( > - IN INTN GicDistributorBase, > - IN INTN TargetListFilter, > - IN INTN CPUTargetList, > - IN INTN SgiId > + IN UINT64 GicDistributorBase, > + IN UINTN TargetListFilter, > + IN UINTN CPUTargetList, > + IN UINTN SgiId > ) > { > MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId); > @@ -131,8 +131,8 @@ ArmGicSendSgiTo ( > UINTN > EFIAPI > ArmGicAcknowledgeInterrupt ( > - IN UINTN GicInterruptInterfaceBase, > - OUT UINTN *InterruptId > + IN UINT64 GicInterruptInterfaceBase, > + OUT UINTN *InterruptId > ) > { > UINTN Value; > @@ -162,8 +162,8 @@ ArmGicAcknowledgeInterrupt ( > VOID > EFIAPI > ArmGicEndOfInterrupt ( > - IN UINTN GicInterruptInterfaceBase, > - IN UINTN Source > + IN UINT64 GicInterruptInterfaceBase, > + IN UINTN Source > ) > { > ARM_GIC_ARCH_REVISION Revision; > @@ -181,9 +181,9 @@ ArmGicEndOfInterrupt ( > VOID > EFIAPI > ArmGicEnableInterrupt ( > - IN UINTN GicDistributorBase, > - IN UINTN GicRedistributorBase, > - IN UINTN Source > + IN UINT64 GicDistributorBase, > + IN UINT64 GicRedistributorBase, > + IN UINTN Source > ) > { > UINT32 RegOffset; > @@ -216,9 +216,9 @@ ArmGicEnableInterrupt ( > VOID > EFIAPI > ArmGicDisableInterrupt ( > - IN UINTN GicDistributorBase, > - IN UINTN GicRedistributorBase, > - IN UINTN Source > + IN UINT64 GicDistributorBase, > + IN UINT64 GicRedistributorBase, > + IN UINTN Source > ) > { > UINT32 RegOffset; > @@ -250,15 +250,15 @@ ArmGicDisableInterrupt ( > BOOLEAN > EFIAPI > ArmGicIsInterruptEnabled ( > - IN UINTN GicDistributorBase, > - IN UINTN GicRedistributorBase, > - IN UINTN Source > + IN UINT64 GicDistributorBase, > + IN UINT64 GicRedistributorBase, > + IN UINTN Source > ) > { > UINT32 RegOffset; > UINTN RegShift; > ARM_GIC_ARCH_REVISION Revision; > - UINTN GicCpuRedistributorBase; > + UINT64 GicCpuRedistributorBase; > UINT32 Interrupts; > > // Calculate enable register offset and bit position > @@ -286,7 +286,7 @@ ArmGicIsInterruptEnabled ( > VOID > EFIAPI > ArmGicDisableDistributor ( > - IN INTN GicDistributorBase > + IN UINT64 GicDistributorBase > ) > { > // Disable Gic Distributor > @@ -296,7 +296,7 @@ ArmGicDisableDistributor ( > VOID > EFIAPI > ArmGicEnableInterruptInterface ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ) > { > ARM_GIC_ARCH_REVISION Revision; > @@ -314,7 +314,7 @@ ArmGicEnableInterruptInterface ( > VOID > EFIAPI > ArmGicDisableInterruptInterface ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ) > { > ARM_GIC_ARCH_REVISION Revision; > diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c > index f90391b..bc01db9 100644 > --- a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c > +++ b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c > @@ -19,7 +19,7 @@ > VOID > EFIAPI > ArmGicEnableDistributor ( > - IN INTN GicDistributorBase > + IN UINT64 GicDistributorBase > ) > { > ARM_GIC_ARCH_REVISION Revision; > diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c > index b9ecd55..c7c5af1 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c > +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c > @@ -30,8 +30,8 @@ Abstract: > > extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol; > > -STATIC UINT32 mGicInterruptInterfaceBase; > -STATIC UINT32 mGicDistributorBase; > +STATIC UINT64 mGicInterruptInterfaceBase; > +STATIC UINT64 mGicDistributorBase; > > /** > Enable interrupt source Source. > diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c > index 5ac1d89..669ec99 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c > +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c > @@ -18,7 +18,7 @@ > UINTN > EFIAPI > ArmGicV2AcknowledgeInterrupt ( > - IN UINTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ) > { > // Read the Interrupt Acknowledge Register > @@ -28,8 +28,8 @@ ArmGicV2AcknowledgeInterrupt ( > VOID > EFIAPI > ArmGicV2EndOfInterrupt ( > - IN UINTN GicInterruptInterfaceBase, > - IN UINTN Source > + IN UINT64 GicInterruptInterfaceBase, > + IN UINTN Source > ) > { > MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source); > diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c > index 92b764f..a7adbaf 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c > +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c > @@ -20,7 +20,7 @@ > VOID > EFIAPI > ArmGicV2EnableInterruptInterface ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ) > { > /* > @@ -33,7 +33,7 @@ ArmGicV2EnableInterruptInterface ( > VOID > EFIAPI > ArmGicV2DisableInterruptInterface ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ) > { > // Disable Gic Interface > diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h > index 4364f3f..bf6405c 100644 > --- a/ArmPkg/Include/Library/ArmGicLib.h > +++ b/ArmPkg/Include/Library/ArmGicLib.h > @@ -101,7 +101,7 @@ > UINTN > EFIAPI > ArmGicGetInterfaceIdentification ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ); > > // > @@ -110,56 +110,56 @@ ArmGicGetInterfaceIdentification ( > VOID > EFIAPI > ArmGicSetupNonSecure ( > - IN UINTN MpId, > - IN INTN GicDistributorBase, > - IN INTN GicInterruptInterfaceBase > + IN UINTN MpId, > + IN UINT64 GicDistributorBase, > + IN UINT64 GicInterruptInterfaceBase > ); > > VOID > EFIAPI > ArmGicSetSecureInterrupts ( > - IN UINTN GicDistributorBase, > - IN UINTN* GicSecureInterruptMask, > - IN UINTN GicSecureInterruptMaskSize > + IN UINT64 GicDistributorBase, > + IN UINTN* GicSecureInterruptMask, > + IN UINTN GicSecureInterruptMaskSize > ); > > VOID > EFIAPI > ArmGicEnableInterruptInterface ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ); > > VOID > EFIAPI > ArmGicDisableInterruptInterface ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ); > > VOID > EFIAPI > ArmGicEnableDistributor ( > - IN INTN GicDistributorBase > + IN UINT64 GicDistributorBase > ); > > VOID > EFIAPI > ArmGicDisableDistributor ( > - IN INTN GicDistributorBase > + IN UINT64 GicDistributorBase > ); > > UINTN > EFIAPI > ArmGicGetMaxNumInterrupts ( > - IN INTN GicDistributorBase > + IN UINT64 GicDistributorBase > ); > > VOID > EFIAPI > ArmGicSendSgiTo ( > - IN INTN GicDistributorBase, > - IN INTN TargetListFilter, > - IN INTN CPUTargetList, > - IN INTN SgiId > + IN UINT64 GicDistributorBase, > + IN UINTN TargetListFilter, > + IN UINTN CPUTargetList, > + IN UINTN SgiId > ); > > /* > @@ -178,46 +178,46 @@ ArmGicSendSgiTo ( > UINTN > EFIAPI > ArmGicAcknowledgeInterrupt ( > - IN UINTN GicInterruptInterfaceBase, > - OUT UINTN *InterruptId > + IN UINT64 GicInterruptInterfaceBase, > + OUT UINTN *InterruptId > ); > > VOID > EFIAPI > ArmGicEndOfInterrupt ( > - IN UINTN GicInterruptInterfaceBase, > - IN UINTN Source > + IN UINT64 GicInterruptInterfaceBase, > + IN UINTN Source > ); > > UINTN > EFIAPI > ArmGicSetPriorityMask ( > - IN INTN GicInterruptInterfaceBase, > - IN INTN PriorityMask > + IN UINT64 GicInterruptInterfaceBase, > + IN UINTN PriorityMask > ); > > VOID > EFIAPI > ArmGicEnableInterrupt ( > - IN UINTN GicDistributorBase, > - IN UINTN GicRedistributorBase, > - IN UINTN Source > + IN UINT64 GicDistributorBase, > + IN UINT64 GicRedistributorBase, > + IN UINTN Source > ); > > VOID > EFIAPI > ArmGicDisableInterrupt ( > - IN UINTN GicDistributorBase, > - IN UINTN GicRedistributorBase, > - IN UINTN Source > + IN UINT64 GicDistributorBase, > + IN UINT64 GicRedistributorBase, > + IN UINTN Source > ); > > BOOLEAN > EFIAPI > ArmGicIsInterruptEnabled ( > - IN UINTN GicDistributorBase, > - IN UINTN GicRedistributorBase, > - IN UINTN Source > + IN UINT64 GicDistributorBase, > + IN UINT64 GicRedistributorBase, > + IN UINTN Source > ); > > // > @@ -230,34 +230,34 @@ ArmGicIsInterruptEnabled ( > VOID > EFIAPI > ArmGicV2SetupNonSecure ( > - IN UINTN MpId, > - IN INTN GicDistributorBase, > - IN INTN GicInterruptInterfaceBase > + IN UINTN MpId, > + IN UINT64 GicDistributorBase, > + IN UINT64 GicInterruptInterfaceBase > ); > > VOID > EFIAPI > ArmGicV2EnableInterruptInterface ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ); > > VOID > EFIAPI > ArmGicV2DisableInterruptInterface ( > - IN INTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ); > > UINTN > EFIAPI > ArmGicV2AcknowledgeInterrupt ( > - IN UINTN GicInterruptInterfaceBase > + IN UINT64 GicInterruptInterfaceBase > ); > > VOID > EFIAPI > ArmGicV2EndOfInterrupt ( > - IN UINTN GicInterruptInterfaceBase, > - IN UINTN Source > + IN UINT64 GicInterruptInterfaceBase, > + IN UINTN Source > ); > > // > -- > 2.7.4 > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel