From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qk0-x236.google.com (mail-qk0-x236.google.com [IPv6:2607:f8b0:400d:c09::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2E97021A6F108 for ; Thu, 6 Apr 2017 04:43:38 -0700 (PDT) Received: by mail-qk0-x236.google.com with SMTP id h67so34639115qke.0 for ; Thu, 06 Apr 2017 04:43:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=nbd00ZqVvLbDW4v/rvzfZbPIMAdqCx3dlrCyzRFOx6A=; b=PCiusIZ8KRWxKx5OCd3vgYRsXlr7YiL+hkM6AoUgrqC/actC3aZ7wbg9BM3vUg6wUG YAK04f0FhlhCMqiRNUDBMWwIEjp33iTeJYeTcJCF79+mT2GXHKTxTLdR+SxlfyyCt0QS 8R2+zgflfo3D5V62M09ks9BAQwOv8IPdr60/k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=nbd00ZqVvLbDW4v/rvzfZbPIMAdqCx3dlrCyzRFOx6A=; b=LKVJKZh5hiGL8aTnGN1Fuh9FXvtAF0HbbdRQlJ8skEf/pHCdZL5i2+2rkWeL+oRnax /xW5O17T+8EJlx/vV16Rbg7KAObNrmaKtWa5ofIftvjIXD09SesoQF6c/kzi3olbuMnO dgpKa5+lbAY90lP38golt4ryx/MnFhr4XKbyJe8ETPzbPqtt7Wv47V1MAuR9u2yIFFIp Fd28lLRGcCEuQygwNBKwABe1Lb8zeYScZSQp3G0uFsx6TWiaKTUdVHV1+ISokcs2GeKs F3Q+rR5+uw99OVH5ur7WoLPKWp7LbA1dP4/QI1mqzNa4SrTVjrDtukeW2sufISG+TyPj tCjw== X-Gm-Message-State: AFeK/H0yyE4c7gSmBIrzdgE3kU1H0mSnoO5UvUM/kxkp8dDKDzLJIASzf2PnfsyFOUFKKXQUzy3mJxLJtEEP5vjU X-Received: by 10.55.92.3 with SMTP id q3mr32790638qkb.164.1491479017289; Thu, 06 Apr 2017 04:43:37 -0700 (PDT) MIME-Version: 1.0 Received: by 10.140.36.138 with HTTP; Thu, 6 Apr 2017 04:43:36 -0700 (PDT) In-Reply-To: References: <1491424713-5203-1-git-send-email-ard.biesheuvel@linaro.org> <1491424713-5203-2-git-send-email-ard.biesheuvel@linaro.org> From: Ryan Harkin Date: Thu, 6 Apr 2017 12:43:36 +0100 Message-ID: To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Leif Lindholm , Jeremy Linton Subject: Re: [PATCH 2/2] ArmPlatformPkg/PL111LcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 11:43:38 -0000 Content-Type: text/plain; charset=UTF-8 On 6 April 2017 at 12:32, Ard Biesheuvel wrote: > On 6 April 2017 at 12:14, Ryan Harkin wrote: >> On 5 April 2017 at 21:38, Ard Biesheuvel wrote: >>> Replace the uncached memory mapping of the framebuffer with a write- >>> combining one. This improves performance, and avoids issues with >>> unaligned accesses and DC ZVA instructions performed by the accelerated >>> memcpy/memset routines. >>> >>> Contributed-under: TianoCore Contribution Agreement 1.0 >>> Signed-off-by: Ard Biesheuvel >> >> Well, ... PL111 isn't usually enabled for me. And if I enable it, >> neither Foundation nor AEMv8 models boot with or without this patch. >> >> So it's no worse than before.... >> > > Not even foundation model? That is strange ... > The reason we created a config without PL111 was because Foundation didn't originally have a PL111. And I wanted a single binary to run on Foundation and AEMv8. But ARM added it to Foundation about a year ago and I've never tried it. I'm happy for you to submit the patch if it works for you. >> >>> --- >>> ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c >>> index 2000c9bdf436..d18d6b3e1665 100644 >>> --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c >>> +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c >>> @@ -192,7 +192,7 @@ LcdPlatformGetVram ( >>> ASSERT_EFI_ERROR(Status); >>> >>> // Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable. >>> - Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); >>> + Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_WC); >>> ASSERT_EFI_ERROR(Status); >>> if (EFI_ERROR(Status)) { >>> gBS->FreePool(VramBaseAddress); >>> -- >>> 2.7.4 >>> >>> _______________________________________________ >>> edk2-devel mailing list >>> edk2-devel@lists.01.org >>> https://lists.01.org/mailman/listinfo/edk2-devel