From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-yb1-f178.google.com (mail-yb1-f178.google.com [209.85.219.178]) by mx.groups.io with SMTP id smtpd.web09.27582.1652699142748551214 for ; Mon, 16 May 2022 04:05:43 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=xqGMoTI1; spf=pass (domain: linaro.org, ip: 209.85.219.178, mailfrom: masahisa.kojima@linaro.org) Received: by mail-yb1-f178.google.com with SMTP id r11so26270279ybg.6 for ; Mon, 16 May 2022 04:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=pXV7G7tfTJXfJpmYKjCWOebM43ilhyveR5FhsvQOA4w=; b=xqGMoTI1lBPuYwwr/M0MdJ3LgMzqaV8mKFURb7c4UiALuXnZd7ZwehVmzErGEUoN8F e9LXBTuwGCtov2JFwM8GfLCXHGLZWmIJBKucsUwrSAA6WvLiQ6weGIgqvK/vVdrQgjhg eydm7qqL7CGF+To1qjbQ2j8FdDwG66Q0mF2yKqtyWP5TP0ZV8/DuE35L2chjrmAM7LX/ g0DMz0141cgu6R3NxqFblPr2jxWUk9gBRmTyjysKydQQBZrjtcJOHeb3ADKtXYqAlfM4 aR7GA0SNCjJZfP2MToYObsc1mFWS8J2f8WpWa2+SHdan6dDDZnA2iYuk6fMz8E4P5QRP eWgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=pXV7G7tfTJXfJpmYKjCWOebM43ilhyveR5FhsvQOA4w=; b=FYgusb9lTjbK5pHimig5hREdtmIdqqc1uYwYYCmb+pPUiz4+n6oY00nQalx7BoICYK NLDriGwXudk1wP1NOH3UuNAHRXY6DgKgMSna2iZEIxq7Rbrup8wI2vpP7/AZOSWzv9eX v28tqCcOeHZxBbdLiF/0NFqeaGmHnvQpv/EhHryMhRvVmTQMYOn/Vh/fTzUpNtoxSl5t Aa8RUR7YRWz10tJA0TnJfi9sYR2IHX0vWsy9aeRYE3eMHulXjSfrKgiFmar15KbMJVHB VIFRg/QGWb3dDORCeJ/CkuZKtOoYF/6M9eB1UNtaE3TPmPHSrDhYWI+HSvHIWSpyJ4t0 f0bw== X-Gm-Message-State: AOAM533Qb/2OI0zKPpIJqa43zkraUKSR+eT7ZoorXNmf3Qh1br35ri+a 2Nr2/tGCOlU+QVL93BCWz1eXiUEM3KUgr00zDCuuqA== X-Google-Smtp-Source: ABdhPJxqn4g2Edo+hAoZPiQNzu7lshSOsmOg54BbC+ZmzL2HEpvwFU9NrRfK7/DlC3KS5ra4yg9wrvyophDMNErdkc0= X-Received: by 2002:a05:6902:512:b0:64a:afe8:e94f with SMTP id x18-20020a056902051200b0064aafe8e94fmr16521141ybs.297.1652699141918; Mon, 16 May 2022 04:05:41 -0700 (PDT) MIME-Version: 1.0 References: <16EDB0E3E48BF3B9.11610@groups.io> In-Reply-To: <16EDB0E3E48BF3B9.11610@groups.io> From: "Masahisa Kojima" Date: Mon, 16 May 2022 20:05:30 +0900 Message-ID: Subject: Re: [edk2-devel] [PATCH edk2-platforms 1/1] Silicon/SynQuacer/Fip006Dxe: Support 4-bytes address for erase and write To: Ard Biesheuvel , Leif Lindholm Cc: Kazuhiko Sakamoto , masahisa.kojima@linaro.org, devel@edk2.groups.io Content-Type: text/plain; charset="UTF-8" Hi Ard, Leif, On Tue, 10 May 2022 at 17:25, Masahisa Kojima via groups.io wrote: > > From: Kazuhiko Sakamoto > > Support 4-bytes address for erase and write, so that we can > access whole region of SPI-NOR Flash(64MiB) implemented on the > Developerbox. > > This commit also fixes the wrong macro name. SPINOR_OP_SE and > SPINOR_OP_SE_4B is the commoand for 64KB block erase, > it must be SPINOR_OP_BE and SPINOR_OP_BE_4B. > > Signed-off-by: Masahisa Kojima > --- > Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h | 4 ++-- > Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c | 13 +++++-------- > 2 files changed, 7 insertions(+), 10 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h > index bade5706e6ae..3cb86ab588e0 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h > +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.h > @@ -313,7 +313,7 @@ NorFlashReadID ( > #define SPINOR_OP_BE_4K_PMC 0xd7 // Erase 4KiB block on PMC chips > #define SPINOR_OP_BE_32K 0x52 // Erase 32KiB block > #define SPINOR_OP_CHIP_ERASE 0xc7 // Erase whole flash chip > -#define SPINOR_OP_SE 0xd8 // Sector erase (usually 64KiB) > +#define SPINOR_OP_BE 0xd8 // Block erase (usually 64KiB) > #define SPINOR_OP_RDID 0x9f // Read JEDEC ID > #define SPINOR_OP_RDSFDP 0x5a // Read SFDP > #define SPINOR_OP_RDCR 0x35 // Read configuration register > @@ -329,7 +329,7 @@ NorFlashReadID ( > #define SPINOR_OP_PP_1_4_4_4B 0x3e // Quad page program > #define SPINOR_OP_BE_4K_4B 0x21 // Erase 4KiB block > #define SPINOR_OP_BE_32K_4B 0x5c // Erase 32KiB block > -#define SPINOR_OP_SE_4B 0xdc // Sector erase (usually 64KiB) > +#define SPINOR_OP_BE_4B 0xdc // Block erase (usually 64KiB) > #define SPINOR_OP_RD_ARRAY 0xe8 // Read array > #define SPINOR_OP_RD_NVCFG 0xb5 // Read non-volatile config register > #define SPINOR_OP_RD_VCR 0x85 // Read VCR register > diff --git a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c > index 8cdaa0eeb83f..b2ca0033ac13 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c > +++ b/Silicon/Socionext/SynQuacer/Drivers/Fip006Dxe/NorFlash.c > @@ -51,12 +51,10 @@ STATIC CONST CSDC_DEFINITION mN25qCSDCDefTable[] = { > { SPINOR_OP_READ_4B, TRUE, TRUE, FALSE, FALSE, CS_CFG_MBM_SINGLE, > CSDC_TRP_SINGLE }, > // Write Operations > - { SPINOR_OP_PP, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, > - CSDC_TRP_SINGLE }, > - { SPINOR_OP_PP_1_1_4, TRUE, FALSE, FALSE, TRUE, CS_CFG_MBM_QUAD, > + { SPINOR_OP_PP_4B, TRUE, TRUE, FALSE, TRUE, CS_CFG_MBM_SINGLE, > CSDC_TRP_SINGLE }, > // Erase Operations > - { SPINOR_OP_SE, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, > + { SPINOR_OP_BE_4B, FALSE, FALSE, FALSE, TRUE, CS_CFG_MBM_SINGLE, > CSDC_TRP_SINGLE }, > }; > > @@ -446,9 +444,8 @@ NorFlashEraseSingleBlock ( > BlockAddress -= Instance->RegionBaseAddress; > BlockAddress += Instance->OffsetLba * Instance->BlockSize; > > - NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq); > - MmioWrite32 (Instance->DeviceBaseAddress, > - SwapBytes32 (BlockAddress & 0x00FFFFFF) | SPINOR_OP_SE); > + NorFlashSetHostCommand (Instance, SPINOR_OP_BE_4B); > + MmioWrite32 (Instance->DeviceBaseAddress, SwapBytes32 (BlockAddress)); > NorFlashWaitProgramErase (Instance); > NorFlashSetHostCSDC (Instance, TRUE, mFip006NullCmdSeq); > > @@ -515,7 +512,7 @@ NorFlashWriteSingleWord ( > if (EFI_ERROR (NorFlashEnableWrite (Instance))) { > return EFI_DEVICE_ERROR; > } > - NorFlashSetHostCommand (Instance, SPINOR_OP_PP); > + NorFlashSetHostCommand (Instance, SPINOR_OP_PP_4B); > MmioWrite32 (WordAddress, WriteData); > NorFlashWaitProgramErase (Instance); Ping. If you could take a look, it would be much appreciated. Thanks, Masahisa Kojima > > -- > 2.17.1 > > > > > >