From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4003:c0f::241; helo=mail-ot0-x241.google.com; envelope-from=masahisa.kojima@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-ot0-x241.google.com (mail-ot0-x241.google.com [IPv6:2607:f8b0:4003:c0f::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 49484220E8CA1 for ; Mon, 16 Apr 2018 04:25:17 -0700 (PDT) Received: by mail-ot0-x241.google.com with SMTP id m22-v6so16912718otf.8 for ; Mon, 16 Apr 2018 04:25:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=RcYzmGsFgtsuFF6PsQ0+btO4VkHsb26hdA/hJxSa6fg=; b=MMo9tBBbGxAUz8Fcr8JPxBAR4a/sp68TF9dtmwGt8MLsT2wcZYuyzuz/n1oyXndx8s B2Hd6jgvm+l8s1eNK5yeRgJRzqbaGxfRfq7WiJIk1dyNSlHRpqmkfHpzYoKwes4/nmrw yB47dq0adJiXBnStMTUnRsS2YmT+LI6/RSdzQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=RcYzmGsFgtsuFF6PsQ0+btO4VkHsb26hdA/hJxSa6fg=; b=YREE1XlkFhSQwt8KRhjVYuMj2bBdB3l4DovZ0mj2FNc8vfowrCIgqiwKeMB2cZ6s/t 4IywKST6yIeOzegqd+9Fx5xChj5vzj/1TvCRrvuXQV+ceEAggBA+UTGzlIPzrdjPqKGs yC4xnjJ0g1UkVNaBJ9lVJtU0gc4ZNkFPwy+F7k3h4NBjIzLbVfd40i5XCik8oqfuGXhh BXYSLHMwLLXmv98rG4H0PDM1NZP+jKpRdCKw/AotonoOXjwx8GD8GnO/7vBjzNPn3CgJ OxgzbAKho3hzFOxRUAgrUz9Bk2VuQoONVz2C/IA9WUp49OZYEarpvZovyRl7PvNB8p9K uCgg== X-Gm-Message-State: ALQs6tC5c9pSIaCWSWvn8mRr06bntvbNdJ46y+9QJXLZkE6Emg9q9ePr izNzqJ8GwImfOHnm6LJ4JMfA6jrKmPE57a6xeA9KRg== X-Google-Smtp-Source: AIpwx4+Y7XbyL/78Maij+BOVp+aZviPZx3uFstrphkT7HO3YwN/iwAqHPpmHbGOVntXvEmQHdKyBt+JLyAYFsSEKea4= X-Received: by 2002:a9d:1b67:: with SMTP id l94-v6mr2175027otl.198.1523877916169; Mon, 16 Apr 2018 04:25:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.74.80.135 with HTTP; Mon, 16 Apr 2018 04:25:15 -0700 (PDT) In-Reply-To: <20180416110058.16952-1-ard.biesheuvel@linaro.org> References: <20180416110058.16952-1-ard.biesheuvel@linaro.org> From: Masahisa Kojima Date: Mon, 16 Apr 2018 20:25:15 +0900 Message-ID: To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, Leif Lindholm , Jassi Brar X-Mailman-Approved-At: Mon, 16 Apr 2018 08:24:54 -0700 Subject: Re: [PATCH edk2-platforms] Silicon/Socionext/SynQuacer: update PHY reference clock rate X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Apr 2018 11:25:17 -0000 Content-Type: text/plain; charset="UTF-8" Hi Ard, > Please confirm that the modification to ogma_config.h is correct. Thank you very much for your update. We confirmed and your modification is correct. Regards, Masahisa On 16 April 2018 at 20:00, Ard Biesheuvel wrote: > As reported by Kojima-san, the PHY reference clock value we use in our > ACPI and DT descriptions is out of sync with the hardware. Replace > 125 MHz with 250 MHz throughout. > > Cc: Masahisa Kojima > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Kojima-san, > > Please confirm that the modification to ogma_config.h is correct. > > Thanks, > Ard. > > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 2 +- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 ++-- > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > index b6f6c4360029..3f73c191d4d6 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > @@ -162,7 +162,7 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", > Package (2) { "phy-channel", FixedPcdGet32 (PcdNetsecPhyAddress) }, > Package (2) { "max-speed", 1000 }, > Package (2) { "max-frame-size", 9000 }, > - Package (2) { "socionext,phy-clock-frequency", 125000000 }, > + Package (2) { "socionext,phy-clock-frequency", 250000000 }, > } > }) > } > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 6e93c6ae16a8..f6887329f6c7 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -420,9 +420,9 @@ > reg-shift = <2>; > }; > > - clk_netsec: refclk125mhz { > + clk_netsec: refclk250mhz { > compatible = "fixed-clock"; > - clock-frequency = <125000000>; > + clock-frequency = <250000000>; > #clock-cells = <0>; > }; > > diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > index 1caf64e30623..f6ec9b30ec8e 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/ogma_config.h > @@ -16,8 +16,8 @@ > #ifndef OGMA_CONFIG_H > #define OGMA_CONFIG_H > > -#define OGMA_CONFIG_CLK_HZ 125000000UL > -#define OGMA_CONFIG_GMAC_CLK_HZ 125000000UL > +#define OGMA_CONFIG_CLK_HZ 250000000UL > +#define OGMA_CONFIG_GMAC_CLK_HZ 250000000UL > #define OGMA_CONFIG_CHECK_CLK_SUPPLY > > #define OGMA_CONFIG_USE_READ_GMAC_STAT > -- > 2.17.0 >