From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) by mx.groups.io with SMTP id smtpd.web10.35123.1674611104901529173 for ; Tue, 24 Jan 2023 17:45:05 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@google.com header.s=20210112 header.b=eQg3sWvV; spf=pass (domain: google.com, ip: 209.85.218.42, mailfrom: lisik@google.com) Received: by mail-ej1-f42.google.com with SMTP id ss4so43698815ejb.11 for ; Tue, 24 Jan 2023 17:45:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=bcQ/j1jNPc8XW+hXXv3TqqSs0egZ0ecbRIxB2KmwDgQ=; b=eQg3sWvV+pRHxLkMfQFCul9sN32RzobVyONacHrzXr/eC4WS1JbVW4nT1bQ6uPvO8m q/c/fTh7ZYc4JCmTFy0xL4kldkaoDcYJkEQObGr3o7EiHe2llBIhtQXeJzQbrEiO+Pbu EgbhbERyGMdrpkSsCFPHUNPNa3NtxEIA5SEmwT2V0ypa2IIlYdXfysG7H/Nqum/HF5LE vOuLfkYroe6Li1c3sgrD+yQwafzs+bAcnv1yBKp6A+rgfcmhn6wvaijEb1JeV5m+Xvjk ohtmVL3VgwMlAdyRbUKapSbxFBnUQrZjQLeajsy1G15D9Sx3siNSqR/2K+Kj6zZ1Mc8b nGzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=bcQ/j1jNPc8XW+hXXv3TqqSs0egZ0ecbRIxB2KmwDgQ=; b=BlnqZYtVGuG4vmC5u7YGvnsqfC4eiJFKR03QmOz7vyy9Jk4MHKGqZD/r9wHeKkWZnA cZMQLYtVqZHk5j17pAS4JIj/rS8BR01iGI1VqU4K+YS+w7+1FVRklC+seAVUOLgVqEOn Y1MnNoG0/xpmbwPZjK5Rc6QDCUnyKEognILhf/z0/1KiC3sxEWA8y6mXEAOCUzhebJl3 IOylAlP3wOEHmxoVKGEm5gHuF1GRN0Lge5U+oPvxl7pIZ9WGmcGu6vz2MV0TbiWJHRVo CERuXocR4reu3+ygu2lCaijsWa3RD7a/RDNiHnxEZO9F0Kfk1D5mHxTjeR7K6YPnHbsD +osg== X-Gm-Message-State: AFqh2krPntG1zX6EJUczOsAD4Gnv3LSxmg9zHKPfORK5ypG902kTlN58 F/2nLvIMqJBMkkjXViR8tRaURMOhY4+7ZBNvJezSgw== X-Google-Smtp-Source: AMrXdXvYOrzkQmjMWSHWFzHn2KROc+9bR01AXt6Ip6abe59z2wbMGDfE0/JKvBAIipZawmQSBxW2beNWsvyiPJyIN+E= X-Received: by 2002:a17:906:bcee:b0:84d:39d2:be19 with SMTP id op14-20020a170906bcee00b0084d39d2be19mr3976660ejb.363.1674611103158; Tue, 24 Jan 2023 17:45:03 -0800 (PST) MIME-Version: 1.0 References: <5e1916c6669ee2a918a2c22b7698e96f7dbf5488.1673568149.git.lisik@google.com> In-Reply-To: From: "Mikolaj Lisik" Date: Tue, 24 Jan 2023 17:44:51 -0800 Message-ID: Subject: Re: [edk2-devel] [PATCH] OvmfPkg: Create additional PML4 entries for large SEV-SNP VMs To: Pedro Falcato Cc: devel@edk2.groups.io, Erdem Aktas , James Bottomley , "Yao, Jiewen" , Min Xu , Tom Lendacky , michael.roth@amd.com Content-Type: text/plain; charset="UTF-8" Thanks for the review! > Please swap the Present and ReadWrite lines. You should only set > Present after everything else as to avoid explicit caching (TLB and > paging structure) issues. > > Although this whole file is full of spotty behavior. ASSERTS can get > deleted and the file is full of them. Yes, keeping consistency with the rest of the file was my main motivation for doing things this way. Will add popper error handling bere in V2. > There are plenty of Present = 1 sets before setting other important > bits like RW, which *will* cause you to get bad TLB entries if the CPU > speculates a load/store to that address. ... > *sigh* > In any case, because of that CpuFlushTlb () your patch isn't wrong, > but it should be changed into something more MMU-code natural. Makes sense! Thanks for all this information. Yes, I simply wanted to order setting of the bits exactly as they have been done before in the file. Will adjust in V2 and send a second patch adjusting them for other instances. Mikolaj