From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400c:c05::229; helo=mail-vk0-x229.google.com; envelope-from=heyi.guo@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-vk0-x229.google.com (mail-vk0-x229.google.com [IPv6:2607:f8b0:400c:c05::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0C7CB21F30413 for ; Fri, 29 Sep 2017 12:15:51 -0700 (PDT) Received: by mail-vk0-x229.google.com with SMTP id q190so322566vkd.13 for ; Fri, 29 Sep 2017 12:19:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=xv74tyhPlPelpRm7OIyIxFNzeNM8D2aNjy5KZGXsWIQ=; b=XM/3TYfPMimSNXvK/aetzbVr54eMIKjJyT5NN/3hHnmtDphgMqLl3bGNFo149N1crh CjKE3nTwfVx7Vvtirs0BvZlQYJSh/RgvghhLaATmR+tbgl0MXshHgofCnNrITbtRfM4x TzLQUqNtSFwILOupzg525Q1tGNqIjm1DdDtvY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=xv74tyhPlPelpRm7OIyIxFNzeNM8D2aNjy5KZGXsWIQ=; b=DaMW5sw/SQnhAWQYJvC1HE0+AL3mI+0bY1Evzp+d/OPy2dF+L+74jfGT5DjMR1uf/k vp3pyexoscGIpbqxYHuKvK6c3d2ix5DO+u2HRIyDBEGciNI+HbUkUUlhYvqDjw33seu4 GHjhIx/nP1+JlMLKoCtxFQcknoWAA1eDRi0pu4hMTqivywY13Y56Zf1WxEA7KGBkYjs9 DDFWZt+i4ZbkJzAuIyZE4nOC2boOkkyP6wohy5GnRSf/8LCX9end4nStl9q9pGVOL5g4 C3BXTBQysfCi5n+WheMZErTSLfNy4u3tVZgaw35XdMTnj3yHT0LdejASlrO4tTyofkE9 Yn6A== X-Gm-Message-State: AMCzsaXpsHyV5pQc37HFY49+H4yk96NlRBwE3Jm3JqpkB3lJvo3JzVVu f2syq92q2gB/kRbqV+uRH8NA7ZpM5vTPGrXDKR53yA== X-Google-Smtp-Source: AOwi7QCpC+A6hz0PJ72BvHrt5993rQcNgy4sJwcUOhm/dfQO9oXYwhmTGYegf1drFIIsfwbCCk6nZ+sy8Ih7h98fI2Y= X-Received: by 10.31.190.77 with SMTP id o74mr2797703vkf.39.1506712746945; Fri, 29 Sep 2017 12:19:06 -0700 (PDT) MIME-Version: 1.0 Received: by 10.103.18.71 with HTTP; Fri, 29 Sep 2017 12:19:06 -0700 (PDT) In-Reply-To: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> References: <1506655190-56231-1-git-send-email-heyi.guo@linaro.org> From: Heyi Guo Date: Sat, 30 Sep 2017 03:19:06 +0800 Message-ID: To: Leif Lindholm , Linaro UEFI Mailman List , "edk2-devel@lists.01.org" , G Gregory Cc: Ard Biesheuvel , Guoheyi , wanghuiqiang , Ming Huang , Jason Zhang , Mengfanrong , waip23@126.com X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: [PATCH edk2-platforms v5 00/11] Improve D0x platforms and bug fix X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Sep 2017 19:15:52 -0000 Content-Type: text/plain; charset="UTF-8" On 2017/9/29 11:19, Heyi Guo wrote: Code can also be found in github:https://github.com/hisilicon/OpenPlatformPkg.git branch: rp-1710-platforms-v5 Note: 1. There may be some minor issue (or even in SoC IP) that causes D05/3 into exception, which was just found when we updated edk2 and edk2-platforms. We will continue to investigate the issue. This issue might be caused by below code: --- a/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c +++ b/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceIo.c @@ -465,6 +465,10 @@ PciIoPciRead ( Address = (UINT8 *)&Dev->ConfigSpace + Offset; Length = Count << ((UINTN)Width & 0x3); + if (Offset > sizeof (Dev->ConfigSpace)) { + Special process and return; + } + if (Offset + Length > sizeof (Dev->ConfigSpace)) { // // Read all zeroes for config space accesses beyond the first If the input Offset is larger than sizeof (Dev->ConfigSpace), we should not go on the following code, or else the memory between Buffer + sizeof (Dev->ConfigSpace) - Offset ~ Buffer will be seriously corrupted. The bug will be triggered when the PCD PcdTurnOffUsbLegacySupport is true and HcCapParams contains some value larger than 0x40, for EHCI controller. We'd better also turn off this PCD for our platforms, since there are no real ExtendCap registers for our EHCI controller. However, even after fixing this, we still got another exception for alignment fault, which needs addtional time to investigate. Regards, Heyi It boot successfully by switch the VirtualEhciPciIo with old one. 2. The separate patch (Add AddressTranslationOffset support) is a prerequisite for this series and it's source can also be found in above branch(rp-1710-platforms-v5). Chenhui Sun (1): Hisilicon/D03: Disable the function of PerfTuning Heyi Guo (4): Hisilicon/D05: Modify dsc and fdf file Hisilicon/D03: Modify dsc and fdf file Hisilicon: Fix the drivers use the same GUID issue Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase Jason zhang (1): Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. Ming Huang (5): Hisilicon D03/D05: get firmware version from FIRMWARE_VER Hisilicon/D05/Pcie: fix bug of size definition D05/PCIe: Modify PcieRegionBase of secondary chip D05/ACPI: Disable D05 SAS0 and SAS2 D05/ACPI: Modify I2C device Platform/Hisilicon/D02/EarlyConfigPeim/EarlyConfigPeim.inf | 2 +- Platform/Hisilicon/D02/FdtUpdateLibD02/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D02/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- Platform/Hisilicon/D02/OemNicConfigD02/OemNicConfigD02.inf | 2 +- Platform/Hisilicon/D03/D03.dsc | 12 ++- Platform/Hisilicon/D03/D03.fdf | 4 +- Platform/Hisilicon/D03/Library/FdtUpdateLib/FdtUpdateLib.inf | 2 +- Platform/Hisilicon/D05/D05.dsc | 83 +++++++++-------- Platform/Hisilicon/D05/D05.fdf | 4 +- Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf | 2 +- Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 2 +- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf | 2 +- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 38 ++++---- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 7 ++ Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 94 +++++++++++++++++++- Silicon/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf | 2 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 3 +- Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 50 ----------- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl | 20 +---- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 8 +- Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl | 10 +++ Silicon/Hisilicon/HisiPkg.dec | 1 - Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 +- Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLib.inf | 2 +- Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf | 2 +- 26 files changed, 203 insertions(+), 157 deletions(-)