Re: [edk2-devel] [edk2-platforms][PATCH V4 1/4] Silicon/ARM/NeoverseN1Soc: Extract NT_FW_CONFIG address passed by TF-A

["sahil" <sahil@arm.com>]

Hi All,

Please find the links to previous discussions below :

V1 -
https://edk2.groups.io/g/devel/topic/96088980#100022
V2 -
https://edk2.groups.io/g/devel/topic/96671861#103652
V3 -
https://edk2.groups.io/g/devel/topic/100912169#112452

Thanks,
Sahil

On Thu, 4 Jan 2024 at 18:46, sahil <sahil@arm.com> wrote:
>
> NT_FW_CONFIG DTB contains platform information passed by TF-A boot
> stage. This patch enables support to first extract address of
> NT_FW_CONFIG and then pass it to other modules as a PPI.
>
> Signed-off-by: sahil <sahil@arm.com>
> ---
>  Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec                    |  5 ++++-
>  Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf  |  3 ++-
>  Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h              |  9 ++++++---
>  Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c    | 12 +++++++++++-
>  Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S |  4 +++-
>  5 files changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> index d59f25a5b915..c04162e7e7cd 100644
> --- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> +++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
> @@ -1,7 +1,7 @@
>  ## @file
>  #  Describes the entire platform configuration.
>  #
> -#  Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.<BR>
> +#  Copyright (c) 2018 - 2024, ARM Limited. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> @@ -83,3 +83,6 @@
>    gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F
>    gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
>    gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
> +
> +[Ppis]
> +  gArmNeoverseN1SocParameterPpiGuid = { 0x4DDD5A72, 0x31AD, 0x4B20, { 0x8F, 0x5F, 0xB3, 0xE8, 0x24, 0x6F, 0x80, 0x2B } }
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> index 96e590cdd810..ead7f11ec964 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
> @@ -1,7 +1,7 @@
>  ## @file
>  #  Platform Library for N1Sdp.
>  #
> -#  Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
> +#  Copyright (c) 2018-2024, ARM Limited. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> @@ -63,3 +63,4 @@
>
>  [Ppis]
>    gArmMpCoreInfoPpiGuid
> +  gArmNeoverseN1SocParameterPpiGuid
> diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
> index 097160c7e2d1..2bddf5007431 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
> +++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h
> @@ -1,6 +1,6 @@
>  /** @file
>  *
> -* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved.
> +* Copyright (c) 2018 - 2024, ARM Limited. All rights reserved.
>  *
>  * SPDX-License-Identifier: BSD-2-Clause-Patent
>  *
> @@ -55,12 +55,15 @@
>  typedef struct {
>    /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */
>    UINT8   MultichipMode;
> -  /*! Slave count in C2C mode */
> -  UINT8   SlaveCount;
> +  /*! Secondary chip count in C2C mode */
> +  UINT8   SecondaryChipCount;
>    /*! Local DDR memory size in GigaBytes */
>    UINT8   LocalDdrSize;
>    /*! Remote DDR memory size in GigaBytes */
>    UINT8   RemoteDdrSize;
>  } NEOVERSEN1SOC_PLAT_INFO;
>
> +typedef struct {
> +  CONST VOID    *NtFwConfig;
> +} NEOVERSEN1SOC_EL3_FW_HANDOFF_PARAM_PPI;
>  #endif
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
> index c0effd37f333..e8568b7a039b 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c
> @@ -1,6 +1,6 @@
>  /** @file
>
> -  Copyright (c) 2018-2021, ARM Limited. All rights reserved.<BR>
> +  Copyright (c) 2018 - 2024, ARM Limited. All rights reserved.<BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -8,8 +8,12 @@
>
>  #include <Library/ArmPlatformLib.h>
>  #include <Library/BaseLib.h>
> +#include <NeoverseN1Soc.h>
>  #include <Ppi/ArmMpCoreInfo.h>
>
> +UINT64  gArgNtFwConfigDtPtr;
> +STATIC  NEOVERSEN1SOC_EL3_FW_HANDOFF_PARAM_PPI mNeoverseN1SocParameterPpi;
> +
>  STATIC ARM_CORE_INFO mCoreInfoTable[] = {
>    { 0x0, 0x0 }, // Cluster 0, Core 0
>    { 0x0, 0x1 }, // Cluster 0, Core 1
> @@ -46,6 +50,7 @@ ArmPlatformInitialize (
>    IN     UINTN                  MpId
>    )
>  {
> +  mNeoverseN1SocParameterPpi.NtFwConfig = (VOID *)gArgNtFwConfigDtPtr;
>    return RETURN_SUCCESS;
>  }
>
> @@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
>      EFI_PEI_PPI_DESCRIPTOR_PPI,
>      &gArmMpCoreInfoPpiGuid,
>      &mMpCoreInfoPpi
> +  },
> +  {
> +    EFI_PEI_PPI_DESCRIPTOR_PPI,
> +    &gArmNeoverseN1SocParameterPpiGuid,
> +    &mNeoverseN1SocParameterPpi
>    }
>  };
>
> diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
> index 8d2069dea837..828c383d6892 100644
> --- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
> +++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S
> @@ -1,6 +1,6 @@
>  /** @file
>  *
> -*  Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
> +*  Copyright (c) 2019 - 2024, ARM Limited. All rights reserved.
>  *
>  *  SPDX-License-Identifier: BSD-2-Clause-Patent
>  *
> @@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
>  // the UEFI firmware through the CPU registers.
>  //
>  ASM_PFX(ArmPlatformPeiBootAction):
> +  adr  x10, gArgNtFwConfigDtPtr
> +  str  x0, [x10]
>    ret
>
>  //
> --
> 2.25.1
>
>
>
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