From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::32a; helo=mail-wm1-x32a.google.com; envelope-from=marcandre.lureau@gmail.com; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D11312115990A for ; Thu, 27 Sep 2018 03:59:31 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id r1-v6so17204362wmh.0 for ; Thu, 27 Sep 2018 03:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to:cc :content-transfer-encoding; bh=hghOUVPAkxyVhYXz4MVPtOj5lSUQPlAMQuEr1d2laPA=; b=E7NiztMPqA0FN+RCKe4s9HwTlLTgbEzzmJtFChzjPH8PHLAdeVaa39zMIElJCBWKov c4hqmQS7gSpC8If/q18zN4LjDI/c834k1/cZEA0En3Qit6v2va8wEU/mfShsgZAwqtye 2CalRpqPlVVAXWlff7bndWIaq7ImCsiI6F7x2qghXd4vdqZ+u7MtCwWwaoMc4G+k54b+ JX50DnlveiWzM3RfI7qptozIr7ouiJUNk2bthe8L6PwJ0/ndbraN5OclXeDSwV76napq gZghul6oppS/45giUeqlhR+rEjbE7N292EYCZFu7x34uxSmH4zrFmNQF9gPsasoT/p8k qOSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc :content-transfer-encoding; bh=hghOUVPAkxyVhYXz4MVPtOj5lSUQPlAMQuEr1d2laPA=; b=eKDD3PVzH4yX2b9BgTqdpJE9Nc7TLWG4XndKLPLpk28HETHG1+OpYiDT7GdwvqZoX8 tKN/zIHa801bLRDQQTAFx3vvcmy6wNgSb3dVj5BrxwASOG5jdEu650eZhIPpCuTQki4E 9RdnRbh4HfvhOcIG7ULw4GCX6jz3rObYxiSSPhw/fGoaOtrb1BaxtIdiHvyH/cgmPvfD 5+Mc7PtnSfGxBLbM/wczGdEa2AHtfM3iKsUc6LQzCgAcNKJq3aJ/g5ng0AxLb5epEJeV wop+b4PW6q+5TkQGXlben7gE3bzf4SMh4MGohOLOj4U/PUCQvT3IaF4n4mtrqFv1lBfv 2GVg== X-Gm-Message-State: ABuFfohQyl74HZL3Dbgb8ASTuPOidV0KB0iuenlahd2xmc/sBySD+Gd6 zPATgTzMbJCTuZq26nev82aoUCvbt1p0k8WCnNWA77/E5n0= X-Google-Smtp-Source: ACcGV63k2r1Kdx/aWUG+b0H1baVK+DOn8XnRIGM6pf4GnfzOghZ9oxXu0Ucth0Sl+5xopEu30uGadCRb9IlnQO/rlFg= X-Received: by 2002:a1c:3795:: with SMTP id e143-v6mr2698501wma.9.1538045969644; Thu, 27 Sep 2018 03:59:29 -0700 (PDT) MIME-Version: 1.0 From: =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= Date: Thu, 27 Sep 2018 14:59:17 +0400 Message-ID: To: edk2-devel@lists.01.org Cc: Chao Zhang , Laszlo Ersek , michael.d.kinney@intel.com, Paolo Bonzini Subject: TCG MOR and processor caches X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Sep 2018 10:59:32 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi, According to "TCG Platform Reset Attack Mitigation Specification", if MOR bit is set, "it must initiate a vendor-specific method that overwrites all of system memory and the processor caches" In QuarkPlatformPkg/Platform/Pei/PlatformInit/MemoryCallback.c and QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c, there is some code to clear RAM, however I don't see code that would clear the processor caches. For edk2/qemu, Paolo suggested it may be simpler to clear the cache unconditionally. How would you implement that? Using EFI_CPU_ARCH_PROTOCOL.FlushDataCache? (or direct AsmWbinvd call) thanks --=20 Marc-Andr=C3=A9 Lureau