From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=thomas.abraham@arm.com; receiver=edk2-devel@lists.01.org Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id F2018211A1E5A for ; Wed, 19 Dec 2018 01:03:22 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2B2331596 for ; Wed, 19 Dec 2018 01:03:22 -0800 (PST) Received: from mail-it1-f176.google.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0F8023F7F3 for ; Wed, 19 Dec 2018 01:03:22 -0800 (PST) Received: by mail-it1-f176.google.com with SMTP id i145so8560562ita.4 for ; Wed, 19 Dec 2018 01:03:22 -0800 (PST) X-Gm-Message-State: AA+aEWbGypeHoYBhQ7kahfXyMnPyuD/dkSKTtLY1spkmpNz9ZjqRNb5r BtNTDaGKcfGmT9NXVs4A8aSfkSgajw1SEqm3xMs= X-Google-Smtp-Source: AFSGD/VkRZf0UknOy1pF1Vdod0bBusPFyu2pNojh6L5bVn7W1iGSSedolRKM8kyAbLYfatVxBBKbI1HJIYtgFO6FXA4= X-Received: by 2002:a05:660c:283:: with SMTP id s3mr5947044itl.135.1545210201244; Wed, 19 Dec 2018 01:03:21 -0800 (PST) MIME-Version: 1.0 References: <20181218131015.20062-1-ard.biesheuvel@linaro.org> <20181218131015.20062-3-ard.biesheuvel@linaro.org> <20181218133955.avtfxupuaoj2a6iv@bivouac.eciton.net> In-Reply-To: From: Thomas Abraham Date: Wed, 19 Dec 2018 14:33:09 +0530 X-Gmail-Original-Message-ID: Message-ID: To: Ard Biesheuvel Cc: Leif Lindholm , "edk2-devel@lists.01.org" Subject: Re: [PATCH 2/4] ArmPlatformPkg/SP805WatchdogDxe: switch to interrupt mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Dec 2018 09:03:23 -0000 Content-Type: text/plain; charset="UTF-8" Hi Ard, On Tue, Dec 18, 2018 at 9:59 PM Ard Biesheuvel wrote: > > On Tue, 18 Dec 2018 at 14:39, Leif Lindholm wrote: > > > > On Tue, Dec 18, 2018 at 02:10:12PM +0100, Ard Biesheuvel wrote: > > > The SP805 watchdog driver doesn't implement the PI watchdog protocol > > > fully, but always simply resets the system if the watchdog time runs > > > out. > > > > > > However, the hardware does support the intended usage model, as long > > > as the SP805 is wired up correctly. So let's implement interrupt based > > > mode involving a handler that is registered by the DXE core and invoked > > > when the watchdog runs out. In the interrupt handler, we invoke the > > > notify function if one was registered, or call the ResetSystem() > > > runtime service otherwise (as per the UEFI spec) > > > > The only question mark from my end is - what happens when the > > interrupt isn't wired up correctly? Would it be worth to bail out and > > refuse to register the driver if PcdSP805WatchdogInterrupt is set to > > 0? > > > > Thomas? > > > > I have left the code in place that enables the hard reset, but the > timeout is double the programmed value (since the countdown timer is > restarted on an interrupt, and the hard reset is generated when it > reaches zero the second time) > > This should cover both the miswired interrupt scenario, and the > scenario where ResetSystem() (or the handler) gets stuck and never > returns. Yes, this would suffice. But the system would reset after twice the amount of time than programmed, which probably is okay. -Thomas. > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel