From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.1778.1595355829349022223 for ; Tue, 21 Jul 2020 11:23:49 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: thomas.abraham@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 24DCF106F for ; Tue, 21 Jul 2020 11:23:48 -0700 (PDT) Received: from mail-il1-f176.google.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0EC083F7BB for ; Tue, 21 Jul 2020 11:23:48 -0700 (PDT) Received: by mail-il1-f176.google.com with SMTP id h16so17258632ilj.11 for ; Tue, 21 Jul 2020 11:23:48 -0700 (PDT) X-Gm-Message-State: AOAM53076DGWEiizM2uFUD6v+tsnWOeXpdQzVOWC3e4tKMXdlgFyAfWD 9Ii5ea0F7RqFcv+4C6cNwL0Sz7w47/uckoz6urg= X-Google-Smtp-Source: ABdhPJydfYI053LQ9ZffMj6dfm+1wyhx/b1lBPMlq4P6IvKiNOEadMK0it3mzkYb4Au/iO40FDuf3uZp2fHoEtU+Ux4= X-Received: by 2002:a92:6a02:: with SMTP id f2mr26730266ilc.68.1595355827558; Tue, 21 Jul 2020 11:23:47 -0700 (PDT) MIME-Version: 1.0 References: <1595148523-22302-1-git-send-email-pranav.madhu@arm.com> <1595148523-22302-3-git-send-email-pranav.madhu@arm.com> In-Reply-To: <1595148523-22302-3-git-send-email-pranav.madhu@arm.com> From: "Thomas Abraham" Date: Tue, 21 Jul 2020 23:53:36 +0530 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [edk2-devel] [edk2-platforms][PATCH v4 2/5] Silicon/ARM/N1SoC: Implement Neoverse N1 Soc specific PciExpressLib To: devel@edk2.groups.io, pranav.madhu@arm.com Cc: Ard Biesheuvel , Leif Lindholm Content-Type: text/plain; charset="UTF-8" Hi Pranav, On Sun, Jul 19, 2020 at 2:19 PM Pranav Madhu wrote: > > From: Deepak Pandey > > A slave error is generated when host accesses the config space of > non-available device or unimplemented function on a given bus. So > implement a Neoverse N1 SoC specific PciExpressLib library with a > workaround to return 0xffffffff for all such access. > > This library is inherited from MdePkg/Library/BasePciExpressLib and > based on commit 9344f0921518 of that library in the tianocore/edk2 > project. > > In addition to this, the Neoverse N1 SoC has two other limitations which > affect the access to the PCIe root port: > 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is > isolated from rest of the downstream hierarchy ECAM space. > 2. Root port ECAM space is not capable of 8bit/16bit writes. > This library includes workaround for these limitations as well. > > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Signed-off-by: Pranav Madhu > --- > Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 4 + > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.inf | 56 + > Silicon/ARM/NeoverseN1Soc/Library/NeoverseN1SocPciExpressLib/PciExpressLib.c | 1589 ++++++++++++++++++++ > 3 files changed, 1649 insertions(+) > <...> > +UINT8 > +EFIAPI > +PciExpressWrite8 ( > + IN UINTN Address, > + IN UINT8 Value > + ) > +{ > + UINT8 Bus, Device, Function; > + UINT8 Offset; > + UINT32 Data; > + > + ASSERT_INVALID_PCI_ADDRESS (Address); > + > + Bus = GET_BUS_NUM (Address); > + Device = GET_DEV_NUM (Address); > + Function = GET_FUNC_NUM (Address); > + > + // > + // 8-bit and 16-bit writes to root port config space is not supported due to > + // a hardware limitation. As a workaround, perform a read-update-write > + // sequence on the whole 32-bit word of the root port config register such > + // that only the specified 8-bits of that word are updated. > + // > + if ((Bus == 0) && (Device == 0) && (Function == 0)) { > + Offset = Address & 0x3; > + Address &= 0xFFFFFFFC; > + Data = MmioRead32 ((UINTN)GetPciExpressAddress (Address)); nit: There should have been a space before the GetPciExpressAddress. This is inconsistent with the rest of the file. Thanks, Thomas. <...>