From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-il1-f196.google.com (mail-il1-f196.google.com [209.85.166.196]) by mx.groups.io with SMTP id smtpd.web10.10718.1598496993152253439 for ; Wed, 26 Aug 2020 19:56:33 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=Qm1UMlD2; spf=pass (domain: linaro.org, ip: 209.85.166.196, mailfrom: tanmay.jagdale@linaro.org) Received: by mail-il1-f196.google.com with SMTP id j9so3654790ilc.11 for ; Wed, 26 Aug 2020 19:56:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ha4snkbs0A40Bp9MteFsjaKfxZZBHilTrFHgiXcbNDk=; b=Qm1UMlD2fKjRkM7JaoilpXB9rNxvAAWUSTTYkyUkuoxUaJURrYzZpCWDjI8TE99mty oKZWk95DxsoowAYWO1Gj5wB4/UyRUwCmjm6KdbSLzVbpWF5RXLi0mkBmkeGGPaqb8tKC wy3UzrPwvfN3sxaLLUp3bX+XAvNX4TKKxDA8mLE/iO/tkZlivX+3VyK/yPbeUuxPxjhQ ziNw5K3vtdLYhWb24yBYBepVb90+ZPqcMCg+o0CJVLgzreUg//rbITpSzrzimTe2OaCG soKkRE3s7JFiernRd6qPz9sphsT/svJoL82TWF3boWotrAK0t2jMBCxSz4x8D32929Y0 Zw5Q== X-Google-DKIM-Signature: v=1; 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boundary="00000000000068affd05add31522" --00000000000068affd05add31522 Content-Type: text/plain; charset="UTF-8" Hi Graeme, On Thu, 27 Aug 2020 at 04:18, Graeme Gregory wrote: > On Wed, Aug 26, 2020 at 04:35:22PM +0100, Graeme Gregory wrote: > > On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote: > > > - Add support to create MADT table at runtime. > > > - Included a macro for GIC Redistributor structure initialisation. > > > > > > Signed-off-by: Tanmay Jagdale > > > --- > > > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | > 20 ++- > > > Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | > 15 ++ > > > Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | > 156 ++++++++++++++++++++ > > > 3 files changed, 190 insertions(+), 1 deletion(-) > > > > > > diff --git > a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > > > index 3795a7e11639..8125e8ba7553 100644 > > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > > > @@ -41,9 +41,27 @@ [LibraryClasses] > > > UefiRuntimeServicesTableLib > > > > > > [Pcd] > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile > > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount > > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCount > > > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress > > > > > > [Depex] > > > - TRUE > > > + gEfiAcpiTableProtocolGuid ## CONSUMES > > > + > > > +[Guids] > > > + gEdkiiPlatformHasAcpiGuid > > > + > > > +[Protocols] > > > + gEfiAcpiTableProtocolGuid ## CONSUMES > > > + > > > +[FixedPcd] > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision > > > + gArmTokenSpaceGuid.PcdGicDistributorBase > > > + gArmTokenSpaceGuid.PcdGicRedistributorsBase > > > + > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId > > > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision > > > diff --git > a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > > > index eac195b0585c..7a9a0061675f 100644 > > > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > > > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > > > @@ -22,6 +22,21 @@ > > > FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 > CreatorRevision */ \ > > > } > > > > > > +// Defines for MADT > > > +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000 > > > +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000 > > > +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23 > > > +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000 > > > + > > > +// Macro for MADT GIC Redistributor Structure > > > +#define SBSAQEMU_MADT_GICR_INIT() { > \ > > > + EFI_ACPI_6_0_GICR, /* Type */ > \ > > > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ > \ > > > + EFI_ACPI_RESERVED_WORD, /* Reserved */ > \ > > > + FixedPcdGet32 (PcdGicRedistributorsBase), /* > DiscoveryRangeBaseAddress */ \ > > > + SBSAQEMU_MADT_GICR_SIZE /* DiscoveryRangeLength > */ \ > > > + } > > > + > > > #define SBSAQEMU_UART0_BASE 0x60000000 > > > > > > #define SBSAQEMU_PCI_SEG0_CONFIG_BASE 0xf0000000 > > > diff --git > a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > > > index 75abdae3b8ce..16cb4e904e6f 100644 > > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > > > @@ -6,11 +6,17 @@ > > > * SPDX-License-Identifier: BSD-2-Clause-Patent > > > * > > > **/ > > > +#include > > > +#include > > > +#include > > > +#include > > > #include > > > +#include > > > #include > > > #include > > > #include > > > #include > > > +#include > > > #include > > > #include > > > > > > @@ -61,6 +67,137 @@ CountCpusFromFdt ( > > > ASSERT_RETURN_ERROR (PcdStatus); > > > } > > > > > > +/* > > > + * A Function to Compute the ACPI Table Checksum > > > + */ > > > +VOID > > > +AcpiPlatformChecksum ( > > > + IN UINT8 *Buffer, > > > + IN UINTN Size > > > + ) > > > +{ > > > + UINTN ChecksumOffset; > > > + > > > + ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); > > > + > > > + // Set checksum field to 0 since it is used as part of the > calculation > > > + Buffer[ChecksumOffset] = 0; > > > + > > > + Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size); > > > +} > > > + > > > +/* > > > + * A function that add the MADT ACPI table. > > > + IN EFI_ACPI_COMMON_HEADER *CurrentTable > > > + */ > > > +EFI_STATUS > > > +AddMadtTable ( > > > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > > > + ) > > > +{ > > > + EFI_STATUS Status; > > > + UINTN TableHandle; > > > + UINT32 TableSize; > > > + EFI_PHYSICAL_ADDRESS PageAddress; > > > + UINT8 *New; > > > + UINT32 NumCores; > > > + > > > + // Initialize MADT ACPI Header > > > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = { > > > + SBSAQEMU_ACPI_HEADER > (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, > > > + > EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER, > > > + > EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), > > > + 0, 0 }; > > > + > > > + // Initialize GICC Structure > > > + EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT ( > > > + 0, /* GicID */ > > > + 0, /* AcpiCpuUid */ > > > + 0, /* Mpidr */ > > > + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */ > > > + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */ > > > + FixedPcdGet32 (PcdGicDistributorBase), /* PhysicalBaseAddress */ > > > + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */ > > > + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */ > > > + 25, /* GsivId */ > > > + 0, /* GicRBase */ > > > + 0 /* Efficiency */ > > > + ); > > > + > > > + // Initialize GIC Distributor Structure > > > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd = > > > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT ( > > > + 0, > > > + FixedPcdGet32 (PcdGicDistributorBase), > > > + 0, > > > + 3 /* GicVersion */ > > > + ); > > > + > > > + // Initialize GIC Redistributor Structure > > > + EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT(); > > > + > > > + // Get CoreCount which was determined eariler after parsing device > tree > > > + NumCores = PcdGet32 (PcdCoreCount); > > > + > > > + // Calculate the new table size based on the number of cores > > > + TableSize = sizeof > (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) + > > > + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + > > > + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + > > > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); > > > + > > > + Status = gBS->AllocatePages ( > > > + AllocateAnyPages, > > > + EfiACPIReclaimMemory, > > > + EFI_SIZE_TO_PAGES (TableSize), > > > + &PageAddress > > > + ); > > > + if (EFI_ERROR(Status)) { > > > + DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MADT > table\n")); > > > + return EFI_OUT_OF_RESOURCES; > > > + } > > > + > > > + New = (UINT8 *)(UINTN) PageAddress; > > > + ZeroMem (New, TableSize); > > > + > > > + // Add the ACPI Description table header > > > + CopyMem (New, &Header, sizeof > (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER)); > > > + ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize; > > > + New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); > > > + > > > + // Add new GICC structures for the Cores > > > + for (NumCores = 0; NumCores < PcdGet32 (PcdCoreCount); NumCores++) { > > > + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; > > > + > > > + CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); > > > + GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New; > > > + GiccPtr->AcpiProcessorUid = NumCores; > > > + GiccPtr->MPIDR = NumCores; > > > > This does not seem to be quite correct, if I dump the MPIDRs from ARM-TF > when > > booting with 12 cpus this is what I get. > > > > NOTICE: MPIDR 0 > > NOTICE: MPIDR 1 > > NOTICE: MPIDR 2 > > NOTICE: MPIDR 3 > > NOTICE: MPIDR 4 > > NOTICE: MPIDR 5 > > NOTICE: MPIDR 6 > > NOTICE: MPIDR 7 > > NOTICE: MPIDR 100 > > NOTICE: MPIDR 101 > > NOTICE: MPIDR 102 > > NOTICE: MPIDR 103 > > > > I think this will make PSCI operations from CPU8 onwards fail. > > > > I can confirm this is wrong > > I did a quick hack > > GiccPtr->MPIDR = ((NumCores / 8) << 8) | (NumCores % 8); > > Thanks for the fix. > and I can boot 128 cores (MPIDR also needs fixed in SSDT I think) > > [ 12.637579] GICv3: CPU127: found redistributor f07 region > 0:0x0000000041060000 > [ 12.640185] CPU127: Booted secondary processor 0x0000000f07 > [0x411fd070] > [ 12.676961] smp: Brought up 1 node, 128 CPUs > > Considering this patch is in the works > > https://lists.gnu.org/archive/html/qemu-devel/2020-08/msg06223.html > > which add MPIDR to the DT, i think you will when that is accepted be > able to use the MPIDR from there and then you are protected for the > CPU topology changing. > > So shall I push an interim patch that uses the aforementioned formula to derive the MPIDR ? Or wait for the qemu patch to get merged and then read MPIDR directly from there ? Thanks, Tanmay Thanks > > Graeme > > > > Thanks > > > > Graeme > > > > > > > + New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); > > > + } > > > + > > > + // GIC Distributor Structure > > > + CopyMem (New, &Gicd, sizeof > (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE)); > > > + New += sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE); > > > + > > > + // GIC ReDistributor Structure > > > + CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCTURE)); > > > + New += sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); > > > + > > > + AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > > > + > > > + Status = AcpiTable->InstallAcpiTable ( > > > + AcpiTable, > > > + (EFI_ACPI_COMMON_HEADER *)PageAddress, > > > + TableSize, > > > + &TableHandle > > > + ); > > > + if (EFI_ERROR(Status)) { > > > + DEBUG ((DEBUG_ERROR, "Failed to install MADT table\n")); > > > + } > > > + > > > + return Status; > > > +} > > > + > > > EFI_STATUS > > > EFIAPI > > > InitializeSbsaQemuAcpiDxe ( > > > @@ -68,8 +205,27 @@ InitializeSbsaQemuAcpiDxe ( > > > IN EFI_SYSTEM_TABLE *SystemTable > > > ) > > > { > > > + EFI_STATUS Status; > > > + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; > > > + > > > // Parse the device tree and get the number of CPUs > > > CountCpusFromFdt (); > > > > > > + // Check if ACPI Table Protocol has been installed > > > + Status = gBS->LocateProtocol ( > > > + &gEfiAcpiTableProtocolGuid, > > > + NULL, > > > + (VOID **)&AcpiTable > > > + ); > > > + if (EFI_ERROR (Status)) { > > > + DEBUG ((DEBUG_ERROR, "Failed to locate ACPI Table Protocol\n")); > > > + return Status; > > > + } > > > + > > > + Status = AddMadtTable (AcpiTable); > > > + if (EFI_ERROR(Status)) { > > > + DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n")); > > > + } > > > + > > > return EFI_SUCCESS; > > > } > > > -- > > > 2.28.0 > > > > --00000000000068affd05add31522 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Graeme,


On Thu, 27 Aug 2020 at 04:18, Graeme Gregor= y <graeme@nuviainc.com> wr= ote:
On Wed, Aug= 26, 2020 at 04:35:22PM +0100, Graeme Gregory wrote:
> On Tue, Aug 25, 2020 at 07:09:55PM +0530, Tanmay Jagdale wrote:
> > - Add support to create MADT table at runtime.
> > - Included a macro for GIC Redistributor structure initialisation= .
> >
> > Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
> > ---
> >=C2=A0 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiD= xe.inf |=C2=A0 20 ++-
> >=C2=A0 Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi= .h=C2=A0 =C2=A0 =C2=A0|=C2=A0 15 ++
> >=C2=A0 Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiD= xe.c=C2=A0 =C2=A0| 156 ++++++++++++++++++++
> >=C2=A0 3 files changed, 190 insertions(+), 1 deletion(-)
> >
> > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQe= muAcpiDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiD= xe.inf
> > index 3795a7e11639..8125e8ba7553 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiD= xe.inf
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiD= xe.inf
> > @@ -41,9 +41,27 @@ [LibraryClasses]
> >=C2=A0 =C2=A0 UefiRuntimeServicesTableLib
> >=C2=A0
> >=C2=A0 [Pcd]
> > +=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile > >=C2=A0 =C2=A0 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount<= br> > >=C2=A0 =C2=A0 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdClusterCou= nt
> >=C2=A0 =C2=A0 gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTree= BaseAddress
> >=C2=A0
> >=C2=A0 [Depex]
> > -=C2=A0 TRUE
> > +=C2=A0 gEfiAcpiTableProtocolGuid=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
> > +
> > +[Guids]
> > +=C2=A0 gEdkiiPlatformHasAcpiGuid
> > +
> > +[Protocols]
> > +=C2=A0 gEfiAcpiTableProtocolGuid=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
> > +
> > +[FixedPcd]
> > +=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision<= br> > > +=C2=A0 gArmTokenSpaceGuid.PcdGicDistributorBase
> > +=C2=A0 gArmTokenSpaceGuid.PcdGicRedistributorsBase
> > +
> > +=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId > > +=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevis= ion
> > +=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
> > +=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId > > +=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision<= br> > > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQ= emuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > > index eac195b0585c..7a9a0061675f 100644
> > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi= .h
> > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi= .h
> > @@ -22,6 +22,21 @@
> >=C2=A0 =C2=A0 =C2=A0 FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)= /* UINT32=C2=A0 CreatorRevision */ \
> >=C2=A0 =C2=A0 }
> >=C2=A0
> > +// Defines for MADT
> > +#define SBSAQEMU_MADT_GIC_VBASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 0x2c020000
> > +#define SBSAQEMU_MADT_GIC_HBASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 0x2c010000
> > +#define SBSAQEMU_MADT_GIC_PMU_IRQ=C2=A0 =C2=A0 =C2=A0 =C2=A0 23<= br> > > +#define SBSAQEMU_MADT_GICR_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 0x4000000
> > +
> > +// Macro for MADT GIC Redistributor Structure
> > +#define SBSAQEMU_MADT_GICR_INIT() {=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> > +=C2=A0 =C2=A0EFI_ACPI_6_0_GICR,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Type */=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \=
> > +=C2=A0 =C2=A0sizeof (EFI_ACPI_6_0_GICR_STRUCTURE),=C2=A0 =C2=A0 = =C2=A0/* Length */=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 \
> > +=C2=A0 =C2=A0EFI_ACPI_RESERVED_WORD,=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Reserved */=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> > +=C2=A0 =C2=A0FixedPcdGet32 (PcdGicRedistributorsBase), /* Discov= eryRangeBaseAddress */=C2=A0 =C2=A0\
> > +=C2=A0 =C2=A0SBSAQEMU_MADT_GICR_SIZE=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* DiscoveryRangeLength */=C2=A0 = =C2=A0 =C2=A0 =C2=A0 \
> > +=C2=A0 =C2=A0}
> > +
> >=C2=A0 #define SBSAQEMU_UART0_BASE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 0x60000000
> >=C2=A0
> >=C2=A0 #define SBSAQEMU_PCI_SEG0_CONFIG_BASE=C2=A0 =C2=A0 0xf00000= 00
> > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQe= muAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe= .c
> > index 75abdae3b8ce..16cb4e904e6f 100644
> > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiD= xe.c
> > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiD= xe.c
> > @@ -6,11 +6,17 @@
> >=C2=A0 *=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
> >=C2=A0 *
> >=C2=A0 **/
> > +#include <IndustryStandard/Acpi.h>
> > +#include <IndustryStandard/SbsaQemuAcpi.h>
> > +#include <Library/AcpiLib.h>
> > +#include <Library/BaseMemoryLib.h>
> >=C2=A0 #include <Library/DebugLib.h>
> > +#include <Library/MemoryAllocationLib.h>
> >=C2=A0 #include <Library/PcdLib.h>
> >=C2=A0 #include <Library/UefiBootServicesTableLib.h>
> >=C2=A0 #include <Library/UefiDriverEntryPoint.h>
> >=C2=A0 #include <Library/UefiLib.h>
> > +#include <Protocol/AcpiTable.h>
> >=C2=A0 #include <Protocol/FdtClient.h>
> >=C2=A0 #include <libfdt.h>
> >=C2=A0
> > @@ -61,6 +67,137 @@ CountCpusFromFdt (
> >=C2=A0 =C2=A0 ASSERT_RETURN_ERROR (PcdStatus);
> >=C2=A0 }
> >=C2=A0
> > +/*
> > + * A Function to Compute the ACPI Table Checksum
> > + */
> > +VOID
> > +AcpiPlatformChecksum (
> > +=C2=A0 IN UINT8=C2=A0 =C2=A0 =C2=A0 *Buffer,
> > +=C2=A0 IN UINTN=C2=A0 =C2=A0 =C2=A0 Size
> > +=C2=A0 )
> > +{
> > +=C2=A0 UINTN ChecksumOffset;
> > +
> > +=C2=A0 ChecksumOffset =3D OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER= , Checksum);
> > +
> > +=C2=A0 // Set checksum field to 0 since it is used as part of th= e calculation
> > +=C2=A0 Buffer[ChecksumOffset] =3D 0;
> > +
> > +=C2=A0 Buffer[ChecksumOffset] =3D CalculateCheckSum8(Buffer, Siz= e);
> > +}
> > +
> > +/*
> > + * A function that add the MADT ACPI table.
> > +=C2=A0 IN EFI_ACPI_COMMON_HEADER=C2=A0 =C2=A0 *CurrentTable
> > + */
> > +EFI_STATUS
> > +AddMadtTable (
> > +=C2=A0 IN EFI_ACPI_TABLE_PROTOCOL=C2=A0 =C2=A0*AcpiTable
> > +=C2=A0 )
> > +{
> > +=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Statu= s;
> > +=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0TableHandle;
> > +=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 TableSize;
> > +=C2=A0 EFI_PHYSICAL_ADDRESS=C2=A0 PageAddress;
> > +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0*New;
> > +=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 NumCores;
> > +
> > +=C2=A0 // Initialize MADT ACPI Header
> > +=C2=A0 EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Heade= r =3D {
> > +=C2=A0 =C2=A0 =C2=A0SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_= APIC_DESCRIPTION_TABLE_SIGNATURE,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TA= BLE_HEADER,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TA= BLE_REVISION),
> > +=C2=A0 =C2=A0 =C2=A0 0, 0 };
> > +
> > +=C2=A0 // Initialize GICC Structure
> > +=C2=A0 EFI_ACPI_6_0_GIC_STRUCTURE Gicc =3D EFI_ACPI_6_0_GICC_STR= UCTURE_INIT (
> > +=C2=A0 =C2=A0 0,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0/* GicID */
> > +=C2=A0 =C2=A0 0,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0/* AcpiCpuUid */
> > +=C2=A0 =C2=A0 0,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0/* Mpidr */
> > +=C2=A0 =C2=A0 EFI_ACPI_6_0_GIC_ENABLED,=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 /* Flags */
> > +=C2=A0 =C2=A0 SBSAQEMU_MADT_GIC_PMU_IRQ,=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0/* PMU Irq */
> > +=C2=A0 =C2=A0 FixedPcdGet32 (PcdGicDistributorBase), /* Physical= BaseAddress */
> > +=C2=A0 =C2=A0 SBSAQEMU_MADT_GIC_VBASE,=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* GicVBase */
> > +=C2=A0 =C2=A0 SBSAQEMU_MADT_GIC_HBASE,=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* GicHBase */
> > +=C2=A0 =C2=A0 25,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 /* GsivId */
> > +=C2=A0 =C2=A0 0,=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0/* GicRBase */
> > +=C2=A0 =C2=A0 0=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 /* Efficiency */
> > +=C2=A0 =C2=A0 );
> > +
> > +=C2=A0 // Initialize GIC Distributor Structure
> > +=C2=A0 EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd =3D
> > +=C2=A0 =C2=A0 EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT (
> > +=C2=A0 =C2=A0 =C2=A0 0,
> > +=C2=A0 =C2=A0 =C2=A0 FixedPcdGet32 (PcdGicDistributorBase),
> > +=C2=A0 =C2=A0 =C2=A0 0,
> > +=C2=A0 =C2=A0 =C2=A0 3 /* GicVersion */
> > +=C2=A0 =C2=A0 );
> > +
> > + // Initialize GIC Redistributor Structure
> > +=C2=A0 EFI_ACPI_6_0_GICR_STRUCTURE Gicr =3D SBSAQEMU_MADT_GICR_I= NIT();
> > +
> > +=C2=A0 // Get CoreCount which was determined eariler after parsi= ng device tree
> > +=C2=A0 NumCores =3D PcdGet32 (PcdCoreCount);
> > +
> > +=C2=A0 // Calculate the new table size based on the number of co= res
> > +=C2=A0 TableSize =3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPT= ION_TABLE_HEADER) +
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(sizeof (= EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) +
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sizeof (E= FI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) +
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sizeof (E= FI_ACPI_6_0_GICR_STRUCTURE);
> > +
> > +=C2=A0 Status =3D gBS->AllocatePages (
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 A= llocateAnyPages,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 E= fiACPIReclaimMemory,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 E= FI_SIZE_TO_PAGES (TableSize),
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &= amp;PageAddress
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 )= ;
> > +=C2=A0 if (EFI_ERROR(Status)) {
> > +=C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "Failed to allocate page= s for MADT table\n"));
> > +=C2=A0 =C2=A0 return EFI_OUT_OF_RESOURCES;
> > +=C2=A0 }
> > +
> > +=C2=A0 New =3D (UINT8 *)(UINTN) PageAddress;
> > +=C2=A0 ZeroMem (New, TableSize);
> > +
> > +=C2=A0 // Add the=C2=A0 ACPI Description table header
> > +=C2=A0 CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_= APIC_DESCRIPTION_TABLE_HEADER));
> > +=C2=A0 ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length =3D Table= Size;
> > +=C2=A0 New +=3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_T= ABLE_HEADER);
> > +
> > +=C2=A0 // Add new GICC structures for the Cores
> > +=C2=A0 for (NumCores =3D 0; NumCores < PcdGet32 (PcdCoreCount= ); NumCores++) {
> > +=C2=A0 =C2=A0 EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr;
> > +
> > +=C2=A0 =C2=A0 CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_= STRUCTURE));
> > +=C2=A0 =C2=A0 GiccPtr =3D (EFI_ACPI_6_0_GIC_STRUCTURE *) New; > > +=C2=A0 =C2=A0 GiccPtr->AcpiProcessorUid =3D NumCores;
> > +=C2=A0 =C2=A0 GiccPtr->MPIDR =3D NumCores;
>
> This does not seem to be quite correct, if I dump the MPIDRs from ARM-= TF when
> booting with 12 cpus this is what I get.
>
> NOTICE:=C2=A0 MPIDR 0
> NOTICE:=C2=A0 MPIDR 1
> NOTICE:=C2=A0 MPIDR 2
> NOTICE:=C2=A0 MPIDR 3
> NOTICE:=C2=A0 MPIDR 4
> NOTICE:=C2=A0 MPIDR 5
> NOTICE:=C2=A0 MPIDR 6
> NOTICE:=C2=A0 MPIDR 7
> NOTICE:=C2=A0 MPIDR 100
> NOTICE:=C2=A0 MPIDR 101
> NOTICE:=C2=A0 MPIDR 102
> NOTICE:=C2=A0 MPIDR 103
>
> I think this will make PSCI operations from CPU8 onwards fail.
>

I can confirm this is wrong

I did a quick hack

GiccPtr->MPIDR =3D ((NumCores / 8) << 8) | (NumCores % 8);

Thanks for the fix.
=C2=A0
and I can boot 128 cores (MPIDR also needs fixed in SSDT I think)

[=C2=A0 =C2=A012.637579] GICv3: CPU127: found redistributor f07 region
0:0x0000000041060000
[=C2=A0 =C2=A012.640185] CPU127: Booted secondary processor 0x0000000f07 [0x411fd070]
[=C2=A0 =C2=A012.676961] smp: Brought up 1 node, 128 CPUs

Considering this patch is in the works

https://lists.gnu.org/archive/htm= l/qemu-devel/2020-08/msg06223.html

which add MPIDR to the DT, i think you will when that is accepted be
able to use the MPIDR from there and then you are protected for the
CPU topology changing.

So shall I push an interim patch that uses the aforementioned form= ula
to derive the MPIDR ? Or wait for the qemu patch to get merged and<= /span>
then read MPIDR directly from there ?

Thanks,
=
Tanmay

Thanks

Graeme


> Thanks
>
> Graeme
>
>
> > +=C2=A0 =C2=A0 New +=3D sizeof (EFI_ACPI_6_0_GIC_STRUCTURE);
> > +=C2=A0 }
> > +
> > +=C2=A0 // GIC Distributor Structure
> > +=C2=A0 CopyMem (New, &Gicd, sizeof (EFI_ACPI_6_0_GIC_DISTRIB= UTOR_STRUCTURE));
> > +=C2=A0 New +=3D sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE);=
> > +
> > +=C2=A0 // GIC ReDistributor Structure
> > +=C2=A0 CopyMem (New, &Gicr, sizeof (EFI_ACPI_6_0_GICR_STRUCT= URE));
> > +=C2=A0 New +=3D sizeof (EFI_ACPI_6_0_GICR_STRUCTURE);
> > +
> > +=C2=A0 AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > > +
> > +=C2=A0 Status =3D AcpiTable->InstallAcpiTable (
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 AcpiTable,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 (EFI_ACPI_COMMON_HEADER *)PageAddress,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 TableSize,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 &TableHandle
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 );
> > +=C2=A0 if (EFI_ERROR(Status)) {
> > +=C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "Failed to install MADT = table\n"));
> > +=C2=A0 }
> > +
> > +=C2=A0 return Status;
> > +}
> > +
> >=C2=A0 EFI_STATUS
> >=C2=A0 EFIAPI
> >=C2=A0 InitializeSbsaQemuAcpiDxe (
> > @@ -68,8 +205,27 @@ InitializeSbsaQemuAcpiDxe (
> >=C2=A0 =C2=A0 IN EFI_SYSTEM_TABLE=C2=A0 =C2=A0 =C2=A0*SystemTable<= br> > >=C2=A0 =C2=A0 )
> >=C2=A0 {
> > +=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Status;
> > +=C2=A0 EFI_ACPI_TABLE_PROTOCOL=C2=A0 =C2=A0 =C2=A0 =C2=A0 *AcpiT= able;
> > +
> >=C2=A0 =C2=A0 // Parse the device tree and get the number of CPUs<= br> > >=C2=A0 =C2=A0 CountCpusFromFdt ();
> >=C2=A0
> > +=C2=A0 // Check if ACPI Table Protocol has been installed
> > +=C2=A0 Status =3D gBS->LocateProtocol (
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &= amp;gEfiAcpiTableProtocolGuid,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 N= ULL,
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (= VOID **)&AcpiTable
> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 )= ;
> > +=C2=A0 if (EFI_ERROR (Status)) {
> > +=C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "Failed to locate ACPI T= able Protocol\n"));
> > +=C2=A0 =C2=A0 return Status;
> > +=C2=A0 }
> > +
> > +=C2=A0 Status =3D AddMadtTable (AcpiTable);
> > +=C2=A0 if (EFI_ERROR(Status)) {
> > +=C2=A0 =C2=A0 =C2=A0DEBUG ((DEBUG_ERROR, "Failed to add MAD= T table\n"));
> > +=C2=A0 }
> > +
> >=C2=A0 =C2=A0 return EFI_SUCCESS;
> >=C2=A0 }
> > --
> > 2.28.0
> >
--00000000000068affd05add31522--