From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web11.7345.1680872732268699709 for ; Fri, 07 Apr 2023 06:05:32 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=fIuhV7Av; spf=pass (domain: gmail.com, ip: 209.85.214.170, mailfrom: pedro.falcato@gmail.com) Received: by mail-pl1-f170.google.com with SMTP id o2so39954687plg.4 for ; Fri, 07 Apr 2023 06:05:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1680872731; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=LjO/gTjzrjXu35uS//3aGFZ/esID+VqC0J5iolu2uxQ=; b=fIuhV7Av1YnU3ZaWfB5hvXVnVfhE1E1iqv7mt8nYCYmYmOV8Lag8kt3lpVDli3e2RE fM15IjDG29BzR+x0LPTGLz66iBf9UqTpTsBRvYSOzOOiJVvS8mhBXvujA7TM2gRoCKYn hcrxDZzk00JFT3tJN3UfKhGXQGGBQ5WQcdVVHqR9klAyGWologOUqvPIHIaSwWB8rxfp 3aRnvUPGHghzeWbOwNGbAi/aDzr0UAoX2nc+mY3x6RbphNObKqfC232IVoCksvJMiabI qS80kXLVvR5xbB/YNocZ7ZHlCAJRt+MxIIQS6GBSQFEjsJwrbKXsQbF26RHcoMTUDGJj M0Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680872731; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LjO/gTjzrjXu35uS//3aGFZ/esID+VqC0J5iolu2uxQ=; b=VJ6oWQT5I49XS4pXrsUNWV8EJb2jNTN+nPOA+RS3VyeSBbfkhe6BBLsiXBqTOPaHj0 8T8sPdIxchETFy5B7bV5dFiH7Bt2mtB+ZYRjTEOlTVAiobZOTFBfqmryUt3Km6tCe5jI jxOEM50Ler2rNFpzHVxEpyfnJauL9XWcchLk6/7gdr2EMKgJsrBeByUAwnR9xvF6hKVa rA6+46be7VHDMnCVSInBNo+Rfmj7ozODy3qgMdICQWJHiLXlELEMcYBMq6Kr/IXst75Y PtDqaSKknoS9/hE7ZLdxIVsLsIm1mm0lyVElL1OtFzlo54vKHeO1/1f4ck4QZBfH51Ff Ovtw== X-Gm-Message-State: AAQBX9dmLpoSXK5RfHEbvBg47MR0WkFT7nzYzmebPE7hkbIMnNLOfnUz d2uClHVhlU/ek6d9WJNUDyz8zFkQLkThVflXW+fIkraB X-Google-Smtp-Source: AKy350aJAKV+rL1JDWNoUq/VXW4hD4Bc5JDV9qVYGXe2D3XpFwxykX3BBwE10fV043/n6Dgv2d/fQd/7qgAAw3Z9caQ= X-Received: by 2002:a17:90a:a004:b0:23d:3b06:ee13 with SMTP id q4-20020a17090aa00400b0023d3b06ee13mr635921pjp.1.1680872730819; Fri, 07 Apr 2023 06:05:30 -0700 (PDT) MIME-Version: 1.0 References: <20230407124731.121236-1-marcin.juszkiewicz@linaro.org> In-Reply-To: From: "Pedro Falcato" Date: Fri, 7 Apr 2023 14:05:19 +0100 Message-ID: Subject: Re: [edk2-devel] [PATCH v3] add ArmCpuInfo EFI application To: devel@edk2.groups.io, marcin.juszkiewicz@linaro.org Cc: Ard Biesheuvel , Leif Lindholm , Rebecca Cran Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Forgot mentioning: STATIC vs static, CONST vs const, VOID vs void, CHAR8 vs char, etc. All fun microsoftisms you need to use here. On Fri, Apr 7, 2023 at 2:02=E2=80=AFPM Pedro Falcato wrote: > > On Fri, Apr 7, 2023 at 1:47=E2=80=AFPM Marcin Juszkiewicz > wrote: > > > > App goes through ID_AA64*_EL1 system registers and decode their values. > > > > Signed-off-by: Marcin Juszkiewicz > > --- > > ArmPkg/ArmPkg.dsc | 1 + > > ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 38 + > > ArmPkg/Application/ArmCpuInfo/readargs.h | 12 + > > ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2317 ++++++++++++++++++= ++ > > ArmPkg/Application/ArmCpuInfo/readregs.s | 49 + > > 5 files changed, 2417 insertions(+) > > > > diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc > > index 3fb95d1951a9..6b938ce8b671 100644 > > --- a/ArmPkg/ArmPkg.dsc > > +++ b/ArmPkg/ArmPkg.dsc > > @@ -166,6 +166,7 @@ [Components.AARCH64] > > ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf > > ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf > > ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf > > + ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf > > > > [Components.AARCH64, Components.ARM] > > ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf > > diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf b/ArmPkg/Appl= ication/ArmCpuInfo/ArmCpuInfo.inf > > new file mode 100644 > > index 000000000000..158f86a4740c > > --- /dev/null > > +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf > > @@ -0,0 +1,38 @@ > > +## @file > > +# > > +# Attempt to have AArch64 cpu information. > > +# > > +# Based on HelloWorld: > > +# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved. > > +# Copyright (c) 2023 Marcin Juszkiewicz > > +# > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > +# > > +# > > +## > > + > > +[Defines] > > + INF_VERSION =3D 0x00010019 > > + BASE_NAME =3D ArmCpuInfo > > + FILE_GUID =3D b3134491-6502-4faf-a9da-007184e32= 163 > > + MODULE_TYPE =3D UEFI_APPLICATION > > + VERSION_STRING =3D 1.0 > > + ENTRY_POINT =3D UefiMain > > + > > +# > > +# This flag specifies whether HII resource section is generated into = PE image. > > +# > > + UEFI_HII_RESOURCE_SECTION =3D TRUE > > + > > +[Sources] > > + ArmCpuInfo.c > > + readregs.s > > + > > +[Packages] > > + ArmPkg/ArmPkg.dec > > + MdePkg/MdePkg.dec > > + MdeModulePkg/MdeModulePkg.dec > > + > > +[LibraryClasses] > > + UefiApplicationEntryPoint > > + UefiLib > > diff --git a/ArmPkg/Application/ArmCpuInfo/readargs.h b/ArmPkg/Applicat= ion/ArmCpuInfo/readargs.h > > new file mode 100644 > > index 000000000000..eaa52cf16145 > > --- /dev/null > > +++ b/ArmPkg/Application/ArmCpuInfo/readargs.h > > @@ -0,0 +1,12 @@ > > +UINT64 read_aa64pfr0_el1(void); > > +UINT64 read_aa64pfr1_el1(void); > > +UINT64 read_aa64dfr0_el1(void); > > +UINT64 read_aa64dfr1_el1(void); > > +UINT64 read_aa64isar0_el1(void); > > +UINT64 read_aa64isar1_el1(void); > > +UINT64 read_aa64isar2_el1(void); > > +UINT64 read_aa64mmfr0_el1(void); > > +UINT64 read_aa64mmfr1_el1(void); > > +UINT64 read_aa64mmfr2_el1(void); > > +UINT64 read_aa64smfr0_el1(void); > > +UINT64 read_aa64zfr0_el1(void); > > diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c b/ArmPkg/Applic= ation/ArmCpuInfo/ArmCpuInfo.c > > new file mode 100644 > > index 000000000000..6c31ad4dbcb9 > > --- /dev/null > > +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c > > @@ -0,0 +1,2317 @@ > > +/** @file > > + > > + Copyright (c) 2023 Marcin Juszkiewicz > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > + **/ > > + > > +#include > > +#include "readargs.h" > > + > > +void > > +print_text ( > > + const char *field, > > + const char *bits, > > + const char *value, > > + const char *description > > + ) > > +{ > > + AsciiPrint (" %-16a | %5a | %5a | %a\n", field, bits, value, descrip= tion); > > +} > > + > > +void > > +print_values ( > > + const char *field, > > + const char *bits, > > + const int value, > > + const char *description > > + ) > > +{ > > + STATIC CONST CHAR8 binaries[][5] =3D { > > + "0000", "0001", "0010", "0011", > > + "0100", "0101", "0110", "0111","1000", "1001", "1010", "1011", > > + "1100", "1101", "1110", "1111" > > + }; > > + > > + AsciiPrint (" %-16a | %5a | %5a | %a\n", field, bits, binaries[value= & 0xf], description); > > +} > > + > > +void > > +print_spacer ( > > + void > > + ) > > +{ > > + AsciiPrint ("------------------|-------|-------|--------------------= --------------------------\n"); > > +} > > + > > +void > > +handle_aa64mmfr0_el1 ( > > + const UINT64 aa64mmfr0_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR0_EL1"; > > + char *description; > > + char *bits; > > + > > + bits =3D "3:0 "; > > + value =3D aa64mmfr0_el1 & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "32 bits (4GB) of physical address range suppor= ted."; > > + break; > > + case 0b0001: > > + description =3D "36 bits (64GB) of physical address range suppo= rted."; > > + break; > > + case 0b0010: > > + description =3D "40 bits (1TB) of physical address range suppor= ted."; > > + break; > > + case 0b0011: > > + description =3D "42 bits (4TB) of physical address range suppor= ted."; > > + break; > > + case 0b0100: > > + description =3D "44 bits (16TB) of physical address range suppo= rted."; > > + break; > > + case 0b0101: > > + description =3D "48 bits (256TB) of physical address range supp= orted."; > > + break; > > + case 0b0110: > > + description =3D "52 bits (4PB) of physical address range suppor= ted."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + if (value =3D=3D 0b0110) { > > + print_text ("", "", "", "FEAT_LPA implemented."); > > + } > > + > > + bits =3D "7:4 "; > > + value =3D (aa64mmfr0_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "ASID: 8 bits"; > > + break; > > + case 0b0010: > > + description =3D "ASID: 16 bits"; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "11:8 "; > > + value =3D (aa64mmfr0_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "No mixed-endian support."; > > + break; > > + case 0b0001: > > + description =3D "Mixed-endian support."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // only valid for BigEnd !=3D 0b0000 > > + if (((aa64mmfr0_el1 >> 8) & 0xf) !=3D 0b0000 ) { > > + if (((aa64mmfr0_el1 >> 16) & 0xf) =3D=3D 0b0000 ) { > > + print_values ("ID_AA64MMFR0_EL1", "19:16", 0b0000, "No mixed-end= ian support at EL0."); > > + } > > + > > + if (((aa64mmfr0_el1 >> 16) & 0xf) =3D=3D 0b0001 ) { > > + print_values ("ID_AA64MMFR0_EL1", "19:16", 0b0001, "Mixed-endian= support at EL0."); > > + } > > + } > > + > > + bits =3D "15:12"; > > + value =3D (aa64mmfr0_el1 >> 12) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "No support for a distinction between Secure and= Non-Secure Memory."; > > + break; > > + case 0b0001: > > + description =3D "Supports a distinction between Secure and Non-S= ecure Memory."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "31:28"; > > + value =3D (aa64mmfr0_el1 >> 28) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D " 4KB granule supported."; > > + break; > > + case 0b1111: > > + description =3D " 4KB granule not supported."; > > + break; > > + case 0b0001: // add FEAT_LPA2 check > > + description =3D " 4KB granule supported for 52-bit address."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "43:40"; > > + value =3D (aa64mmfr0_el1 >> 40) & 0xf; > > + switch (value) { > > + case 0b0001: > > + description =3D " 4KB granule not supported at stage 2."; > > + break; > > + case 0b0010: > > + description =3D " 4KB granule supported at stage 2."; > > + break; > > + case 0b0011: > > + description =3D " 4KB granule supported at stage 2 for 52-bit ad= dress."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "23:20"; > > + value =3D (aa64mmfr0_el1 >> 20) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "16KB granule not supported."; > > + break; > > + case 0b0001: > > + description =3D "16KB granule supported."; > > + break; > > + case 0b0010: // add FEAT_LPA2 check > > + description =3D "16KB granule supported for 52-bit address."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "35:32"; > > + value =3D (aa64mmfr0_el1 >> 32) & 0xf; > > + switch (value) { > > + case 0b0001: > > + description =3D "16KB granule not supported at stage 2."; > > + break; > > + case 0b0010: > > + description =3D "16KB granule supported at stage 2."; > > + break; > > + case 0b0011: > > + description =3D "16KB granule supported at stage 2 for 52-bit ad= dress."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "27:24"; > > + value =3D (aa64mmfr0_el1 >> 24) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "64KB granule supported."; > > + break; > > + case 0b1111: > > + description =3D "64KB granule not supported."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "39:36"; > > + value =3D (aa64mmfr0_el1 >> 36) & 0xf; > > + switch (value) { > > + case 0b0001: > > + description =3D "64KB granule not supported at stage 2."; > > + break; > > + case 0b0010: > > + description =3D "64KB granule supported at stage 2."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "47:44"; > > + value =3D (aa64mmfr0_el1 >> 44) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_ExS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_ExS implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 55:48 reserved > > + > > + bits =3D "59:56"; > > + value =3D (aa64mmfr0_el1 >> 56) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_FGT not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_FGT implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "63:60"; > > + value =3D (aa64mmfr0_el1 >> 60) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_ECV not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_ECV implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_ECV implemented with extras."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > +} > > + > > +void > > +handle_aa64mmfr1_el1 ( > > + const UINT64 aa64mmfr1_el1, > > + const UINT64 aa64pfr0_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR1_EL1"; > > + char *description; > > + char *bits; > > + > > + bits =3D "3:0 "; > > + value =3D aa64mmfr1_el1 & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_HAFDBS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_HAFDBS implemented without dirty status su= pport."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_HAFDBS implemented with dirty status suppo= rt."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "7:4 "; > > + value =3D (aa64mmfr1_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_VMID16 not implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_VMID16 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "11:8 "; > > + value =3D (aa64mmfr1_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_VHE not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_VHE implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "15:12"; > > + value =3D (aa64mmfr1_el1 >> 12) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_HPDS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_HPDS implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_HPDS2 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "19:16"; > > + value =3D (aa64mmfr1_el1 >> 16) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_LOR not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_LOR implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "23:20"; > > + value =3D (aa64mmfr1_el1 >> 20) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_PAN not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_PAN implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_PAN2 implemented."; > > + break; > > + case 0b0011: > > + description =3D "FEAT_PAN3 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // when FEAT_RAS implemented > > + if ((((aa64pfr0_el1 >> 28) & 0xf) =3D=3D 0b0001) || > > + (((aa64pfr0_el1 >> 28) & 0xf) =3D=3D 0b0010)) > > + { > > + if (((aa64mmfr1_el1 >> 24) & 0xf) =3D=3D 0b0000 ) { > > + print_values ("ID_AA64MMFR1_EL1", "27:24", 0b0000, "The PE never= generates an SError interrupt due to"); > > + print_text ("", "", "", "an External abort on a speculative read= ."); > > + } > > + > > + if (((aa64mmfr1_el1 >> 24) & 0xf) =3D=3D 0b0001 ) { > > + print_values ("ID_AA64MMFR1_EL1", "27:24", 0b0001, "The PE might= generate an SError interrupt due to"); > > + print_text ("", "", "", "an External abort on a speculative read= ."); > > + } > > + } > > + > > + bits =3D "31:28"; > > + value =3D (aa64mmfr1_el1 >> 28) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_XNX not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_XNX implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "35:32"; > > + value =3D (aa64mmfr1_el1 >> 32) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_TWED not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_TWED implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "39:36"; > > + value =3D (aa64mmfr1_el1 >> 36) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_ETS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_ETS implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "43:40"; > > + value =3D (aa64mmfr1_el1 >> 40) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_HCX not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_HCX implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "47:44"; > > + value =3D (aa64mmfr1_el1 >> 44) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_AFP not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_AFP implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "51:48"; > > + value =3D (aa64mmfr1_el1 >> 48) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_nTLBPA not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_nTLBPA implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "55:52"; > > + value =3D (aa64mmfr1_el1 >> 52) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_TIDCP1 not implemented"; > > + break; > > + case 0b0001: > > + description =3D "FEAT_TIDCP1 implemented"; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "59:56"; > > + value =3D (aa64mmfr1_el1 >> 56) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_CMOW not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_CMOW implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 63:60 reserved > > +} > > + > > +void > > +handle_aa64mmfr2_el1 ( > > + const UINT64 aa64mmfr2_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64MMFR2_EL1"; > > + char *description; > > + char *bits; > > + > > + bits =3D "3:0 "; > > + value =3D (aa64mmfr2_el1) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_TTCNP not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_TTCNP implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "7:4 "; > > + value =3D (aa64mmfr2_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_UAO not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_UAO implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "11:8 "; > > + value =3D (aa64mmfr2_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_LSMAOC not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_LSMAOC implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "15:12"; > > + value =3D (aa64mmfr2_el1 >> 12) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_IESB not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_IESB implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "19:16"; > > + value =3D (aa64mmfr2_el1 >> 16) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_LVA not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_LVA implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "23:20"; > > + value =3D (aa64mmfr2_el1 >> 20) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_CCIDX not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_CCIDX implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "27:24"; > > + value =3D (aa64mmfr2_el1 >> 24) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_NV not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_NV implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_NV2 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "31:28"; > > + value =3D (aa64mmfr2_el1 >> 28) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_TTST not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_TTST implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "35:32"; > > + value =3D (aa64mmfr2_el1 >> 32) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_LSE2 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_LSE2 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "39:36"; > > + value =3D (aa64mmfr2_el1 >> 36) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_IDST not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_IDST implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "43:40"; > > + value =3D (aa64mmfr2_el1 >> 40) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_S2FWB not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_S2FWB implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 47:44 reserved > > + > > + bits =3D "51:48"; > > + value =3D (aa64mmfr2_el1 >> 48) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_TTL not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_TTL implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "55:52"; > > + value =3D (aa64mmfr2_el1 >> 52) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_BBM: Level 0 support for changing block si= ze is supported."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_BBM: Level 1 support for changing block si= ze is supported."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_BBM: Level 2 support for changing block si= ze is supported."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "59:56"; > > + value =3D (aa64mmfr2_el1 >> 56) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_EVT not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_EVT: HCR_EL2.{TOCU, TICAB, TID4} traps are= supported."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_EVT: HCR_EL2.{TTLBOS, TTLSBIS, TOCU, TICAB= , TID4} traps are supported."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "63:60"; > > + value =3D (aa64mmfr2_el1 >> 60) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_E0PD not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_E0PD implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > +} > > + > > +void > > +handle_aa64pfr0_el1 ( > > + const UINT64 aa64pfr0_el1, > > + const UINT64 aa64pfr1_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64PFR0_EL1"; > > + char *description; > > + char *bits; > > + > > + bits =3D "3:0 "; > > + value =3D (aa64pfr0_el1) & 0xf; > > + switch (value) { > > + case 0b0001: > > + description =3D "EL0 in AArch64 only"; > > + break; > > + case 0b0010: > > + description =3D "EL0 in AArch64 and AArch32"; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "7:4 "; > > + value =3D (aa64pfr0_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0001: > > + description =3D "EL1 in AArch64 only"; > > + break; > > + case 0b0010: > > + description =3D "EL1 in AArch64 and AArch32"; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "11:8 "; > > + value =3D (aa64pfr0_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "EL2 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "EL2 in AArch64 only"; > > + break; > > + case 0b0010: > > + description =3D "EL2 in AArch64 and AArch32"; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "15:12"; > > + value =3D (aa64pfr0_el1 >> 12) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "EL3 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "EL3 in AArch64 only"; > > + break; > > + case 0b0010: > > + description =3D "EL3 in AArch64 and AArch32"; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "19:16"; > > + value =3D (aa64pfr0_el1 >> 16) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Floating-point implemented."; > > + break; > > + case 0b0001: > > + description =3D "Floating-point with half-precision support (FE= AT_FP16)."; > > + break; > > + case 0b1111: > > + description =3D "Floating-point not implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "23:20"; > > + value =3D (aa64pfr0_el1 >> 20) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Advanced SIMD implemented."; > > + break; > > + case 0b0001: > > + description =3D "Advanced SIMD with half precision support (FEA= T_FP16)."; > > + break; > > + case 0b1111: > > + description =3D "Advanced SIMD not implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "27:24"; > > + value =3D (aa64pfr0_el1 >> 24) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "System registers of GIC CPU not implemented."; > > + break; > > + case 0b0001: > > + description =3D "System registers to versions 3.0/4.0 of GIC CPU= implemented."; > > + break; > > + case 0b0011: > > + description =3D "System registers to versions 4.1 of GIC CPU imp= lemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "31:28"; > > + value =3D (aa64pfr0_el1 >> 28) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_RAS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_RAS implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_RASv1p1 implemented."; > > + // 0b0010 FEAT_RASv1p1 implemented and, if EL3 is implemented, F= EAT_DoubleFault implemented. > > + if ((((aa64pfr0_el1 >> 12) & 0xf) =3D=3D 0b0001) || > > + (((aa64pfr0_el1 >> 12) & 0xf) =3D=3D 0b0010)) > > + { > > + description =3D "FEAT_RASv1p1 implemented. FEAT_DoubleFault im= plemented."; > > + } > > + > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "35:32"; > > + value =3D (aa64pfr0_el1 >> 32) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SVE not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SVE implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "39:36"; > > + value =3D (aa64pfr0_el1 >> 36) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Secure EL2 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "Secure EL2 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "43:40"; > > + value =3D (aa64pfr0_el1 >> 40) & 0xf; > > + switch (value) { > > + case 0b0000: > > + if (((aa64pfr1_el1 >> 16) & 0xf) =3D=3D 0b0000 ) { > > + description =3D "FEAT_MPAM not implemented."; > > + } > > + > > + if (((aa64pfr1_el1 >> 16) & 0xf) =3D=3D 0b0001 ) { > > + description =3D "FEAT_MPAM v0.1 implemented."; > > + } > > + > > + break; > > + case 0b0001: > > + if (((aa64pfr1_el1 >> 16) & 0xf) =3D=3D 0b0000 ) { > > + description =3D "FEAT_MPAM v1.0 implemented."; > > + } > > + > > + if (((aa64pfr1_el1 >> 16) & 0xf) =3D=3D 0b0001 ) { > > + description =3D "FEAT_MPAM v1.1 implemented."; > > + } > > + > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "47:44"; > > + value =3D (aa64pfr0_el1 >> 44) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_AMU not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_AMUv1 implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_AMUv1p1 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "51:48"; > > + value =3D (aa64pfr0_el1 >> 48) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_DIT not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_DIT implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "55:52"; > > + value =3D (aa64pfr0_el1 >> 52) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_RME not implemented"; > > + break; > > + case 0b0001: > > + description =3D "FEAT_RME implemented"; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "59:56"; > > + value =3D (aa64pfr0_el1 >> 56) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "no info is FEAT_CSV2 implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_CSV2 implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_CSV2_2 implemented."; > > + break; > > + case 0b0011: > > + description =3D "FEAT_CSV2_3 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + if (value =3D=3D 0b0001) { > > + if (((aa64pfr1_el1 >> 32) & 0xf) =3D=3D 0b0001 ) { > > + print_values ("ID_AA64PRF1_EL1", "35:32", 0b0001, "FEAT_CSV2_1p1= implemented."); > > + } > > + > > + if (((aa64pfr1_el1 >> 32) & 0xf) =3D=3D 0b0010 ) { > > + print_values ("ID_AA64PRF1_EL1", "35:32", 0b0010, "FEAT_CSV2_1p2= implemented."); > > + } > > + } > > + > > + bits =3D "63:60"; > > + value =3D (aa64pfr0_el1 >> 60) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_CSV3 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_CSV3 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > +} > > + > > +void > > +handle_aa64pfr1_el1 ( > > + const UINT64 aa64pfr1_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64PFR1_EL1"; > > + char *description; > > + char *bits; > > + > > + bits =3D "3:0 "; > > + value =3D aa64pfr1_el1 & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_BTI not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_BTI implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "7:4 "; > > + value =3D (aa64pfr1_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SSBS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SSBS implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_SSBS2 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "11:8 "; > > + value =3D (aa64pfr1_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_MTE not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_MTE implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_MTE2 implemented."; > > + break; > > + case 0b0011: > > + description =3D "FEAT_MTE3 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 15:12 is RAS_frac > > + // 19:16 is MPAM_frac > > + // 23:20 is reserved > > + > > + bits =3D "27:24"; > > + value =3D (aa64pfr1_el1 >> 24) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SME not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SME implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "31:28"; > > + value =3D (aa64pfr1_el1 >> 28) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_RNG_TRAP not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_RNG_TRAP implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 35:32 is CSV2_frac > > + > > + bits =3D "39:36"; > > + value =3D (aa64pfr1_el1 >> 36) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_NMI not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_NMI implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 63:40 are reserved > > +} > > + > > +void > > +handle_aa64isar0_el1 ( > > + const UINT64 aa64isar0_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR0_EL1"; > > + char *description; > > + char *bits; > > + > > + // 3:0 reserved > > + > > + bits =3D "7:4 "; > > + value =3D (aa64isar0_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_AES, FEAT_PMULL not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_AES implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_AES and FEAT_PMULL implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "11:8 "; > > + value =3D (aa64isar0_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SHA1 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SHA1 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "15:12"; > > + value =3D (aa64isar0_el1 >> 12) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SHA256, FEAT_SHA512 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SHA256 implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_SHA512 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "19:16"; > > + value =3D (aa64isar0_el1 >> 16) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "CRC32 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "CRC32 instructions implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "23:20"; > > + value =3D (aa64isar0_el1 >> 20) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_LSE not implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_LSE implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "27:24"; > > + value =3D (aa64isar0_el1 >> 24) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "TME instructions not implemented."; > > + break; > > + case 0b0001: > > + description =3D "TME instructions implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "31:28"; > > + value =3D (aa64isar0_el1 >> 28) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_RDM not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_RDM implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "35:32"; > > + value =3D (aa64isar0_el1 >> 32) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SHA3 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SHA3 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "39:36"; > > + value =3D (aa64isar0_el1 >> 36) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SM3 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SM3 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "43:40"; > > + value =3D (aa64isar0_el1 >> 40) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SM4 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SM4 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "47:44"; > > + value =3D (aa64isar0_el1 >> 44) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_DotProd not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_DotProd implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "51:48"; > > + value =3D (aa64isar0_el1 >> 48) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_FHM not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_FHM implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "55:52"; > > + value =3D (aa64isar0_el1 >> 52) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_FlagM/FEAT_FlagM2 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_FlagM implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_FlagM2 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "59:56"; > > + value =3D (aa64isar0_el1 >> 56) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_TLBIOS/FEAT_TLBIRANGE not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_TLBIOS implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_TLBIRANGE implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "63:60"; > > + value =3D (aa64isar0_el1 >> 60) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_RNG not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_RNG implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > +} > > + > > +void > > +handle_aa64isar1_el1 ( > > + const UINT64 aa64isar1_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR1_EL1"; > > + char *description; > > + char *bits; > > + > > + bits =3D "3:0 "; > > + value =3D (aa64isar1_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "DC CVAP not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_DPB implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_DPB2 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "7:4 "; > > + value =3D (aa64isar1_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Address Authentication (APA) not implemented."= ; > > + break; > > + case 0b0001: > > + description =3D "FEAT_PAuth implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_EPAC implemented."; > > + break; > > + case 0b0011: > > + description =3D "FEAT_PAuth2 implemented."; > > + break; > > + case 0b0100: > > + description =3D "FEAT_FPAC implemented."; > > + break; > > + case 0b0101: > > + description =3D "FEAT_FPACCOMBINE implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + if (value > 0) { > > + print_text ("", "", "", "FEAT_PACQARMA5 implemented."); > > + } > > + > > + bits =3D "11:8 "; > > + value =3D (aa64isar1_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Address Authentication (API) not implemented."= ; > > + break; > > + case 0b0001: > > + description =3D "FEAT_PAuth implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_EPAC implemented."; > > + break; > > + case 0b0011: > > + description =3D "FEAT_PAuth2 implemented."; > > + break; > > + case 0b0100: > > + description =3D "FEAT_FPAC implemented."; > > + break; > > + case 0b0101: > > + description =3D "FEAT_FPACCOMBINE implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + if (value > 0) { > > + print_text ("", "", "", "FEAT_PACIMP implemented."); > > + } > > + > > + bits =3D "15:12"; > > + value =3D (aa64isar1_el1 >> 12) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_JSCVT not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_JSCVT implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "19:16"; > > + value =3D (aa64isar1_el1 >> 16) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_FCMA not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_FCMA implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "23:20"; > > + value =3D (aa64isar1_el1 >> 20) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_LRCPC (2) not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_LRCPC implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_LRCPC2 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "27:24"; > > + value =3D (aa64isar1_el1 >> 24) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_PACQARMA5 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_PACQARMA5 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "31:28"; > > + value =3D (aa64isar1_el1 >> 28) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_PACIMP not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_PACIMP implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "35:32"; > > + value =3D (aa64isar1_el1 >> 32) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_FRINTTS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_FRINTTS implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "39:36"; > > + value =3D (aa64isar1_el1 >> 36) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SB not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SB implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "43:40"; > > + value =3D (aa64isar1_el1 >> 40) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SPECRES not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SPECRES implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "47:44"; > > + value =3D (aa64isar1_el1 >> 44) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_BF16 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_BF16 implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_EBF16 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "51:48"; > > + value =3D (aa64isar1_el1 >> 48) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_DGH not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_DGH implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "55:52"; > > + value =3D (aa64isar1_el1 >> 52) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_I8MM not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_I8MM implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "59:56"; > > + value =3D (aa64isar1_el1 >> 56) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_XS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_XS implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "63:60"; > > + value =3D (aa64isar1_el1 >> 60) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_LS64 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_LS64 implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_LS64_V implemented."; > > + break; > > + case 0b0011: > > + description =3D "FEAT_LS64_ACCDATA implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > +} > > + > > +void > > +handle_aa64isar2_el1 ( > > + const UINT64 aa64isar2_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64ISAR2_EL1"; > > + char *description; > > + char *bits; > > + > > + bits =3D "3:0 "; > > + value =3D (aa64isar2_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_WFxT not implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_WFxT implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "7:4 "; > > + value =3D (aa64isar2_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_RPRES not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_RPRES implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "11:8 "; > > + value =3D (aa64isar2_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_PACQARMA3 not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_PACQARMA3 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "15:12"; > > + value =3D (aa64isar2_el1 >> 12) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Address Authentication (APA3) not implemented.= "; > > + break; > > + case 0b0001: > > + description =3D "FEAT_PAuth implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_EPAC implemented."; > > + break; > > + case 0b0011: > > + description =3D "FEAT_PAuth2 implemented."; > > + break; > > + case 0b0100: > > + description =3D "FEAT_FPAC implemented."; > > + break; > > + case 0b0101: > > + description =3D "FEAT_FPACCOMBINE implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "19:16"; > > + value =3D (aa64isar2_el1 >> 16) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_MOPS not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_MOPS implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "23:20"; > > + value =3D (aa64isar2_el1 >> 20) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_HBC not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_HBC implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "27:24"; > > + value =3D (aa64isar2_el1 >> 24) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_CONSTPACFIELD not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_CONSTPACFIELD implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 63:28 reserved > > +} > > + > > +void > > +handle_aa64dfr0_el1 ( > > + const UINT64 aa64dfr0_el1 > > + ) > > +{ > > + UINT64 value; > > + STATIC CONST CHAR8 RegName[] =3D "ID_AA64DFR0_EL1"; > > + char *description; > > + char *bits; > > + > > + bits =3D "3:0 "; > > + value =3D (aa64dfr0_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0110: > > + description =3D "Armv8 debug architecture"; > > + break; > > + case 0b0111: > > + description =3D "Armv8 debug architecture with VHE"; > > + break; > > + case 0b1000: > > + description =3D "FEAT_Debugv8p2 implemented."; > > + break; > > + case 0b1001: > > + description =3D "FEAT_Debugv8p4 implemented."; > > + break; > > + case 0b1010: > > + description =3D "FEAT_Debugv8p8 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "7:4 "; > > + value =3D (aa64dfr0_el1 >> 4) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Trace unit System registers not implemented."; > > + break; > > + case 0b0001: > > + description =3D "Trace unit System registers implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "11:8 "; > > + value =3D (aa64dfr0_el1 >> 8) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Performance Monitors Extension not implemented.= "; > > + break; > > + case 0b0001: > > + description =3D "FEAT_PMUv3 implemented."; > > + break; > > + case 0b0100: > > + description =3D "FEAT_PMUv3p1 implemented."; > > + break; > > + case 0b0101: > > + description =3D "FEAT_PMUv3p4 implemented."; > > + break; > > + case 0b0110: > > + description =3D "FEAT_PMUv3p5 implemented."; > > + break; > > + case 0b0111: > > + description =3D "FEAT_PMUv3p7 implemented."; > > + break; > > + case 0b1000: > > + description =3D "FEAT_PMUv3p8 implemented."; > > + break; > > + case 0b1111: > > + description =3D "IMPLEMENTATION DEFINED form of performance moni= tors supported."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "15:12"; > > + value =3D (aa64dfr0_el1 >> 12) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "reserved"; > > + break; > > + default: > > + description =3D "Number of breakpoints, minus 1."; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 19:16 reserved > > + > > + bits =3D "23:20"; > > + value =3D (aa64dfr0_el1 >> 20) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "reserved"; > > + break; > > + default: > > + description =3D "Number of watchpoints, minus 1."; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 27:24 reserved > > + > > + bits =3D "31:28"; > > + value =3D (aa64dfr0_el1 >> 28) & 0xf; > > + switch (value) { > > + default: > > + description =3D "Number of breakpoints that are context-aware, m= inus 1."; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "35:32"; > > + value =3D (aa64dfr0_el1 >> 32) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_SPE not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_SPE implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_SPEv1p1 implemented."; > > + break; > > + case 0b0011: > > + description =3D "FEAT_SPEv1p2 implemented."; > > + break; > > + case 0b0100: > > + description =3D "FEAT_SPEv1p3 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "39:36"; > > + value =3D (aa64dfr0_el1 >> 36) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_DoubleLock implemented."; > > + break; > > + case 0b1111: > > + description =3D "FEAT_DoubleLock not implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "43:40"; > > + value =3D (aa64dfr0_el1 >> 40) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_TRF not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_TRF implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "47:44"; > > + value =3D (aa64dfr0_el1 >> 44) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_TRBE not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_TRBE implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "51:48"; > > + value =3D (aa64dfr0_el1 >> 48) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_MTPMU not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_MTPMU and FEAT_PMUv3 implemented."; > > + break; > > + case 0b1111: > > + description =3D "FEAT_MTPMU not implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + bits =3D "55:52"; > > + value =3D (aa64dfr0_el1 >> 52) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "FEAT_BRBE not implemented."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_BRBE implemented."; > > + break; > > + case 0b0010: > > + description =3D "FEAT_BRBEv1p1 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > + > > + // 59:56 reserved > > + > > + bits =3D "63:60"; > > + value =3D (aa64dfr0_el1 >> 60) & 0xf; > > + switch (value) { > > + case 0b0000: > > + description =3D "Setting MDCR_EL2.HPMN to zero has CONSTRAINED U= NPREDICTABLE behavior."; > > + break; > > + case 0b0001: > > + description =3D "FEAT_HPMN0 implemented."; > > + break; > > + default: > > + description =3D "unknown"; > > + break; > > + } > > + > > + print_values (RegName, bits, value, description); > > +} > > + > > +EFI_STATUS > > +EFIAPI > > +UefiMain ( > > + IN EFI_HANDLE ImageHandle, > > + IN EFI_SYSTEM_TABLE *SystemTable > > + ) > > +{ > > + UINT64 aa64dfr0_el1 =3D read_aa64dfr0_el1 (); > > + UINT64 aa64dfr1_el1 =3D read_aa64dfr1_el1 (); > > + UINT64 aa64isar0_el1 =3D read_aa64isar0_el1 (); > > + UINT64 aa64isar1_el1 =3D read_aa64isar1_el1 (); > > + UINT64 aa64isar2_el1 =3D read_aa64isar2_el1 (); > > + UINT64 aa64mmfr0_el1 =3D read_aa64mmfr0_el1 (); > > + UINT64 aa64mmfr1_el1 =3D read_aa64mmfr1_el1 (); > > + UINT64 aa64mmfr2_el1 =3D read_aa64mmfr2_el1 (); > > + UINT64 aa64pfr0_el1 =3D read_aa64pfr0_el1 (); > > + UINT64 aa64pfr1_el1 =3D read_aa64pfr1_el1 (); > > EDK2 requires separation between declarations and code (something > alike old C89 semantics, but stricter). so: > UINT64 aa64pfr1_el1; > <...> > aa64pfr1_el1 =3D read_aa64pfr1_el1 (); > > > + > > + /* UINT64 aa64smfr0_el1 =3D read_aa64smfr0_el1 ();*/ > > + /* UINT64 aa64zfr0_el1 =3D read_aa64zfr0_el1 ();*/ > > Dead Code? > > + > > + AsciiPrint ("ID_AA64MMFR0_EL1 =3D 0x%016lx\n", aa64mmfr0_el1); > > + AsciiPrint ("ID_AA64MMFR1_EL1 =3D 0x%016lx\n", aa64mmfr1_el1); > > + AsciiPrint ("ID_AA64MMFR2_EL1 =3D 0x%016lx\n", aa64mmfr2_el1); > > + AsciiPrint ("ID_AA64PFR0_EL1 =3D 0x%016lx\n", aa64pfr0_el1); > > + AsciiPrint ("ID_AA64PFR1_EL1 =3D 0x%016lx\n", aa64pfr1_el1); > > + AsciiPrint ("ID_AA64ISAR0_EL1 =3D 0x%016lx\n", aa64isar0_el1); > > + AsciiPrint ("ID_AA64ISAR1_EL1 =3D 0x%016lx\n", aa64isar1_el1); > > + AsciiPrint ("ID_AA64ISAR2_EL1 =3D 0x%016lx\n", aa64isar2_el1); > > + AsciiPrint ("ID_AA64DFR0_EL1 =3D 0x%016lx\n", aa64dfr0_el1); > > + AsciiPrint ("ID_AA64DFR1_EL1 =3D 0x%016lx\n", aa64dfr1_el1); = // ignore > > Why ignore? > > > + /* AsciiPrint ("ID_AA64SMFR0_EL1 =3D 0x%016lx\n", aa64smfr0_el1);= */ > > + /* AsciiPrint ("ID_AA64ZFR0_EL1 =3D 0x%016lx\n", aa64zfr0_el1);*/ > > dead? > > + > > + AsciiPrint ("\n"); > > + print_text ("Register", "Bits", "Value", "Feature"); > > + print_spacer (); > > + > > + handle_aa64mmfr0_el1 (aa64mmfr0_el1); > > + print_spacer (); > > + handle_aa64mmfr1_el1 (aa64mmfr1_el1, aa64pfr0_el1); > > + print_spacer (); > > + handle_aa64mmfr2_el1 (aa64mmfr2_el1); > > + > > + print_spacer (); > > + handle_aa64pfr0_el1 (aa64pfr0_el1, aa64pfr1_el1); > > + print_spacer (); > > + handle_aa64pfr1_el1 (aa64pfr1_el1); > > + > > + print_spacer (); > > + handle_aa64isar0_el1 (aa64isar0_el1); > > + print_spacer (); > > + handle_aa64isar1_el1 (aa64isar1_el1); > > + print_spacer (); > > + handle_aa64isar2_el1 (aa64isar2_el1); > > + > > + print_spacer (); > > + handle_aa64dfr0_el1 (aa64dfr0_el1); > > + > > + return EFI_SUCCESS; > > +} > > diff --git a/ArmPkg/Application/ArmCpuInfo/readregs.s b/ArmPkg/Applicat= ion/ArmCpuInfo/readregs.s > > ASM files that require preprocessing should have a capital S here (.S vs = .s) > > > new file mode 100644 > > index 000000000000..052834b3c3f2 > > --- /dev/null > > +++ b/ArmPkg/Application/ArmCpuInfo/readregs.s > > @@ -0,0 +1,49 @@ > > +#include > > + > > +ASM_FUNC(read_aa64pfr0_el1) > > + mrs x0, ID_AA64PFR0_EL1; > > + ret; > > ASM lines (for GAS at least) don't usually end in semicolons. so > +ASM_FUNC(read_aa64pfr0_el1) > + mrs x0, ID_AA64PFR0_EL1 > + ret > > You'd only need the semicolons if you had multiple instructions in one > line (like mrs x0, ID_AA...; ret) > > > + > > +ASM_FUNC(read_aa64pfr1_el1) > > + mrs x0, ID_AA64PFR1_EL1; > > + ret; > > + > > +ASM_FUNC(read_aa64dfr0_el1) > > + mrs x0, ID_AA64DFR0_EL1; > > + ret; > > + > > +ASM_FUNC(read_aa64dfr1_el1) > > + mrs x0, ID_AA64DFR1_EL1; > > + ret; > > + > > +ASM_FUNC(read_aa64isar0_el1) > > + mrs x0, ID_AA64ISAR0_EL1; > > + ret; > > + > > +ASM_FUNC(read_aa64isar1_el1) > > + mrs x0, ID_AA64ISAR1_EL1; > > + ret; > > + > > +ASM_FUNC(read_aa64isar2_el1) > > + mrs x0, ID_AA64ISAR2_EL1; > > + ret; > > + > > +ASM_FUNC(read_aa64mmfr0_el1) > > + mrs x0, ID_AA64MMFR0_EL1; > > + ret; > > + > > +ASM_FUNC(read_aa64mmfr1_el1) > > + mrs x0, ID_AA64MMFR1_EL1; > > + ret; > > + > > +ASM_FUNC(read_aa64mmfr2_el1) > > + mrs x0, ID_AA64MMFR2_EL1; > > + ret; > > + > > +# ASM_FUNC(read_aa64zfr0_el1) > > +# mrs x0, ID_AA64ZFR0_EL1; > > +# ret; > > + > > +# ASM_FUNC(read_aa64smfr0_el1) > > +# mrs x0, ID_AA64SMFR0_EL1; > > +# ret; > > Dead code? > > > -- > > 2.40.0 > > Marcin, > > Brief comments in general: > 1) You use binary literals extensively, which are not portable (GNU C > extension, AFAIK not in MSVC) > > 2) Naming of identifiers (vars, functions, etc) needs to follow the > EDK2 style. eg: > description vs Description > read_aa64mmfr1_el1 vs ReadAa64MmfrEl1 > etc... > > -- > Pedro --=20 Pedro