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From: "Pedro Falcato" <pedro.falcato@gmail.com>
Date: Sun, 29 Oct 2023 19:15:14 +0000
Message-ID: <CAKbZUD1-qgRx+jZOZOCNiQ+0JufVLbFU58bTHDm1bBiS8stDqg@mail.gmail.com>
Subject: Re: [edk2-devel] [PATCH v7 0/5] Cache Management Operations Support For RISC-V
To: devel@edk2.groups.io, dhaval@rivosinc.com
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>, Jiewen Yao <jiewen.yao@intel.com>,
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On Sun, Oct 29, 2023 at 2:46=E2=80=AFPM Dhaval Sharma <dhaval@rivosinc.com>=
wrote:
>
> Implementing code to support Cache Management Operations (CMO) defined by
> RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
> This is a re-write of original series v5.
> The patchset contains 5 patches- created based on V5 feedback.
> 1. Restructuring of existing code and move instruction declarations into =
BaseLib
> 2. Renaming existing functions to denote type of instruction used to maan=
age cache.
> This is useful for further patches where more cache management instruc=
tions are added.
> 3. Add the new cache maintenance operations to BaseLib, including the
> new assembly instruction encodings.
> 4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
> 5. Add platform level PCD to allow overriding of RISC-V features.
>
With or without nits fixed:
Reviewed-by: Pedro Falcato <pedro.falcato@gmail.com>
But I would *really* prefer it if you could test this on a real board
with this extension.
--=20
Pedro
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