From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 4B0EB941B75 for ; Sun, 29 Oct 2023 19:07:32 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Or1WW/aVa3Hq74eEBx424QEy5YtEdIQ8jWVf+tmIsEw=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1698606450; v=1; b=fCqNUR8lmEEsGFnrqiGkq5rGUoK7Z1D0BXhBvOLD5NJGHrjSye9ttdd2n1W9rD+SJUMzJcAw q4XKQkcNpyQBoMOEhZuVsL0NNzWhTJ9G6P62thnvH3M5L2MA6lbXgVVqpgjHcrAxpLBIergtR2r 7aThcKvBJQu/GnIyWfG0hhQg= X-Received: by 127.0.0.2 with SMTP id ryyAYY7687511xIObqOabU1r; Sun, 29 Oct 2023 12:07:30 -0700 X-Received: from mail-vs1-f42.google.com (mail-vs1-f42.google.com [209.85.217.42]) by mx.groups.io with SMTP id smtpd.web11.78664.1698606450224124403 for ; Sun, 29 Oct 2023 12:07:30 -0700 X-Received: by mail-vs1-f42.google.com with SMTP id ada2fe7eead31-45865d6e588so2478034137.0 for ; Sun, 29 Oct 2023 12:07:30 -0700 (PDT) X-Gm-Message-State: oMpUQb4opqJaU7Ik7PCx4Zkax7686176AA= X-Google-Smtp-Source: AGHT+IElPu7/OYCERLu6SCjpz3zmZ4a0FHvKb2T8VNiJiMDxUgNLh0eMECv6BIA6ypjrC87BIFweefcVhoOkAJjIakk= X-Received: by 2002:a05:6102:1043:b0:450:cebb:4f15 with SMTP id h3-20020a056102104300b00450cebb4f15mr4918175vsq.1.1698606449071; Sun, 29 Oct 2023 12:07:29 -0700 (PDT) MIME-Version: 1.0 References: <20231029144613.150580-1-dhaval@rivosinc.com> <20231029144613.150580-5-dhaval@rivosinc.com> In-Reply-To: <20231029144613.150580-5-dhaval@rivosinc.com> From: "Pedro Falcato" Date: Sun, 29 Oct 2023 19:07:18 +0000 Message-ID: Subject: Re: [edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V To: devel@edk2.groups.io, dhaval@rivosinc.com Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pedro.falcato@gmail.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=fCqNUR8l; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=gmail.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Sun, Oct 29, 2023 at 2:46=E2=80=AFPM Dhaval Sharma = wrote: > > Use newly defined cache management operations for RISC-V where possible > It builds up on the support added for RISC-V cache management > instructions in BaseLib. > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > Cc: Laszlo Ersek > > Signed-off-by: Dhaval Sharma > Acked-by: Laszlo Ersek > --- > > Notes: > V7: > - Added PcdLib > - Restructure DEBUG message based on feedback on V6 > - Make naming consistent to CMO, remove all CBO references > - Add ASSERT for not supported functions instead of plain debug messa= ge > - Added RB tag > V6: > - Utilize cache management instructions if HW supports it > This patch is part of restructuring on top of v5 > > MdePkg/MdePkg.dec | 8= + > MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 5= + > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 168= +++++++++++++++++--- > MdePkg/MdePkg.uni | 4= + > 4 files changed, 165 insertions(+), 20 deletions(-) > > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec > index ac54338089e8..fa92673ff633 100644 > --- a/MdePkg/MdePkg.dec > +++ b/MdePkg/MdePkg.dec > @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.A= ARCH64] > # @Prompt CPU Rng algorithm's GUID. > gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0= x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00= 000037 > > +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] > + # > + # Configurability to override RISC-V CPU Features > + # BIT 0 =3D Cache Management Operations. This bit is relevant only if > + # previous stage has feature enabled and user wants to disable it. > + # > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UI= NT64|0x69 > + > [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] > ## This value is used to set the base address of PCI express hierarchy= . > # @Prompt PCI Express Base Address. > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceL= ib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > index 6fd9cbe5f6c9..601a38d6c109 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > @@ -56,3 +56,8 @@ [LibraryClasses] > BaseLib > DebugLib > > +[LibraryClasses.RISCV64] > + PcdLib > + > +[Pcd.RISCV64] > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg= /Library/BaseCacheMaintenanceLib/RiscVCache.c > index 4eb18edb9aa7..5b3104afb67e 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > @@ -2,6 +2,7 @@ > RISC-V specific functionality for cache. > > Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rig= hts reserved.
> + Copyright (c) 2023, Rivos Inc. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > @@ -9,10 +10,115 @@ > #include > #include > #include > +#include > + > +// > +// TODO: Grab cache block size and make Cache Management Operation > +// enabling decision based on RISC-V CPU HOB in > +// future when it is available. > +// > +#define RISCV_CACHE_BLOCK_SIZE 64 > +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1 > + > +typedef enum { > + Clean, > + Flush, > + Invld, > +} CACHE_OP; small nit: You may want to do something like CACHE_OP_{CLEAN, FLUSH, INVID}. but since this is a file-local enum I don't consider this merge-blocking. --=20 Pedro -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110275): https://edk2.groups.io/g/devel/message/110275 Mute This Topic: https://groups.io/mt/102256468/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-