From: "Pedro Falcato" <pedro.falcato@gmail.com>
To: devel@edk2.groups.io, mcb30@ipxe.org
Cc: jlotwo@gmail.com, Ard Biesheuvel <ardb@kernel.org>
Subject: Re: [edk2-devel] [RFC] Ordering of Arm PCI ECAM and MMIO operations
Date: Wed, 1 Nov 2023 23:07:54 +0000 [thread overview]
Message-ID: <CAKbZUD19XU32GVFuHnjF1bFvw45TexOPVMsctL3YYtJhK-n-wQ@mail.gmail.com> (raw)
In-Reply-To: <0102018b8cde55ad-1703490f-ed69-4b5a-81dc-9bf2a378d064-000000@eu-west-1.amazonses.com>
On Wed, Nov 1, 2023 at 9:51 PM Michael Brown <mcb30@ipxe.org> wrote:
>
> On 01/11/2023 20:17, Joe L wrote:
> > Thanks for the discussion,
> >
> > Are we saying that DataSynchronizationBarrier () before the return
> > from RootBridgeIoPciAccess() is not strong enough to determine that
> > the final ECAM write would have completed? According to Learn the
> > architecture - ARMv8-A memory systems
> > <https://developer.arm.com/documentation/100941/0101/Barriers> the
> > DSB should block "execution of any further instructions, not just
> > loads or stores, until synchronization is complete". To me this means
> > that for Arm the DSB will stall any subsequent instructions until the
> > completion for the ECAM write is received by the processor.
>
> I honestly can't tell from the wording there whether or not DSB would
> guarantee that the configuration space write has completed all the way
> to the target PCIe device (as opposed to e.g. completing as far as the
> host bridge, or to an intermediate PCIe bridge).
>
> I don't know the answer, and it feels like the kind of messy area where
> adding a barrier will definitely reduce the probability of the issue
> occurring but might not guarantee a fix, which is a bad situation to be
> left in.
Given we are working with Device nGnRnE memory, and the documentation
says stuff like
" This determines whether an intermediate write buffer between the
processor and the slave device being accessed is allowed to send an
acknowledgement of a write completion. If the address is marked as non
Early Write Acknowledgement (nE), then the write response must come
from the peripheral. If the address is marked as Early Write
Acknowledgement (E), then it is permissible for a buffer in the
interconnect logic to signal write acceptance, in advance of the write
actually being received by the end device. This is essentially a
message to the external memory system."
I would expect the write ACK to come from the device itself (I can't
wait for the obscure ARM doc that proves me wrong!)
--
Pedro
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prev parent reply other threads:[~2023-11-01 23:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-31 23:24 [edk2-devel] [RFC] Ordering of Arm PCI ECAM and MMIO operations Joe L
2023-11-01 2:09 ` Pedro Falcato
2023-11-01 9:56 ` Ard Biesheuvel
2023-11-01 12:25 ` Michael Brown
2023-11-01 12:51 ` Ard Biesheuvel
2023-11-01 13:23 ` Michael Brown
2023-11-01 16:41 ` Ard Biesheuvel
2023-11-01 20:17 ` Joe L
2023-11-01 21:51 ` Michael Brown
2023-11-01 23:07 ` Pedro Falcato [this message]
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