From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) by mx.groups.io with SMTP id smtpd.web10.4097.1661809300522731875 for ; Mon, 29 Aug 2022 14:41:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=K0XY6mLB; spf=pass (domain: gmail.com, ip: 209.85.216.42, mailfrom: pedro.falcato@gmail.com) Received: by mail-pj1-f42.google.com with SMTP id h13-20020a17090a648d00b001fdb9003787so4612757pjj.4 for ; Mon, 29 Aug 2022 14:41:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc; bh=PyXQWDtlO4ae/GL7nrxpKJ8xytIs8wnqd7gHUoinEs0=; b=K0XY6mLBBdFRwUtV8T5gXW5oM546G8v5T1qm43v7UqznlqFh6Dbhwo8Q9Wl5ZnojDu weHAQ/Tmar/Ri5XNfr+IKMx4AH0j7rUBD3Np/C3ZUZG944HpDz70ilH0vZi1jqLW8efr hLJoee9tUvLAtKjDtHpzmoKwOKRqB5/A63A+q8S38LYqkXuyuCzExRKcZHzQY7zZagIi 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2002:a17:902:b48f:b0:172:b57e:f0ff with SMTP id y15-20020a170902b48f00b00172b57ef0ffmr18330392plr.25.1661809299365; Mon, 29 Aug 2022 14:41:39 -0700 (PDT) MIME-Version: 1.0 References: <20220827000201.22235-1-theojehl76@gmail.com> <20220827000201.22235-2-theojehl76@gmail.com> In-Reply-To: <20220827000201.22235-2-theojehl76@gmail.com> From: "Pedro Falcato" Date: Mon, 29 Aug 2022 22:41:26 +0100 Message-ID: Subject: Re: [edk2-platforms][PATCH v1 01/02] QemuOpenBoardPkg: Add QemuOpenBoardPkg To: =?UTF-8?B?VGjDqW8=?= Cc: edk2-devel-groups-io , Leif Lindholm , Michael D Kinney , Isaac Oram , Gerd Hoffmann , Stefan Hajnoczi Content-Type: multipart/alternative; boundary="000000000000f925e905e7682046" --000000000000f925e905e7682046 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Sat, Aug 27, 2022 at 1:02 AM Th=C3=A9o wrote: > From: Th=C3=A9o Jehl > > QemuOpenBoardPkg adds a MinPlatform port to Qemu x86_64 > It can boots UEFI Linux and Windows, and works on PIIX4 and Q35 > This board port provides a simple starting place for investigating edk2 a= nd > MinPlatform Arch. > Currently we implement up to stage 4 of the MinPlatform spec and can boot > Windows/Linux. > > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Isaac Oram > Cc: Pedro Falcato > Cc: Gerd Hoffmann > Cc: Stefan Hajnoczi > > Signed-off-by: Th=C3=A9o Jehl > --- > Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec > | 32 + > Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc > | 55 ++ > Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc > | 31 + > Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc > | 100 +++ > Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc > | 56 ++ > Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc > | 144 +++++ > Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf > | 313 ++++++++++ > Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootMana= gerLib.inf > | 39 ++ > Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.inf > | 29 + > Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLib= .inf > | 23 + > Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf > | 63 ++ > Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf > | 49 ++ > Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf > | 59 ++ > Platform/Qemu/QemuOpenBoardPkg/Include/Library/OpenQemuFwCfgLib.h > | 102 +++ > Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h > | 59 ++ > Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootMana= ger.c > | 105 ++++ > Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c > | 222 +++++++ > Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLib= .c > | 130 ++++ > Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c > | 285 +++++++++ > Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.c > | 140 +++++ > Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c > | 56 ++ > Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c > | 244 ++++++++ > Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c > | 59 ++ > Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c > | 91 +++ > Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c > | 67 ++ > Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc > | 85 +++ > Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/SecEntry.nasm > | 117 ++++ > Platform/Qemu/QemuOpenBoardPkg/README.md > | 53 ++ > 28 files changed, 2808 insertions(+) > > diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec > b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec > new file mode 100644 > index 000000000000..3b5300a0c309 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec > @@ -0,0 +1,32 @@ > +## @file QemuOpenBoardPkg.dec > +# Declaration file for QemuOpenBoardPkg. > +# > +# This package supports a simple QEMU port implemented per the > MinPlatform > +# Arch specification. > +# > +# Copyright (c) 2022 Th=C3=A9o Jehl > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# @par Specification Reference: > +# - > https://tianocore-docs.github.io/edk2-MinimumPlatformSpecification/draft/ > 0.7 > +## > + > +[Defines] > + DEC_SPECIFICATION =3D 0x00010005 > + PACKAGE_NAME =3D QemuOpenBoardPkg > + PACKAGE_GUID =3D 3487DE0A-6770-48A2-9833-FB426A42D7B= 2 > + PACKAGE_VERSION =3D 0.1 > + > +[LibraryClasses] > + OpenQemuFwCfgLib|Include/Library/OpenQemuFwCfgLib.h > + > +[Includes] > + Include > + > +[Guids] > + gQemuOpenBoardPkgTokenSpaceGuid =3D { 0x221b20c4, > 0xa3dc, 0x4b8f, { 0xb6, 0x94, 0x03, 0xc7, 0xf4, 0x76, 0x51, 0x2b } } > + > +[PcdsFixedAtBuild] > + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x0000000= 1 > + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x0000000= 2 > + gQemuOpenBoardPkgTokenSpaceGuid.PcdDebugIoPort|0|UINT16|0x00000003 > diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc > b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc > new file mode 100644 > index 000000000000..114c4e8193b2 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc > @@ -0,0 +1,55 @@ > +## @file > +# Common DSC content to begin Stage 1 enabling > +# > +# @copyright > +# Copyright (C) 2022 Intel Corporation > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > > +########################################################################= ######## > +# > +# Library Class section - list of all Library Classes needed by this > Platform. > +# > > +########################################################################= ######## > + > +[LibraryClasses] > + PciSegmentInfoLib | > MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimpl= e.inf > + BoardInitLib | > QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.inf > + SetCacheMtrrLib | > MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf > + ReportCpuHobLib | > MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf > + SiliconPolicyInitLib | > MinPlatformPkg/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolic= yInitLibNull.inf > + SiliconPolicyUpdateLib | > MinPlatformPkg/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPol= icyUpdateLibNull.inf > + ReportFvLib | > QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf > + PciLib | MdePkg/Library/BasePciLibCf8/BasePciLibCf8.i= nf > + > +[LibraryClasses.Common.SEC] > + TestPointCheckLib | > MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf > + TimerLib | > MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf > + > +[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM] > + TestPointCheckLib | > MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf > + TestPointLib | > MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf > + TimerLib | > MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf > + > +[Components.$(PEI_ARCH)] > + UefiCpuPkg/SecCore/SecCore.inf > + MdeModulePkg/Core/Pei/PeiMain.inf > + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf > + UefiCpuPkg/CpuIoPei/CpuIoPei.inf > + > MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCf= g2Pei.inf > + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf > + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { > + > + PcdLib | MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > + } > + > MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterP= ei.inf > + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf > + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf > + MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf > + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.in= f > + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > + QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf > + !if $(SMM_REQUIRED) =3D=3D TRUE > + OvmfPkg/SmmAccess/SmmAccessPei.inf > + !endif > diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc > b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc > new file mode 100644 > index 000000000000..4b331c4ed1fc > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc > @@ -0,0 +1,31 @@ > +## @file > +# Common DSC content to begin Stage 2 enabling > +# > +# @copyright > +# Copyright (C) 2022 Jehl Th=C3=A9o > Why is your name backwards here (and in other places)? > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > +[LibraryClasses.Common] > + ResetSystemLib | > OvmfPkg/Library/ResetSystemLib/BaseResetSystemLib.inf > + PciHostBridgeLib | > OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf > + PciHostBridgeUtilityLib | > OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf > + DxeHardwareInfoLib | > OvmfPkg/Library/HardwareInfoLib/DxeHardwareInfoLib.inf > + > +[LibraryClasses.Common.PEIM] > + MpInitLib | UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.in= f > + TimerLib | > OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf > + > +[LibraryClasses.Common.DXE_DRIVER, > LibraryClasses.Common.DXE_RUNTIME_DRIVER, > LibraryClasses.Common.DXE_SMM_DRIVER, LibraryClasses.Common.UEFI_DRIVER, > LibraryClasses.Common.UEFI_APPLICATION, LibraryClasses.Common.SMM_CORE] > + PciLib | > OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf > + > +[Components.$(PEI_ARCH)] > + UefiCpuPkg/CpuMpPei/CpuMpPei.inf > + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.i= nf > + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf > + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > + > +[Components.$(DXE_ARCH)] > + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc > b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc > new file mode 100644 > index 000000000000..0435fb2da81d > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc > @@ -0,0 +1,100 @@ > +## @file > +# Common DSC content to begin Stage 3 enabling > +# > +# @copyright > +# Copyright (C) 2022 Jehl Th=C3=A9o > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > +[LibraryClasses.Common] > + PlatformBootManagerLib | > OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf > + BootLogoLib | > MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf > + NvVarsFileLib | > OvmfPkg/Library/NvVarsFileLib/NvVarsFileLib.inf > + QemuFwCfgS3Lib | > OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf > + QemuLoadImageLib | > OvmfPkg/Library/X86QemuLoadImageLib/X86QemuLoadImageLib.inf > + QemuBootOrderLib | > OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.inf > + PlatformBmPrintScLib | > OvmfPkg/Library/PlatformBmPrintScLib/PlatformBmPrintScLib.inf > + XenPlatformLib | > OvmfPkg/Library/XenPlatformLib/XenPlatformLib.inf > + LoadLinuxLib | OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.in= f > + SerializeVariablesLib | > OvmfPkg/Library/SerializeVariablesLib/SerializeVariablesLib.inf > + BoardBootManagerLib | > QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf > + LocalApicLib | > UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf > + IoLib | > MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > + PciExpressLib | > MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf > + PcdLib | MdePkg/Library/DxePcdLib/DxePcdLib.inf > + PciLib | MdePkg/Library/BasePciLibCf8/BasePciLibCf8.i= nf > + DebugLib | > MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf > + SerialPortLib | > PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf > + > +[Components.$(DXE_ARCH)] > + MdeModulePkg/Core/Dxe/DxeMain.inf { > + > + > NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib= .inf > + } > + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { > + > + PcdLib | MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf > + } > + > MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCode= RouterRuntimeDxe.inf > + > MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRunt= imeDxe.inf > + MdeModulePkg/Universal/Metronome/Metronome.inf > + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf > + > PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.in= f > + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf > + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf > + > MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntime= Dxe.inf > + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf > + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf > + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf > + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf > + UefiCpuPkg/CpuDxe/CpuDxe.inf > + PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf > + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf > + MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf > + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.i= nf > + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf > + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf > + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf > + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf > + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf > + OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf > + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf > + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf > + MdeModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf > + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf > + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf > + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf > + PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf > + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf > + FatPkg/EnhancedFatDxe/Fat.inf > + OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf > + > + ShellPkg/Application/Shell/Shell.inf { > + > + ShellCommandLib | > ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf > + NULL | > ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.in= f > + NULL | > ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.in= f > + NULL | > ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.in= f > + NULL | > ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.= inf > + NULL | > ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.in= f > + NULL | > ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLi= b.inf > + NULL | > ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLi= b.inf > + HandleParsingLib | > ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf > + PrintLib | MdePkg/Library/BasePrintLib/BasePrintLib.inf > + BcfgCommandLib | > ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf > + > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask | 0xFF > + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize | FALSE > + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize | 8000 > + } > + > + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf > + OvmfPkg/PlatformDxe/Platform.inf > + MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf > + MdeModulePkg/Application/UiApp/UiApp.inf > + OvmfPkg/IoMmuDxe/IoMmuDxe.inf > + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf > + OvmfPkg/SioBusDxe/SioBusDxe.inf > + MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf > diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc > b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc > new file mode 100644 > index 000000000000..4a1f9c7d0124 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc > @@ -0,0 +1,56 @@ > +## @file > +# Common DSC content to begin Stage 4 enabling > +# > +# @copyright > +# Copyright (C) 2022 Jehl Th=C3=A9o > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > + > +[LibraryClasses] > + !if $(SMM_REQUIRED) =3D=3D TRUE > + SpiFlashCommonLib | > IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf > + !endif > + > +[LibraryClasses.Common.DXE_SMM_DRIVER] > + LockBoxLib | > MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf > + SmmCpuPlatformHookLib | > OvmfPkg/Library/SmmCpuPlatformHookLibQemu/SmmCpuPlatformHookLibQemu.inf > + SmmCpuFeaturesLib | > OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf > + > +[Components.$(DXE_ARCH)] > + OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf > + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf > + OvmfPkg/SataControllerDxe/SataControllerDxe.inf > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf > + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf > + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf > + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf > + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf > + > + !if $(SMM_REQUIRED) =3D=3D TRUE > + OvmfPkg/SmmAccess/SmmAccess2Dxe.inf > + OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf > + MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf > + MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf > + > + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf > + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > + > + > MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterS= mm.inf > + MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.in= f > + UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf > + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.i= nf > + IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf > + !endif > + > + # > + # SMBIOS Support > + # > + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf { > + > + NULL | OvmfPkg/Library/SmbiosVersionLib/DetectSmbiosVersionLib.inf > + } > + OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf > diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc > b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc > new file mode 100644 > index 000000000000..958d6b9537c9 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc > @@ -0,0 +1,144 @@ > +## @file > +# QemuOpenBoardPkg.dsc > +# > +# Description file for QemuOpenBoardPkg > +# > +# Copyright (c) 2022 Th=C3=A9o Jehl > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > +[Defines] > + DSC_SPECIFICATION =3D 0x0001001C > + PLATFORM_GUID =3D 94797875-D562-40CF-8D55-ADD623C8D46C > + PLATFORM_NAME =3D QemuOpenBoardPkg > + PLATFORM_VERSION =3D 0.1 > + SUPPORTED_ARCHITECTURES =3D IA32 | X64 > + FLASH_DEFINITION =3D $(PLATFORM_NAME)/$(PLATFORM_NAME).fdf > + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME) > + BUILD_TARGETS =3D DEBUG | RELEASE | NOOPT > + SKUID_IDENTIFIER =3D ALL > + SMM_REQUIRED =3D FALSE > + > +!ifndef $(PEI_ARCH) > + !error "PEI_ARCH must be specified to build this feature!" > s/feature/package/ > +!endif > +!ifndef $(DXE_ARCH) > + !error "DXE_ARCH must be specified to build this feature!" > s/feature/package/ > +!endif > + > +[SkuIds] > + 0 | DEFAULT > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + QemuOpenBoardPkg/QemuOpenBoardPkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[PcdsFixedAtBuild] > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage | 4 > + > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel | 0x802A00C7 > + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel | 0x802A00C7 > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask | 0x17 > + > + # QEMU "memory" is functional even in SEC. For simplicity, we just us= e > that > + # "memory" for the temporary RAM > + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase | 0x1000000 > 16MB is way too high for a temporary RAM base, although in practice that shouldn't matter (QEMU defaults to 128MB and I'm not sure anyone runs it with less). Is it possible to pick something lower? > + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize | 0x010000 > + > + gQemuOpenBoardPkgTokenSpaceGuid.PcdDebugIoPort | 0x402 > + gEfiMdePkgTokenSpaceGuid.PcdFSBClock | 100000000 > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress | 0xB0000000 > Please explain why we pick this address (no magic values!). Most people don't have the same context you do. > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable = | > TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange = | > FALSE > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase | 0x00000000 # Will b= e > updated by build > + > +[PcdsFeatureFlag] > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable | TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable | FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable | FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|TRUE > + > + !if $(DXE_ARCH) =3D=3D X64 > + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode | TRUE > + !else > + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode | FALSE > + !endif > + > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly | TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable | TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable | FALSE > + > + !if $(SMM_REQUIRED) =3D=3D TRUE > + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire | TRUE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport | FALS= E > + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache | FALS= E > + !endif > + > +[PcdsDynamicDefault] > + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId | 0 > + > + # Video setup > + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution | 64= 0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution | 48= 0 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion | 0x0208 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev | 0x0 > + > + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut | 3 > + > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | 0 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber | 0 > + > + !if $(SMM_REQUIRED) =3D=3D TRUE > + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes | 8 > + gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase | FALSE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode | 0x01 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout | 100000 > + !endif > + > +# Include Common libraries and then stage specific libraries and > components > +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc > +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > +!include QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc > +!include QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc > +!include QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc > +!include QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc > As discussed in private, I'm torn on this StageN.dsc.inc thing. It's great to understand what each specific stage requires, horrible to understand how the platform works in general. > + > +[LibraryClasses.Common] > + OpenQemuFwCfgLib | > QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLib.inf > + PlatformHookLib | > MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf > + PlatformSecLib | > QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf > + DebugLib | > MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf > + PciCf8Lib | MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.i= nf > + TimerLib | > OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf > + > +[LibraryClasses.Common.DXE_CORE] > + TimerLib | > OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf > + > +[LibraryClasses.Common.DXE_DRIVER, > LibraryClasses.Common.DXE_RUNTIME_DRIVER, > LibraryClasses.Common.DXE_SMM_DRIVER, LibraryClasses.Common.UEFI_DRIVER, > LibraryClasses.Common.UEFI_APPLICATION, LibraryClasses.Common.SMM_CORE] > + TimerLib | > OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf > + QemuFwCfgLib | > OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf > + MemEncryptSevLib | > OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEncryptSevLib.inf > + MemEncryptTdxLib | > OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEncryptTdxLibNull.inf > + Tcg2PhysicalPresenceLib | > OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeTcg2PhysicalPresenceLib.in= f > + ResetSystemLib | > OvmfPkg/Library/ResetSystemLib/DxeResetSystemLib.inf > + > +[LibraryClasses.Common.SEC] > + DebugLib | > OvmfPkg/Library/PlatformDebugLibIoPort/PlatformRomDebugLibIoPort.inf > + > +[Components.$(DXE_ARCH)] > + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf > + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > + OvmfPkg/SataControllerDxe/SataControllerDxe.inf > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf > + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf > + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf > diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf > b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf > new file mode 100644 > index 000000000000..2f39ce3860f6 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf > @@ -0,0 +1,313 @@ > +## @file > +# QemuOpenBoardPkg.fdf > +# > +# Copyright (c) 2022 Th=C3=A9o Jehl > +# SPDX-License-Identifier: BSD-2-Clause-Patent > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D > 0xFF800000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D 0x800= 000 > + > +!include QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc > + > +[FD.QemuOpenBoardPkg] > + BaseAddress =3D 0xFF800000 > + Size =3D 0x800000 > + ErasePolarity =3D 1 > + BlockSize =3D 0x1000 > + NumBlocks =3D 0x800 > + > + # > + # Do not modify this block > + # These three areas are tightly coupled and should be modified with > utmost care. > + # The total size must match the size in the EFI_FIRMWARE_VOLUME_HEADER > in NvStorage512K.fdf. > + # The NvStorageVariableSize must also match the VARIABLE_STORE_HEADER > size in NvStorage512K.fdf. > + # The EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER in > CommonNvStorageFtwWorking.fdf doesn't have size info. > + # > + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset | > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > + !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf > + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset | > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > + !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf > + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset | > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as > Base/Size to be written > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize > + FV =3D FvAdvanced > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize > + FV =3D FvSecurity > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize > + FV =3D FvOsBoot > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize > + FV =3D FvUefiBoot > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize > + FV =3D FvBsp > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize > + FV =3D FvPostMemory > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize > + FV =3D FvFspS > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize > + FV =3D FvFspM > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize > + FV =3D FvFspT > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize > + FV =3D FvBspPreMemory > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset | > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize > + FV =3D FvPreMemory > + > +########################### > +# > +# Stage 1 Firmware Volumes > +# > +########################### > + > +[FV.FvPreMemory] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D BD479C6B-2EFF-401F-A7F1-566347B41D07 > + > + FILE FV_IMAGE =3D 618FBA00-2231-41F6-9931-25A89DF501D3 { > + SECTION FV_IMAGE =3D FvSecurityPreMemory > + } > + > + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf > + > + INF > MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterP= ei.inf > + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf > + > + INF > MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf > + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf > + > + INF UefiCpuPkg/SecCore/SecCore.inf > + > +[FV.FvSecurityPreMemory] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D F626B0FB-D759-44A8-B131-42408BB3533D > + > +[FV.FvBspPreMemory] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D 5CF9C072-385F-44FC-B21B-002074251C08 > + > + INF > MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf > + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf > + INF QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf > + > + FILE FV_IMAGE =3D 90B948EA-FF73-4689-B90A-A54F86C1FC01 { > + SECTION FV_IMAGE =3D FvAdvancedPreMemory > + } > + > +[FV.FvAdvancedPreMemory] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D 43528CE0-812B-4074-B77E-C49E7A2F4FE1 > + > +[FV.FvFspT] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D 958CAF39-0B6C-40F1-B190-EC91C536CFF9 > + > +[FV.FvFspM] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D 03982cf7-246a-4356-b6ba-436a2251595c > + > + INF MdeModulePkg/Core/Pei/PeiMain.inf > + > + FILE FV_IMAGE =3D 83B39C64-BFB9-42EC-A7A3-527854A5C4C3 { > + SECTION FV_IMAGE =3D FvPreMemorySilicon > + } > + > +[FV.FvPreMemorySilicon] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D F0205C0E-0AD1-499C-A5F9-96BAF98248A0 > + > + INF > MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf > + > + !if $(SMM_REQUIRED) =3D=3D TRUE > + INF OvmfPkg/SmmAccess/SmmAccessPei.inf > + !endif > + > +[FV.FvFspS] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D C6786443-AFCA-471B-A8FC-E8C330708F99 > + > +[FV.FvPostMemorySilicon] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D EF76DFDC-2B7D-423D-BFE4-8FD4BB22E770 > + > +########################### > +# > +# Stage 2 Firmware Volumes > +# > +########################### > +[FV.FvPostMemory] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D 5A1D6978-BABE-42F9-A629-F7B3B6A1E1BD > + > + INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf > + > + INF > MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf > + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.in= f > + > + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > + > + INF > MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf > + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + > +[FV.FvBsp] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D FCA0BC4A-994D-4EF9-BD56-A8C45872C2A8 > + > +########################### > +# > +# Stage 3 Firmware Volumes > +# > +########################### > + > +[FV.FvUefiBootUnCompressed] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D D2F110DB-2388-4963-BEFD-5889EEE01569 > + > + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf > + > + INF > MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCode= RouterRuntimeDxe.inf > + INF > MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRunt= imeDxe.inf > + > + INF MdeModulePkg/Universal/Metronome/Metronome.inf > + INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf > + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf > + INF UefiCpuPkg/CpuDxe/CpuDxe.inf > + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf > + INF > PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.in= f > + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf > + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf > + INF > MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntime= Dxe.inf > + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf > + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf > + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf > + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf > + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf > + > + INF OvmfPkg/IoMmuDxe/IoMmuDxe.inf > + INF OvmfPkg/PlatformDxe/Platform.inf > + > + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > + INF > MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf > + INF > MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf > + INF > MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf > + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf > + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf > + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf > + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf > + > + INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf > + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf > + INF ShellPkg/Application/Shell/Shell.inf > + > + INF OvmfPkg/SioBusDxe/SioBusDxe.inf > + INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf > + INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf > + > + > +[FV.FvUefiBoot] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D D0C15ADB-FE38-4331-841C-0E96C1B0FBFA > + > + INF MdeModulePkg/Core/Dxe/DxeMain.inf > + > + FILE FV_IMAGE =3D D2F110DB-2388-4963-BEFD-5889EEE01569 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + SECTION FV_IMAGE =3D FvUefiBootUncompressed > + } > + } > + > + > +########################### > +# > +# Stage 4 Firmware Volumes > +# > +########################### > +[FV.FvOsBoot] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D AE8F0EA0-1614-422D-ABC1-C518596F1678 > + > + INF OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf > + > + INF PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf > + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf > + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf > + INF FatPkg/EnhancedFatDxe/Fat.inf > + > + INF MdeModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf > + INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf > + > + # ACPI > + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf > + INF OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf > + > + # Buses > + > + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf > + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf > + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf > + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf > + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf > + > + INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf > + INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > + > + INF OvmfPkg/SataControllerDxe/SataControllerDxe.inf > + > + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + > + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + > + !if $(SMM_REQUIRED) =3D=3D TRUE > + INF OvmfPkg/SmmAccess/SmmAccess2Dxe.inf > + INF OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf > + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf > + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf > + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf > + INF > MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterS= mm.inf > + INF > MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf > + INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf > + INF > MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf > + INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.i= nf > + !endif > + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf > + INF OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf > + > + > +########################### > +# > +# Stage 5 Firmware Volumes > +# > +########################### > +[FV.FvSecurity] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D 1AE6AB90-9431-425B-9A92-ED2708A4E982 > + !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf > + !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf > + > + > +########################### > +# > +# Stage 6 Firmware Volumes > +# > +########################### > +[FV.FvAdvanced] > + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf > + FvNameGuid =3D 936D6D65-CB6C-4B87-A51C-70D56511CB55 > + > +########################### > +# > +# File Construction Rules > +# > +########################### > +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootMan= agerLib.inf > b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootMan= agerLib.inf > new file mode 100644 > index 000000000000..37425d711010 > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootMan= agerLib.inf > @@ -0,0 +1,39 @@ > +## @file > +# The module definition file for BoardBootManagerLib. > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D BoardBootManagerLib > + FILE_GUID =3D 3fe4b589-8bd9-46df-9322-d06fa2c278d= 6 > + MODULE_TYPE =3D DXE_DRIVER > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D BoardBootManagerLib|DXE_DRIVER > + > + > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 X64 EBC > +# > + > +[Sources] > + BoardBootManager.c > + > +[LibraryClasses] > + BaseLib > + UefiBootServicesTableLib > + DebugLib > + UefiLib > + HobLib > + UefiBootManagerLib > + TimerLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.inf > b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.inf > new file mode 100644 > index 000000000000..8f75d1277070 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.in= f > @@ -0,0 +1,29 @@ > +## @file > +# QemuOpenBoardPkg BoardInitLib instance > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D BoardInitLib > + FILE_GUID =3D 70EE7BD9-08FF-4D0E-AA7B-4320844F939= A > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D BoardInitLib > + > +[Sources] > + BoardInitLib.c > + > +[Packages] > + QemuOpenBoardPkg/QemuOpenBoardPkg.dec > + MdePkg/MdePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + OvmfPkg/OvmfPkg.dec > + > +[LibraryClasses] > + DebugLib > + PcdLib > + IoLib > + PciCf8Lib > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLi= b.inf > b/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLi= b.inf > new file mode 100644 > index 000000000000..cfabf412d5bb > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLi= b.inf > @@ -0,0 +1,23 @@ > +## @file > +# OpenQemuFwCfgLib.inf > +# > +# Simple implementation of the QemuFwCfgLib that reads data from the QE= MU > +# FW_CFG device > +# > +# Copyright (c) 2022 Th=C3=A9o Jehl > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > Please explain what FwCfg is and how it works here in the .inf and in the .h. > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D QemuFwCfgLib > + FILE_GUID =3D 70EE7BD9-08FF-4D0E-AA7B-4320844F939= A > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D OpenQemuFwCfgLib > + > +[Sources] > + OpenQemuFwCfgLib.c > + > +[LibraryClasses] > + IoLib > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.in= f > b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.in= f > new file mode 100644 > index 000000000000..d416f1c64061 > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.in= f > @@ -0,0 +1,63 @@ > +### @file > +# Component information file for the Report Firmware Volume (FV) library= . > +# > +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +### > + > +[Defines] > + INF_VERSION =3D 0x00010017 > + BASE_NAME =3D PeiReportFvLib > + FILE_GUID =3D 44328FA5-E4DD-4A15-ABDF-C6584AC363D= 9 > + VERSION_STRING =3D 1.0 > + MODULE_TYPE =3D PEIM > + LIBRARY_CLASS =3D ReportFvLib > + > +[LibraryClasses] > + BaseMemoryLib > + DebugLib > + HobLib > + PeiServicesLib > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + QemuOpenBoardPkg/QemuOpenBoardPkg.dec > + > +[Sources] > + PeiReportFvLib.c > + > +[Pcd] > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase ## > CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset ## > CONSUMES > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.in= f > b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.in= f > new file mode 100644 > index 000000000000..a4c793af05cd > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.in= f > @@ -0,0 +1,49 @@ > +## @file > +# PlatformSecLib for QEMU OpenBoardPkg > +# > +# Copyright (c) 2022 Th=C3=A9o Jehl > +# SPDX-License-Identifier: BSD-2-Clause-Patent > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PlatformSecLib > + FILE_GUID =3D 37b1bddc-5a53-4f2a-af7d-b78d5e80dcb= d > + MODULE_TYPE =3D SEC > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D PlatformSecLib > + > +# > +# The following information is for reference only and not required by th= e > build tools. > +# > +# VALID_ARCHITECTURES =3D IA32 > +# > + > +[Sources.IA32] > + Ia32/SecEntry.nasm > + > +[Sources] > + PlatformSecLib.c > + > +[LibraryClasses] > + DebugLib > + BaseLib > + BaseMemoryLib > + PciLib > + PcdLib > + HobLib > + MtrrLib > + > +[Packages] > + MdePkg/MdePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + QemuOpenBoardPkg/QemuOpenBoardPkg.dec > + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec > + MinPlatformPkg/MinPlatformPkg.dec > + > +[Ppis] > + gTopOfTemporaryRamPpiGuid > + > +[Pcd] > + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase > + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf > b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf > new file mode 100644 > index 000000000000..c800d14a02b5 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf > @@ -0,0 +1,59 @@ > +## @file > +# PlatformInitPei > +# > +# Simple PEIM for QEMU PIIX4/Q35 Memory, SMP and PCI/PCI Express > initialization > +# > +# Copyright (c) 2022 Th=C3=A9o Jehl > +# SPDX-License-Identifier: BSD-2-Clause-Patent > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PlatformInitPei > + FILE_GUID =3D 82d851fe-3106-4175-8b6c-87fda1f2d0a= c > + MODULE_TYPE =3D PEIM > + VERSION_STRING =3D 1.0 > + ENTRY_POINT =3D PlatformInit > + > +[Packages] > + OvmfPkg/OvmfPkg.dec > + MdePkg/MdePkg.dec > + QemuOpenBoardPkg/QemuOpenBoardPkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + > +[Sources] > + PlatformInit.h > + PlatformInit.c > + Memory.c > + Pcie.c > + Pci.c > + Cpu.c > + > +[LibraryClasses] > + PeimEntryPoint > + OpenQemuFwCfgLib > + HobLib > + PcdLib > + PciLib > + > +[Guids] > + gUefiOvmfPkgPlatformInfoGuid > + > +[Pcd] > + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber > + gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber > + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase > + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize > + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base > + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size > + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base > + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes > + > +[FeaturePcd] > + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire > + > +[Depex] > + TRUE > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Include/Library/OpenQemuFwCfgLib.h > b/Platform/Qemu/QemuOpenBoardPkg/Include/Library/OpenQemuFwCfgLib.h > new file mode 100644 > index 000000000000..ec82cc9c89f0 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Library/OpenQemuFwCfgLib.h > @@ -0,0 +1,102 @@ > +/** @file OpenQemuFwCfgLib.h > + OpenQemuFwCfgLib Headers > + > + Implements a minimal library to interact with Qemu FW CFG device > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > + > +#ifndef QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_ > +#define QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_ > + > +#include > +#include > + > +// QEMU fw_cfg registers > +#define FW_CFG_PORT_SEL 0x510 > +#define FW_CFG_PORT_DATA 0x511 > +#define FW_CFG_PORT_DMA 0x514 > + > +// QEMU Selectors > +#define FW_CFG_SIGNATURE 0x0000 > +#define FW_CFG_ID 0x0001 > +#define FW_CFG_FILE_DIR 0x0019 > + > +#define FW_CFG_QEMU_SIGNATURE SIGNATURE_32('Q', 'E', 'M', 'U') > + > +typedef struct { > + UINT32 Size; > + UINT16 Select; > + UINT16 Reserved; > + CHAR8 Name[56]; > +} QEMU_FW_CFG_FILE; > + > +/** > + Checks for Qemu fw_cfg device by reading "QEMU" using the signature > selector > + > + @return EFI_SUCCESS - The fw_cfg device is present > + @return EFI_UNSUPPORTED - The device is absent > + */ > +EFI_STATUS > +EFIAPI > +QemuFwCfgIsPresent ( > + VOID > + ); > + > +/** > + Sets the selector register to the specified value > + > + @param[in] Selector > + > + @return EFI_SUCCESS > + @return EFI_UNSUPPORTED > + */ > +EFI_STATUS > +EFIAPI > +QemuFwCfgSelectItem ( > + IN UINT16 Selector > + ); > + > +/** > + Reads 8 bits from the data register > + > + @return UINT8 > + */ > +UINT8 > +EFIAPI > +QemuFwCfgRead8 ( > + VOID > + ); > + > +/** > + Reads N bytes from the data register > + > + @param Size > + @param Buffer > + */ > +VOID > +EFIAPI > +QemuFwCfgReadBytes ( > + IN UINTN Size, > + OUT VOID *Buffer > + ); > + > +/** > + Finds a file in fw_cfg by its name > + > + @param[in] String Pointer to an ASCII string to match in the database > + @param[out] FWConfigFile Buffer for the config file > + > + @return EFI_STATUS - Entry was found, FWConfigFile is populated > + @return EFI_ERROR - Entry was not found > + */ > +EFI_STATUS > +EFIAPI > +QemuFwCfgFindFile ( > + IN CHAR8 *String, > + OUT QEMU_FW_CFG_FILE *FWConfigFile > + ); > + > +#endif // QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_ > diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.= h > b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h > new file mode 100644 > index 000000000000..7f84e5d9724b > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h > @@ -0,0 +1,59 @@ > +/** @file PlatformInit.h > + Headers for PlatformInitPei PEIM > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_ > +#define QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_ > + > +#include > +#include > + > +#define PIIX4_PCI_IO_BASE 0xC000 > +#define PIIX4_PCI_IO_SIZE 0x4000 > + > +#define Q35_PCI_IO_BASE 0x6000 > +#define Q35_PCI_IO_SIZE 0xA000 > + > +#define PCI_MMIO_TOP_ADDRESS 0xFC000000 > + > +EFI_STATUS > +EFIAPI > +PlatformInit ( > + IN EFI_PEI_FILE_HANDLE FileHandle, > + IN CONST EFI_PEI_SERVICES **PeiServices > + ); > + > +UINT32 > +EFIAPI > +GetMemoryBelow4Gb ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +InstallMemory ( > + IN CONST EFI_PEI_SERVICES **PeiServices > + ); > + > +EFI_STATUS > +EFIAPI > +InitializePcie ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +InitializePciPIIX4 ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +MaxCpuInit ( > + VOID > + ); > + > +#endif //QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_ > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootMan= ager.c > b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootMan= ager.c > new file mode 100644 > index 000000000000..9fad6bc56dfd > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootMan= ager.c > @@ -0,0 +1,105 @@ > +/** @file > + This file include board specific boot manager callbacks > + > + Copyright (c) 2019, Intel Corporation. All rights reserved.
> + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +BOOLEAN mHotKeypressed =3D FALSE; > +EFI_EVENT HotKeyEvent =3D NULL; > +UINTN mBootMenuOptionNumber; > + > +/** > + This function is called each second during the boot manager waits > timeout. > + > + @param TimeoutRemain The remaining timeout. > +**/ > +VOID > +EFIAPI > +BoardBootManagerWaitCallback ( > + UINT16 TimeoutRemain > + ) > +{ > + EFI_STATUS Status; > + EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *TxtInEx; > + EFI_KEY_DATA KeyData; > + BOOLEAN PausePressed; > + > + // > + // Pause on PAUSE key > + // > + Status =3D gBS->HandleProtocol (gST->ConsoleInHandle, > &gEfiSimpleTextInputExProtocolGuid, (VOID **)&TxtInEx); > + ASSERT_EFI_ERROR (Status); > + > + PausePressed =3D FALSE; > + > + while (TRUE) { > + Status =3D TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData); > + if (EFI_ERROR (Status)) { > + break; > + } > + > + if (KeyData.Key.ScanCode =3D=3D SCAN_PAUSE) { > + PausePressed =3D TRUE; > + break; > + } > + } > + > + // > + // Loop until non-PAUSE key pressed > + // > + while (PausePressed) { > + Status =3D TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData); > + if (!EFI_ERROR (Status)) { > + DEBUG ( > + ( > + DEBUG_INFO, "[PauseCallback] %x/%x %x/%x\n", > + KeyData.Key.ScanCode, KeyData.Key.UnicodeChar, > + KeyData.KeyState.KeyShiftState, > KeyData.KeyState.KeyToggleState > + ) > + ); > + PausePressed =3D (BOOLEAN)(KeyData.Key.ScanCode =3D=3D SCAN_PAUSE)= ; > + } > + } > +} > + > +/** > + The function is called when no boot option could be launched, > + including platform recovery options and options pointing to applicatio= ns > + built into firmware volumes. > + > + If this function returns, BDS attempts to enter an infinite loop. > +**/ > +VOID > +EFIAPI > +BoardBootManagerUnableToBoot ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + EFI_BOOT_MANAGER_LOAD_OPTION BootDeviceList; > + CHAR16 OptionName[sizeof ("Boot####")]; > + > + if (mBootMenuOptionNumber =3D=3D LoadOptionNumberUnassigned) { > + return; > + } > + > + UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", > mBootMenuOptionNumber); > + Status =3D EfiBootManagerVariableToLoadOption (OptionName, > &BootDeviceList); > + if (EFI_ERROR (Status)) { > + return; > + } > + > + for ( ;;) { > + EfiBootManagerBoot (&BootDeviceList); > + } > +} > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c > b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c > new file mode 100644 > index 000000000000..ae7c77915b5e > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c > @@ -0,0 +1,222 @@ > +/** @file > + Board initialization library > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define QEMU_IO_DEBUG_MAGIC 0xE9 > + > +/** > + This board service detects the board type. > + > + @retval EFI_SUCCESS The board was detected successfully. > + @retval EFI_NOT_FOUND The board could not be detected. > +**/ > +EFI_STATUS > +EFIAPI > +BoardDetect ( > + VOID > + ) > +{ > + UINT16 DeviceID, VendorID; > + > + DEBUG ((DEBUG_INFO, "BoardDetect()\n")); > + > + DeviceID =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, > PCI_DEVICE_ID_OFFSET)); > + VendorID =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, > PCI_VENDOR_ID_OFFSET)); > + > Please add a comment explaining what you're doing here. > + switch (DeviceID) { > + case INTEL_82441_DEVICE_ID: > + DEBUG ((DEBUG_INFO, "PIIX4\n")); > + return EFI_SUCCESS; > + > + case INTEL_Q35_MCH_DEVICE_ID: > + DEBUG ((DEBUG_INFO, "ICH9\n")); > + return EFI_SUCCESS; > + > Possibly edit these DEBUG such that they're not just stray chipset names in the log. > + default: > + DEBUG ((DEBUG_ERROR, "Unable to detect board (Device id %u Vendor > ID %u)\n", DeviceID, VendorID)); > + return EFI_NOT_FOUND; > + } > +} > + > +/** > + This board service initializes board-specific debug devices. > + > + @retval EFI_SUCCESS Board-specific debug initialization was > successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardDebugInit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_BOOT_MODE > +EFIAPI > +BoardBootModeDetect ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardBootModeDetect()\n")); > + return BOOT_WITH_FULL_CONFIGURATION; > +} > + > +/** > + A hook for board-specific initialization prior to memory initializatio= n. > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitBeforeMemoryInit ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitBeforeMemoryInit()\n")); > + return EFI_SUCCESS; > +} > + > +/** > + A hook for board-specific initialization after memory initialization. > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitAfterMemoryInit ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitAfterMemoryInit()\n")); > + return EFI_SUCCESS; > +} > + > +/** > + A hook for board-specific initialization prior to disabling temporary > RAM. > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitBeforeTempRamExit ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitBeforeTempRamExit()\n")); > + return EFI_SUCCESS; > +} > + > +/** > + A hook for board-specific initialization after disabling temporary RAM= . > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitAfterTempRamExit ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitAfterTempRamExit()\n")); > + return EFI_SUCCESS; > +} > + > +/** > + A hook for board-specific initialization prior to silicon > initialization. > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitBeforeSiliconInit ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitBeforeSiliconInit()\n")); > + return EFI_SUCCESS; > +} > + > +/** > + A hook for board-specific initialization after silicon initialization. > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitAfterSiliconInit ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitAfterSiliconInit()\n")); > + return EFI_SUCCESS; > +} > + > +/** > + A hook for board-specific initialization after PCI enumeration. > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitAfterPciEnumeration ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitAfterPciEnumeration()\n")); > + return EFI_SUCCESS; > +} > + > +/** > + A hook for board-specific functionality for the ReadyToBoot event. > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitReadyToBoot ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitReadyToBoot()\n")); > + return EFI_SUCCESS; > +} > + > +/** > + A hook for board-specific functionality for the ExitBootServices event= . > + > + @retval EFI_SUCCESS The board initialization was successful. > + @retval EFI_NOT_READY The board has not been detected yet. > +**/ > +EFI_STATUS > +EFIAPI > +BoardInitEndOfFirmware ( > + VOID > + ) > +{ > + DEBUG ((DEBUG_INFO, "BoardInitEndOfFirmware()\n")); > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLi= b.c > b/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLi= b.c > Why is this path .../OpenQemuFwCfgLib when the package is called QemuOpenBoardPkg? > new file mode 100644 > index 000000000000..c02c263f03b3 > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfgLi= b.c > @@ -0,0 +1,130 @@ > +/** @file > + Qemu FW CFG device library > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > + > +/** > + Reads 8 bits from the data register > + > + @retval UINT8 > +**/ > +UINT8 > +EFIAPI > +QemuFwCfgRead8 ( > + VOID > + ) > +{ > + return IoRead8 (FW_CFG_PORT_DATA); > +} > + > +/** > + Sets the selector register to the specified value > + > + @param Selector > + > + @retval EFI_SUCCESS > + @retval EFI_UNSUPPORTED > +**/ > +EFI_STATUS > +EFIAPI > +QemuFwCfgSelectItem ( > + IN UINT16 Selector > + ) > +{ > + UINT16 WritenSelector; > + > + WritenSelector =3D IoWrite16 (FW_CFG_PORT_SEL, Selector); > + > + if (WritenSelector !=3D Selector) { > + return EFI_UNSUPPORTED; > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Reads N bytes from the data register > + > + @param Size > + @param Buffer > +**/ > +VOID > +EFIAPI > +QemuFwCfgReadBytes ( > + IN UINTN Size, > + OUT VOID *Buffer > + ) > +{ > + IoReadFifo8 (FW_CFG_PORT_DATA, Size, Buffer); > +} > + > +/** > + Checks for Qemu fw_cfg device by reading "QEMU" using the signature > selector > + > + @retval EFI_SUCCESS - The fw_cfg device is present > + @retval EFI_UNSUPPORTED - The device is absent > +**/ > +EFI_STATUS > +EFIAPI > +QemuFwCfgIsPresent ( > + ) > +{ > + EFI_STATUS Status; > + UINT32 Control; > + > + Status =3D QemuFwCfgSelectItem (FW_CFG_SIGNATURE); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + QemuFwCfgReadBytes (4, &Control); > + if (Control !=3D FW_CFG_QEMU_SIGNATURE) { > + ASSERT (Control =3D=3D FW_CFG_QEMU_SIGNATURE); > + return EFI_UNSUPPORTED; > + } > + > + return EFI_SUCCESS; > +} > + > +/** > + Finds a file in fw_cfg by its name > + > + @param String Pointer to an ASCII string to match in the database > + @param FWConfigFile Buffer for the config file > + @retval EFI_STATUS - Entry was found, FWConfigFile is populated > + @retval EFI_ERROR - Entry was not found > +**/ > +EFI_STATUS > +EFIAPI > +QemuFwCfgFindFile ( > + IN CHAR8 *String, > + OUT QEMU_FW_CFG_FILE *FWConfigFile > + ) > +{ > + QEMU_FW_CFG_FILE FirmwareConfigFile; > + UINT32 FilesCount; > + UINT32 Idx; > + > + QemuFwCfgSelectItem (FW_CFG_FILE_DIR); > + QemuFwCfgReadBytes (sizeof (UINT32), &FilesCount); > + > + FilesCount =3D SwapBytes32 (FilesCount); > + > + for (Idx =3D 0; Idx < FilesCount; Idx++) { > + QemuFwCfgReadBytes (sizeof (QEMU_FW_CFG_FILE), &FirmwareConfigFile); > + if (AsciiStrCmp ((CHAR8 *)&(FirmwareConfigFile.Name), String) =3D=3D= 0) { > + FirmwareConfigFile.Select =3D SwapBytes16 (FirmwareConfigFile.Sele= ct); > + FirmwareConfigFile.Size =3D SwapBytes32 (FirmwareConfigFile.Size= ); > + CopyMem (FWConfigFile, &FirmwareConfigFile, sizeof > (QEMU_FW_CFG_FILE)); > + return EFI_SUCCESS; > + } > + } > + > + return EFI_UNSUPPORTED; > +} > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c > b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c > new file mode 100644 > index 000000000000..809e69ce4381 > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c > @@ -0,0 +1,285 @@ > +/** @file PeiReportFvLib.c > + Source code file for Report Firmware Volume (FV) library > + > + Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +// Use a FV pointer PCD to get a pointer to the FileSystemGuid in the FV > header > +#define PCD_TO_FV_HEADER_FILE_SYSTEM_GUID(Pcd) > (&((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN) PcdGet32 (Pcd))->FileSystemGuid= ) > + > +/** > + Reports FVs necessary for MinPlarform pre-memory initialization > + */ > +VOID > +ReportPreMemFv ( > + VOID > + ) > +{ > + UINTN Index =3D 0; > + EFI_PEI_PPI_DESCRIPTOR *Descriptor =3D NULL; > + EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *Ppi =3D NULL; > + EFI_STATUS Status =3D EFI_SUCCESS; > + EFI_FIRMWARE_VOLUME_HEADER *FvHeader =3D NULL; > + EFI_BOOT_MODE BootMode =3D > BOOT_WITH_FULL_CONFIGURATION; > + > + Status =3D PeiServicesGetBootMode (&BootMode); > + ASSERT_EFI_ERROR (Status); > + > + DEBUG_CODE ( > + for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) { > + Status =3D PeiServicesLocatePpi (&gEfiPeiFirmwareVolumeInfo2PpiGui= d, > Index, &Descriptor, (VOID**) &Ppi); > + if (!EFI_ERROR (Status)) { > + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi->FvInfo; > + DEBUG ((DEBUG_INFO, "Found FV at 0x%x, size 0x%x\n", FvHeader, > FvHeader->FvLength)); > + } > + } > + ); > + > + // > + // FvBspPreMemory and FvPreMemory are required for all stages. > + // > + > + DEBUG ((DEBUG_INFO, "Install FlashFvBspPreMemory - 0x%x, 0x%x\n", > PcdGet32 (PcdFlashFvBspPreMemoryBase), PcdGet32 > (PcdFlashFvBspPreMemorySize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvBspPreMemoryBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvBspPreMemoryBase), > + PcdGet32 (PcdFlashFvBspPreMemorySize), > + NULL, > + NULL, > + 0 > + ); > + > + DEBUG ((DEBUG_INFO, "Install FlashFvPreMemory - 0x%x, 0x%x\n", PcdGet3= 2 > (PcdFlashFvPreMemoryBase), PcdGet32 (PcdFlashFvPreMemorySize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvPreMemoryBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvPreMemoryBase), > + PcdGet32 (PcdFlashFvPreMemorySize), > + NULL, > + NULL, > + 0 > + ); > + > + // > + // In API mode, do not publish FSP FV. > + // > + if (!PcdGetBool (PcdFspWrapperBootMode)) { > + // > + // FvFspT may be required for all stages > + // > + DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvFspTBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvFspTBase), > + PcdGet32 (PcdFlashFvFspTSize), > + NULL, > + NULL, > + 0 > + ); > + > + // > + // FvFspM required for stage 2 and above > + // > + if (PcdGet8 (PcdBootStage) >=3D 2) { > + DEBUG ((DEBUG_INFO, "Install FlashFvFspM - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvFspMBase), PcdGet32 (PcdFlashFvFspMSize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvFspMBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvFspMBase), > + PcdGet32 (PcdFlashFvFspMSize), > + NULL, > + NULL, > + 0 > + ); > + } > + } > + > + // > + // FvAdvanced not needed until stage 6 > + // > + if (PcdGet8 (PcdBootStage) >=3D 6) { > + DEBUG ((DEBUG_INFO, "Install FlashFvAdvancedPreMemory - 0x%x, > 0x%x\n", PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), PcdGet32 > (PcdFlashFvAdvancedPreMemorySize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvAdvancedPreMemoryBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvAdvancedPreMemoryBase), > + PcdGet32 > (PcdFlashFvAdvancedPreMemorySize), > + NULL, > + NULL, > + 0 > + ); > + } > +} > +/** > + Reports FVs for MinPlarform post-memory initialization > + This function also publish FV HOBs to ensure DXE phase is aware of > those FVs > + */ > +VOID > +ReportPostMemFv ( > + VOID > + ) > +{ > + UINTN Index =3D 0; > + EFI_PEI_PPI_DESCRIPTOR *Descriptor =3D NULL; > + EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *Ppi =3D NULL; > + EFI_STATUS Status =3D EFI_SUCCESS; > + EFI_FIRMWARE_VOLUME_HEADER *FvHeader =3D NULL; > + > + DEBUG_CODE ( > + for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) { > + Status =3D PeiServicesLocatePpi (&gEfiPeiFirmwareVolumeInfo2PpiGui= d, > Index, &Descriptor, (VOID**) &Ppi); > + if (!EFI_ERROR (Status)) { > + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi->FvInfo; > + DEBUG ((DEBUG_INFO, "Found FV at 0x%x, size 0x%x\n", FvHeader, > FvHeader->FvLength)); > + } > + } > + ); > + > + // > + // FvFspS, FvPostMemory, and FvBsp may be required for completing stag= e > 2 > + // > + if (PcdGet8 (PcdBootStage) >=3D 2) { > + // > + // In API mode, do not publish FSP FV. > + // > + if (!PcdGetBool (PcdFspWrapperBootMode)) { > + DEBUG ((DEBUG_INFO, "Install FlashFvFspS - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvFspSBase), PcdGet32 (PcdFlashFvFspSSize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvFspSBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvFspSBase), > + PcdGet32 (PcdFlashFvFspSSize), > + NULL, > + NULL, > + 0 > + ); > + } > + > + DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", > PcdGet32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize))= ); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvPostMemoryBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvPostMemoryBase), > + PcdGet32 (PcdFlashFvPostMemorySize), > + NULL, > + NULL, > + 0 > + ); > + > + DEBUG ((DEBUG_INFO, "%Build FlashFvPostMemory FV Hob at %Lx \n", > (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvPostMemoryBase))); > + > + BuildFvHob ( > + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvPostMemoryBase= ), > + PcdGet32 (PcdFlashFvPostMemorySize) > + ); > + > + DEBUG ((DEBUG_INFO, "Install FlashFvBsp - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvBspBase), PcdGet32 (PcdFlashFvBspSize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvBspBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvBspBase), > + PcdGet32 (PcdFlashFvBspSize), > + NULL, > + NULL, > + 0 > + ); > + } > + > + // > + // FvUefiBoot required for completing stage 3 > + // > + if (PcdGet8 (PcdBootStage) >=3D 3) { > + DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", > PcdGet32 (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvUefiBootBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvUefiBootBase), > + PcdGet32 (PcdFlashFvUefiBootSize), > + NULL, > + NULL, > + 0 > + ); > + > + DEBUG ((DEBUG_INFO, "%Build FlashFvUefiBoot FV Hob at %Lx \n", > (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvUefiBootBase))); > + > + BuildFvHob ( > + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvUefiBootBase), > + PcdGet32 (PcdFlashFvUefiBootSize) > + ); > + } > + > + // > + // FvOsBoot required for completing stage 4 > + // > + if (PcdGet8 (PcdBootStage) >=3D 4) { > + DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x\n", PcdGet32 > (PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvOsBootBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvOsBootBase), > + PcdGet32 (PcdFlashFvOsBootSize), > + NULL, > + NULL, > + 0 > + ); > + > + DEBUG ((DEBUG_INFO, "%Build FlashFvOsBoot FV Hob at %Lx \n", > (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvUefiBootBase))); > + > + BuildFvHob ( > + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvOsBootBase), > + PcdGet32 (PcdFlashFvOsBootSize) > + ); > + } > + > + // > + // FvSecurity required for completing stage 5 > + // > + if (PcdGet8 (PcdBootStage) >=3D 5) { > + DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", > PcdGet32 (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvSecurityBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvSecurityBase), > + PcdGet32 (PcdFlashFvSecuritySize), > + NULL, > + NULL, > + 0 > + ); > + } > + > + // > + // FvAdvanced required for completing stage 6 > + // > + if (PcdGet8 (PcdBootStage) >=3D 6) { > + DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x%x\n", > PcdGet32 (PcdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvancedSize))); > + PeiServicesInstallFvInfo2Ppi ( > + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID > (PcdFlashFvAdvancedBase), > + (VOID *)(UINTN)PcdGet32 > (PcdFlashFvAdvancedBase), > + PcdGet32 (PcdFlashFvAdvancedSize), > + NULL, > + NULL, > + 0 > + ); > + } > + > + // > + // Report resource related HOB for flash FV to reserve space in GCD an= d > memory map > + // > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_MEMORY_MAPPED_IO, > + (EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), > + (UINTN)PcdGet32 (PcdFlashAreaBaseAddress), > + (UINTN)PcdGet32 (PcdFlashAreaSize) > + ); > + > + BuildMemoryAllocationHob ( > + (UINTN)PcdGet32 (PcdFlashAreaBaseAddress), > + (UINTN)PcdGet32 (PcdFlashAreaSize), > + EfiMemoryMappedIO > + ); > +} > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.c > b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.c > new file mode 100644 > index 000000000000..ff632494c4a3 > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.c > @@ -0,0 +1,140 @@ > +/** @file > + PlatformSecLib library functions > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +EFI_PEI_CORE_FV_LOCATION_PPI gEfiPeiCoreFvLocationPpi =3D { > + (VOID *)FixedPcdGet32 (PcdFlashFvFspMBase) > +}; > + > +STATIC EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D { > + // > + // This must be the second PPI in the list because it will be patched > in SecPlatformMain (); > + // > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, > + &gTopOfTemporaryRamPpiGuid, > + NULL > + } > +}; > + > +EFI_PEI_PPI_DESCRIPTOR gEfiPeiCoreFvLocationDescriptor =3D { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gEfiPeiCoreFvLocationPpiGuid, > + &gEfiPeiCoreFvLocationPpi > +}; > + > +EFI_PEI_PPI_DESCRIPTOR * > +EFIAPI > +SecPlatformMain ( > + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData > + ) > +{ > + // Use half of available heap size for PpiList > + EFI_PEI_PPI_DESCRIPTOR *PpiList; > + > + PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + > (UINTN)SecCoreData->PeiTemporaryRamSize / 2); > + > + CopyMem (PpiList, &gEfiPeiCoreFvLocationDescriptor, sizeof > (EFI_PEI_PPI_DESCRIPTOR)); > + > + CopyMem (&PpiList[1], &mPeiSecPlatformPpi, sizeof > (EFI_PEI_PPI_DESCRIPTOR)); > + > + // Patch the top of RAM PPI > + PpiList[1].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase + > SecCoreData->TemporaryRamSize); > + DEBUG ((DEBUG_INFO, "SecPlatformMain(): Top of memory %p\n", > PpiList[1].Ppi)); > + > + return PpiList; > +} > + > +/** > + This interface conveys state information out of the Security (SEC) > phase into PEI. > + > + @param PeiServices Pointer to the PEI Services Table. > + @param StructureSize Pointer to the variable describing > size of the input buffer. > + @param PlatformInformationRecord Pointer to the > EFI_SEC_PLATFORM_INFORMATION_RECORD. > + > + @retval EFI_SUCCESS The data was successfully returned. > + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. > + > +**/ > +EFI_STATUS > +EFIAPI > +SecPlatformInformation ( > + IN CONST EFI_PEI_SERVICES **PeiServices, > + IN OUT UINT64 *StructureSize, > + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord > + ) > +{ > + UINT32 TopOfTemporaryRam; > + VOID *TopOfRamPpi; > + EFI_STATUS Status; > + UINT32 Count; > + UINT32 *BistStart; > + UINT32 Length; > + > + Status =3D (*PeiServices)->LocatePpi (PeiServices, > &gTopOfTemporaryRamPpiGuid, 0, NULL, &TopOfRamPpi); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + TopOfTemporaryRam =3D (UINT32)TopOfRamPpi; > + > + DEBUG ((DEBUG_INFO, "SecPlatformInformation: Top of memory is %p\n", > TopOfRamPpi)); > + > + Count =3D *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)); > + Length =3D Count * sizeof (UINT32); > + > + BistStart =3D (UINT32 *)(TopOfTemporaryRam - sizeof (UINT32) - Length)= ; > + > + DEBUG ((DEBUG_INFO, "SecPlatformInformation: Found %u processors with > BISTs starting at %p\n", Count, BistStart)); > + > + if (*StructureSize < Length) { > + *StructureSize =3D Length; > + return EFI_BUFFER_TOO_SMALL; > + } > + > + CopyMem (PlatformInformationRecord, BistStart, Length); > + *StructureSize =3D Length; > + > + // Mask the PIC to avoid any interruption down the line > + IoWrite8 (0x21, 0xff); > + IoWrite8 (0xA1, 0xff); > + > + DEBUG ((DEBUG_INFO, "Initialize APIC Timer \n")); > + InitializeApicTimer (0, MAX_UINT32, TRUE, 5); > + > + DEBUG ((DEBUG_INFO, "Disable APIC Timer interrupt\n")); > + DisableApicTimerInterrupt (); > + > + return EFI_SUCCESS; > +} > + > +/** > + This interface disables temporary memory in SEC Phase. > +**/ > +VOID > +EFIAPI > +SecPlatformDisableTemporaryMemory ( > + VOID > + ) > +{ > + return; > +} > diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c > b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c > new file mode 100644 > index 000000000000..ff3e008aa96b > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c > @@ -0,0 +1,56 @@ > +/** @file Cpu.c > + CPU Count initialization > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PlatformInit.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Probe Qemu FW CFG device for current CPU count and report to MpInitLib > + > + @return EFI_SUCCESS Detection was successful > + @retval EFI_UNSUPPORTED Qemu FW CFG device is not present > + */ > +EFI_STATUS > +EFIAPI > +MaxCpuInit ( > + VOID > + ) > +{ > + UINT16 BootCpuCount; > + EFI_STATUS Status; > + > + Status =3D QemuFwCfgIsPresent (); > + > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "QemuFwCfg not present, unable to detect CPU > count \n")); > + ASSERT_EFI_ERROR (Status); > + return EFI_UNSUPPORTED; > + } > + > + Status =3D QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount); > + > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + QemuFwCfgReadBytes (sizeof (BootCpuCount), &BootCpuCount); > + > + PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount); > + > + PcdSet32S (PcdCpuMaxLogicalProcessorNumber, 64); > + > + return EFI_SUCCESS; > +} > diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c > b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c > new file mode 100644 > index 000000000000..8e378c17d851 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c > @@ -0,0 +1,244 @@ > +/** @file Memory.c > + Memory probing and installation > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Return the memory size below 4GB. > + > + @return UINT32 > +**/ > +UINT32 > +EFIAPI > +GetMemoryBelow4Gb ( > + VOID > + ) > +{ > + EFI_E820_ENTRY64 E820Entry; > + QEMU_FW_CFG_FILE FwCfgFile; > + UINT32 Processed; > + UINT64 Size; > + EFI_STATUS Status; > + > + Status =3D QemuFwCfgIsPresent (); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgFile); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + Size =3D 0; > + QemuFwCfgSelectItem (FwCfgFile.Select); > + for (Processed =3D 0; Processed < FwCfgFile.Size / sizeof > (EFI_E820_ENTRY); Processed++) { > + QemuFwCfgReadBytes (sizeof (EFI_E820_ENTRY), &E820Entry); > + if (E820Entry.Type !=3D EfiAcpiAddressRangeMemory) { > + continue; > + } > + > + if (E820Entry.BaseAddr + E820Entry.Length < SIZE_4GB) { > + Size +=3D E820Entry.Length; > + } else { > + return Size; > + } > + } > + > + return Size; > +} > + > +/** > + Reserve an MMIO region > + > + @param Start > + @param Length > +**/ > +STATIC > +VOID > +ReserveMmioRegion ( > + EFI_PHYSICAL_ADDRESS Start, > + UINT64 Length > + ) > +{ > + EFI_RESOURCE_TYPE ResourceType; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + > + ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT | > EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | EFI_RESOURCE_ATTRIBUTE_TESTED; > + ResourceType =3D EFI_RESOURCE_MEMORY_MAPPED_IO; > + > + BuildResourceDescriptorHob ( > + ResourceType, > + ResourceAttributes, > + Start, > + Length > + ); > +} > + > +/** > + Install EFI memory by probing Qemu FW CFG devices for valid E820 entri= es > + It also reserve space for MMIO regions such as VGA, BIOS and APIC > + > + @param PeiServices > + @retval EFI_SUCCESS Memory initialization succeded > + @retval EFI_UNSUPPORTED Installation failed (etc/e820 file was not > found) > + @retval EFI_NOT_FOUND Qemu FW CFG device is not present > +**/ > +EFI_STATUS > +EFIAPI > +InstallMemory ( > + IN CONST EFI_PEI_SERVICES **PeiServices > + ) > +{ > + EFI_STATUS Status; > + CONST EFI_PEI_SERVICES **PeiServicesTable; > + EFI_E820_ENTRY64 E820Entry; > + EFI_E820_ENTRY64 LargestE820Entry; > + QEMU_FW_CFG_FILE FwCfgFile; > + UINT32 Processed; > + BOOLEAN ValidMemory; > + EFI_RESOURCE_TYPE ResourceType; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + UINT32 MemoryBelow4G; > + UINT32 RequiredBySmm; > + > + Status =3D QemuFwCfgIsPresent (); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_INFO, "QEMU fw_cfg device is not present\n")); > + return EFI_NOT_FOUND; > + } else { > + DEBUG ((DEBUG_INFO, "QEMU fw_cfg device is present\n")); > + } > + > + Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgFile); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "etc/e820 was not found \n")); > + return EFI_UNSUPPORTED; > + } > + > + MemoryBelow4G =3D GetMemoryBelow4Gb (); > + > + LargestE820Entry.Length =3D 0; > + QemuFwCfgSelectItem (FwCfgFile.Select); > + for (Processed =3D 0; Processed < FwCfgFile.Size / sizeof > (EFI_E820_ENTRY); Processed++) { > + QemuFwCfgReadBytes (sizeof (EFI_E820_ENTRY), &E820Entry); > + > + ValidMemory =3D E820Entry.Type =3D=3D EfiAcpiAddressRangeMemo= ry; > + ResourceType =3D EFI_RESOURCE_MEMORY_RESERVED; > + ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT | > EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | EFI_RESOURCE_ATTRIBUTE_TESTED; > + > + if (ValidMemory) { > + if (FeaturePcdGet (PcdSmmSmramRequire) && (E820Entry.BaseAddr + > E820Entry.Length =3D=3D MemoryBelow4G)) { > + RequiredBySmm =3D PcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; > + if (E820Entry.Length < RequiredBySmm) { > + DEBUG (( > + DEBUG_ERROR, > + "Error: There's not enough memory below TOLUD for SMM (%lx < > %x)\n", > + E820Entry.Length, > + RequiredBySmm > + )); > + } > + > + E820Entry.Length -=3D RequiredBySmm; > + DEBUG (( > + DEBUG_INFO, > + "SMM is enabled! Stealing [%lx, %lx](%u MiB) for SMRAM...\n", > + E820Entry.BaseAddr + E820Entry.Length, > + E820Entry.BaseAddr + E820Entry.Length + RequiredBySmm - 1, > + PcdGet16 (PcdQ35TsegMbytes) > + )); > + } > + > + ResourceType =3D EFI_RESOURCE_SYSTEM_MEMORY; > + ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABL= E > | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED; > + > + // > + // Lets handle the lower 1MB in a special way > + // > + > + if (E820Entry.BaseAddr =3D=3D 0) { > + // > + // 0 - 0xa0000 is system memory, everything above that up to 1MB > is not > + // Note that we check if we actually have 1MB > + // > + > + BuildResourceDescriptorHob ( > + ResourceType, > + ResourceAttributes, > + 0, > + MIN (0xa0000, E820Entry.Length) > + ); > + > + E820Entry.BaseAddr +=3D BASE_1MB; > + E820Entry.Length -=3D MIN (BASE_1MB, E820Entry.Length); > + } > + > + // > + // Note that we can only check if this is the largest entry after > reserving everything we have to reserve > + // > + > + if ((E820Entry.Length > LargestE820Entry.Length) && > (E820Entry.BaseAddr + E820Entry.Length <=3D SIZE_4GB)) { > + CopyMem (&LargestE820Entry, &E820Entry, sizeof > (EFI_E820_ENTRY64)); > + DEBUG (( > + DEBUG_INFO, > + "New largest entry for PEI: BaseAddress %lx, Size %lx\n", > + LargestE820Entry.BaseAddr, > + LargestE820Entry.Length > + )); > + } > + } > + > + BuildResourceDescriptorHob ( > + ResourceType, > + ResourceAttributes, > + E820Entry.BaseAddr, > + E820Entry.Length > + ); > + > + DEBUG (( > + DEBUG_INFO, > + "Processed E820 entry [%lx, %lx] with type %x\n", > + E820Entry.BaseAddr, > + E820Entry.BaseAddr + E820Entry.Length - 1, > + E820Entry.Type > + )); > + } > + > + ASSERT (LargestE820Entry.Length !=3D 0); > + DEBUG (( > + DEBUG_INFO, > + "Largest memory chunk found: [%lx, %lx]\n", > + LargestE820Entry.BaseAddr, > + LargestE820Entry.BaseAddr + LargestE820Entry.Length - 1 > + )); > + > + PeiServicesTable =3D GetPeiServicesTablePointer (); > + > + Status =3D (*PeiServices)->InstallPeiMemory (PeiServicesTable, > LargestE820Entry.BaseAddr, LargestE820Entry.Length); > + > + ASSERT_EFI_ERROR (Status); > + > + // Reserve architectural PC MMIO regions > + // VGA space + BIOS shadow mapping > Let's be consistent with other platforms (at least Intel ones) and use // // Comment // as is already used in other parts of the platform. This applies to all other non-conforming comments in the patch. > + ReserveMmioRegion (0xa0000, 0x100000 - 0xa0000); > + // IO APIC and LAPIC space > + ReserveMmioRegion (0xfec00000, 0xff000000 - 0xfec00000); > + return Status; > +} > diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c > b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c > new file mode 100644 > index 000000000000..a66cbf6005fb > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c > @@ -0,0 +1,59 @@ > +/** @file Pci.c > + PCI Initialization for PIIX4 QEMU > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PlatformInit.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Initialize PCI support for QEMU PIIX4 machine > + > + It also publishes PCI MMIO and IO ranges PCDs for OVMF PciHostBridgeLi= b > + > + @retval EFI_SUCCESS Initialization was a success > + @retval EFI_UNSUPPORTED Initialization failed (Memory below 4Gb probin= g > failed) > +**/ > +EFI_STATUS > +EFIAPI > +InitializePciPIIX4 ( > + VOID > + ) > +{ > + UINTN PciIoBase; > + UINTN PciIoSize; > + UINTN PciMmio32Base; > + UINTN PciMmio32Size; > + > + PciIoBase =3D PIIX4_PCI_IO_BASE; > + PciIoSize =3D PIIX4_PCI_IO_SIZE; > + > + PcdSet64S (PcdPciIoBase, PciIoBase); > + PcdSet64S (PcdPciIoSize, PciIoSize); > + > Explain why we're doing this. > + PciMmio32Base =3D (UINTN) GetMemoryBelow4Gb (); > + > + if (PciMmio32Base =3D=3D 0) { > + DEBUG ((DEBUG_ERROR, "Unable to detect memory below 4Gb\n")); > + ASSERT (PciMmio32Base !=3D 0); > + return EFI_UNSUPPORTED; > + } > + > + DEBUG ((DEBUG_ERROR, "Memory below 4Gb: %x \n", PciMmio32Base)); > + PciMmio32Size =3D PCI_MMIO_TOP_ADDRESS - PciMmio32Base; > + > + PcdSet64S (PcdPciMmio32Base, PciMmio32Base); > + PcdSet64S (PcdPciMmio32Size, PciMmio32Size); > + > + return EFI_SUCCESS; > +} > diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c > b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c > new file mode 100644 > index 000000000000..a61fd6447e91 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c > @@ -0,0 +1,91 @@ > +/** @file Pcie.c > + PCI Express initialization for QEMU Q35 > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PlatformInit.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Initialize PCI Express support for QEMU Q35 system > + It also publishes PCI MMIO and IO ranges PCDs for OVMF PciHostBridgeLi= b > + @retval EFI_SUCCESS Initialization was successful > +**/ > +EFI_STATUS > +EFIAPI > +InitializePcie ( > + VOID > + ) > +{ > + UINTN PciBase; > + UINTN PciSize; > + UINTN PciIoBase; > + UINTN PciIoSize; > + > + union { > + UINT64 Uint64; > + UINT32 Uint32[2]; > + } PciExBarBase; > + > + PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); > + > + // Build a reserved memory space for PCIE MMIO > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_MEMORY_RESERVED, > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED, > + PciExBarBase.Uint64, > + SIZE_256MB > + ); > + > + BuildMemoryAllocationHob ( > + PciExBarBase.Uint64, > + SIZE_256MB, > + EfiReservedMemoryType > + ); > + > + // Clear lower 32 bits of register > + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); > + > + // Program PCIE MMIO Base address in MCH PCIEXBAR register > + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), > PciExBarBase.Uint32[1]); > + > + // Enable 256Mb MMIO space > + PciWrite32 ( > + DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), > + PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN > + ); > + > + // Disable Pci MMIO above 4Gb > + PcdSet64S (PcdPciMmio64Size, 0); > + > + // Set Pci MMIO space below 4GB > Nit: It should be PCI and PCIe. > + PciBase =3D (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + SIZE_256MB)= ; > + PciSize =3D PCI_MMIO_TOP_ADDRESS - PciBase; > + > + PcdSet64S (PcdPciMmio32Base, PciBase); > + PcdSet64S (PcdPciMmio32Size, PciSize); > + > + // Set Pci IO port range > + PciIoBase =3D Q35_PCI_IO_BASE; > + PciIoSize =3D Q35_PCI_IO_SIZE; > + > + PcdSet64S (PcdPciIoBase, PciIoBase); > + PcdSet64S (PcdPciIoSize, PciIoSize); > + > + return EFI_SUCCESS; > +} > diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.= c > b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c > new file mode 100644 > index 000000000000..f69518301cd2 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c > @@ -0,0 +1,67 @@ > +/** @file PlarformInit.c > + Platform initialization PEIM for QEMU > + > + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved. > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include "PlatformInit.h" > +#include > +#include > +#include "Library/DebugLib.h" > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +PlatformInit ( > + IN EFI_PEI_FILE_HANDLE FileHandle, > + IN CONST EFI_PEI_SERVICES **PeiServices > + ) > +{ > + EFI_STATUS Status; > + UINT16 DeviceId; > + EFI_HOB_PLATFORM_INFO *EfiPlatformInfo; > + > + // Install permanent memory > + Status =3D InstallMemory (PeiServices); > + > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Memory installation failed\n")); > + return Status; > + } else { > + DEBUG ((DEBUG_INFO, "Memory installation success\n")); > + } > + > + // Report CPU core count to MPInitLib > + MaxCpuInit (); > + > + EfiPlatformInfo =3D AllocateZeroPool (sizeof (EFI_HOB_PLATFORM_INFO)); > + if (EfiPlatformInfo =3D=3D NULL) { > + DEBUG ((DEBUG_ERROR, "Failed to allocate pool for > EFI_HOB_PLATFORM_INFO\n")); > + return EFI_UNSUPPORTED; > + } > + > + // Report gUefiOvmfPkgPlatformInfo HOB with only the necessary data fo= r > OVMF > + DeviceId =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, > PCI_DEVICE_ID_OFFSET)); > + DEBUG ((DEBUG_INFO, "Building gUefiOvmfPkgPlatformInfoGuid with Host > bridge dev ID %x \n", DeviceId)); > + (*EfiPlatformInfo).HostBridgeDevId =3D DeviceId; > + > + BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, EfiPlatformInfo, > sizeof (EFI_HOB_PLATFORM_INFO)); > + > + PcdSet16S (PcdOvmfHostBridgePciDevId, DeviceId); > + > + // Initialize PCI or PCIe based on current emulated system > + if (DeviceId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { > + DEBUG ((DEBUG_INFO, "Q35: Initialize PCIe\n")); > + return InitializePcie (); > + } else { > + DEBUG ((DEBUG_INFO, "PIIX4: Initialize PCI\n")); > + return InitializePciPIIX4 (); > + } > +} > diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc > b/Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc > new file mode 100644 > index 000000000000..29f49f914171 > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc > @@ -0,0 +1,85 @@ > +## @file > +# Flashmap and variable definitions for QemuOpenBoardPkg FVs and FD > +# > +# @copyright > +# Copyright (C) 2022 Jehl Th=C3=A9o > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > +# > +# These three items are tightly coupled. > +# The spare area size must be >=3D the first two areas. > +# The total size must match the size in the EFI_FIRMWARE_VOLUME_HEADER. > +# The NvStorageVariableSize must also match the VARIABLE_STORE_HEADER > size. > +# The EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER doesn't have size info. > +# > +# There isn't really a benefit to a larger spare area unless the FLASH > device > +# block size is larger than the size specified. > +# > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D > 0x0003C000 > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D > 0x00004000 > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > + > +# > +# Early FV > +# > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D > 0x00081000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize =3D > 0x00040000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D > 0x00010000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D > 0x00040000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D > 0x00020000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D > 0x00080000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize =3D > 0x00020000 > + > +# > +# Later FV > +# > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D > 0x00400000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D > 0x00100000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D > 0x00080000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize - > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize - > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize - > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize > + > +# > +# Calculate Offsets Once (Do not modify) > +# This layout is specified by the EDK II Minimum Platform Archicture > specification. > +# Each offset is the prior region's offset plus the prior region's size. > +# > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D > 0x00000000 > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize > + > +# > +# Calculate base addresses > +# > + > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase =3D > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize > + > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize > +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase =3D > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + > gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize > diff --git > a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/SecEntry.nas= m > b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/SecEntry.nas= m > new file mode 100644 > index 000000000000..bd90a466f790 > --- /dev/null > +++ > b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/SecEntry.nas= m > @@ -0,0 +1,117 @@ > > +;-----------------------------------------------------------------------= ------- > +; @file SecEntry > +; Sec entry implementation > Nit: SEC > +; > +; Copyright (c) 2022 Th=C3=A9o Jehl > +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; > > +;-----------------------------------------------------------------------= ------- > + > +CODE_SEG equ CodeSegDescriptor - GDT_START > +DATA_SEG equ DataSegDescriptor - GDT_START > + > +extern ASM_PFX(SecStartup) > + > +extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase)) > +extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize)) > + > +SECTION .text > + > +BITS 16 > +align 4 > +global ASM_PFX(_ModuleEntryPoint) > +ASM_PFX(_ModuleEntryPoint): > + cli > + ; Save the BIST in mm0 > + movd mm0, eax > + mov esi, GDT_Descriptor > + db 66h > + lgdt [cs:si] > + > + mov eax, cr0 > + or eax, 1 > + mov cr0, eax > + > + mov ax, DATA_SEG > + mov ds, ax > + mov es, ax > + mov fs, ax > + mov gs, ax > + mov ss, ax > + > + mov esi, ProtectedModeEntryLinearAddress > + > + jmp dword far [cs:si] > + > +BITS 32 > +align 4 > +ProtectedModeEntry: > + PROTECTED_MODE equ $ > + > + mov ecx, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))] > + mov edx, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))] > + > + ;Initialize the stack at the end of base + size > Nit: space between ; and Initialize > + mov esp, ecx > + add esp, edx > + > + ; TODO: Multiprocessor support > Remove this TODO and figure out if we want to actually keep BISTs or not (not like we're ever getting a bad one anyway). > + push 1 > + ; For now, we push the BIST once > + movd eax, mm0 > + push eax > + ; Code in PlatformSecLib will look up this information we've just push= ed > + ; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D TOP OF MEMORY = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + ; Count of BISTs > + ; BISTs[1..n] > + ; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D REST OF MEMORY = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > + ; Each BIST is always a DWORD in size > + > + mov edi, 0xFFFFFFFC ;BFV > + > + push DWORD [edi] ;Passes BFV > + > + push ecx ;Passes RAM size > + > + push edx ;Passes RAM base > + > + call ASM_PFX(SecStartup) > + > +align 8 > +NULL_SEGMENT equ $ - GDT_START > +GDT_START: > + > +NullSegDescriptor: > + dd 0x0 > + dd 0x0 > + > + CODE_SEL equ $ - GDT_START > + > +CodeSegDescriptor: > + dw 0xFFFF > + dw 0x0 > + db 0x0 > + db 0x9B > + db 0xCF > + db 0x0 > + > + DATA_SEL equ $ - GDT_START > + > +DataSegDescriptor: > + dw 0xFFFF > + dw 0x0 > + db 0x0 > + db 0x93 > + db 0xCF > + db 0x0 > + > +GDT_END: > + > +GDT_Descriptor: > + dw GDT_END - GDT_START - 1 > + dd GDT_START > + > +ProtectedModeEntryLinearAddress: > +ProtectedModeEntryLinear: > + DD ProtectedModeEntry ; Offset of our 32 bit code > + DW CODE_SEL > diff --git a/Platform/Qemu/QemuOpenBoardPkg/README.md > b/Platform/Qemu/QemuOpenBoardPkg/README.md > new file mode 100644 > index 000000000000..e1238c1f4e3e > --- /dev/null > +++ b/Platform/Qemu/QemuOpenBoardPkg/README.md > @@ -0,0 +1,53 @@ > +# QemuOpenBoardPkg > + > +This project brings UEFI support to QEMU x86_64 following the MinPlatfor= m > specification. > + > +## Capabilities > + > +- Supports IA-32 and hybrid X64 (IA32 PEI Core and X64 DXE Core) > +- Modern QEMU (Tested on 7.0.0) > + - PIIX4 and Q35 machines > +- Boot UEFI Linux > +- Boot UEFI Windows > + > +## How to build > + > +### Pre-requesites > + > +- EDK2 > + - How to setup a local tree: > https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-wit= h-EDK-II > + > +- EDK2 Platforms > + - https://github.com/tianocore/edk2-platforms > + > +- Environnements variables: > + - WORKSPACE set to your current workspace > + - PACKAGES_PATH should contain path to: > + - edk2 > + - edk2-platforms > + - edk2-platforms/Platform/Intel > + - edk2-platforms/Platform/Qemu > + - edk2-platforms/Silicon/Intel > + > +Currently QemuOpenBoardPkg's PEI Core is 32 bits only, DXE supports > either 32 bits or 64 bits > + > +QemuOpenBoardPkg (IA32 PEI - IA32 DXE) > + > +```build -a IA32 -D PEI_ARCH=3DIA32 -D DXE_ARCH=3DIA32``` > + > +QemuOpenBoardPkg (IA32 PEI - X64 DXE) > + > +```build -a IA32 -a X64 -D PEI_ARCH=3DIA32 -D DXE_ARCH=3DX64``` > + > +## How to use > + > +Using qemu-system-x86_64, use > + > +```-bios ``` > + > +To redirect serial output to the console > + > +```-serial stdio``` > + > +## Important notes > +- Secure boot is not yet available due to QemuOpenBoardPkg NVRAM storage > not being persistent yet. > -- > 2.32.1 (Apple Git-133) > > --=20 Pedro Falcato --000000000000f925e905e7682046 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Sat, Aug 27, 2022 at 1:02 AM Th=C3= =A9o <theojehl76@gmail.com&g= t; wrote:
From: = Th=C3=A9o Jehl <theojehl76@gmail.com>

QemuOpenBoardPkg adds a MinPlatform port to Qemu x86_64
It can boots UEFI Linux and Windows, and works on PIIX4 and Q35
This board port provides a simple starting place for investigating edk2 and=
MinPlatform Arch.
Currently we implement up to stage 4 of the MinPlatform spec and can boot Windows/Linux.

Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Pedro Falcato <pedro.falcato@gmail.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Stefan Hajnoczi <stefanha@gmail.com>

Signed-off-by: Th=C3=A9o Jehl <theojehl76@gmail.com>
---
=C2=A0Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 |=C2=A0 32 +
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 55 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 31 +
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 | 100 +++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 |=C2=A0 56 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 | 144 +++++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 | 313 ++++++++++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootM= anagerLib.inf |=C2=A0 39 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.inf= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 29 +
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfg= Lib.inf=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 23 +
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.= inf=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 63 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.= inf=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 49 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 59 ++ =C2=A0Platform/Qemu/QemuOpenBoardPkg/Include/Library/OpenQemuFwCfgLib.h=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 102 +++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 59 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootM= anager.c=C2=A0 =C2=A0 =C2=A0 | 105 ++++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 222 +++++++ =C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfg= Lib.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 130 ++++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.= c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 285 +++++++++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.= c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 140 +++++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0|=C2=A0 56 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | 244 ++++++++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0|=C2=A0 59 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 91 +++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2= =A0 67 ++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= =C2=A0 85 +++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/SecEntry.n= asm=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 117 ++++
=C2=A0Platform/Qemu/QemuOpenBoardPkg/README.md=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 53 ++
=C2=A028 files changed, 2808 insertions(+)

diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec b/Platform= /Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec
new file mode 100644
index 000000000000..3b5300a0c309
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec
@@ -0,0 +1,32 @@
+## @file QemuOpenBoardPkg.dec
+#=C2=A0 Declaration file for QemuOpenBoardPkg.
+#
+#=C2=A0 This package supports a simple QEMU port implemented per the MinPl= atform
+#=C2=A0 Arch specification.
+#
+#=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl
+#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#=C2=A0 @par Specification Reference:
+#=C2=A0 =C2=A0-https://tia= nocore-docs.github.io/edk2-MinimumPlatformSpecification/draft/ 0.7
+##
+
+[Defines]
+=C2=A0 DEC_SPECIFICATION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =3D 0x00010005
+=C2=A0 PACKAGE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0=3D QemuOpenBoardPkg
+=C2=A0 PACKAGE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0=3D 3487DE0A-6770-48A2-9833-FB426A42D7B2
+=C2=A0 PACKAGE_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =3D 0.1
+
+[LibraryClasses]
+=C2=A0 OpenQemuFwCfgLib|Include/Library/OpenQemuFwCfgLib.h
+
+[Includes]
+=C2=A0 Include
+
+[Guids]
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D { 0x221b20c4, 0xa3dc, 0x4b8f, = { 0xb6, 0x94, 0x03, 0xc7, 0xf4, 0x76, 0x51, 0x2b } }
+
+[PcdsFixedAtBuild]
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x0000= 0001
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x0000= 0002
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid.PcdDebugIoPort|0|UINT16|0x00000003<= br> diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc b/Pl= atform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc
new file mode 100644
index 000000000000..114c4e8193b2
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc
@@ -0,0 +1,55 @@
+## @file
+# Common DSC content to begin Stage 1 enabling
+#
+# @copyright
+# Copyright (C) 2022 Intel Corporation
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+##########################################################################= ######
+#
+# Library Class section - list of all Library Classes needed by this Platf= orm.
+#
+##########################################################################= ######
+
+[LibraryClasses]
+=C2=A0 PciSegmentInfoLib=C2=A0 =C2=A0 =C2=A0 =C2=A0| MinPlatformPkg/Pci/Li= brary/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+=C2=A0 BoardInitLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | QemuOpenBoa= rdPkg/Library/BoardInitLib/BoardInitLib.inf
+=C2=A0 SetCacheMtrrLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| MinPlatformPkg/L= ibrary/SetCacheMtrrLib/SetCacheMtrrLib.inf
+=C2=A0 ReportCpuHobLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| MinPlatformPkg/P= latformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+=C2=A0 SiliconPolicyInitLib=C2=A0 =C2=A0 | MinPlatformPkg/PlatformInit/Lib= rary/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf
+=C2=A0 SiliconPolicyUpdateLib=C2=A0 | MinPlatformPkg/PlatformInit/Library/= SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf
+=C2=A0 ReportFvLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| QemuOp= enBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
+=C2=A0 PciLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 | MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+
+[LibraryClasses.Common.SEC]
+=C2=A0 TestPointCheckLib=C2=A0 =C2=A0 =C2=A0 =C2=A0| MinPlatformPkg/Test/L= ibrary/TestPointCheckLib/SecTestPointCheckLib.inf
+=C2=A0 TimerLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | M= dePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+
+[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+=C2=A0 TestPointCheckLib=C2=A0 =C2=A0 =C2=A0 =C2=A0| MinPlatformPkg/Test/L= ibrary/TestPointCheckLib/PeiTestPointCheckLib.inf
+=C2=A0 TestPointLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | MinPlatform= Pkg/Test/Library/TestPointLib/PeiTestPointLib.inf
+=C2=A0 TimerLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | M= dePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+
+[Components.$(PEI_ARCH)]
+=C2=A0 UefiCpuPkg/SecCore/SecCore.inf
+=C2=A0 MdeModulePkg/Core/Pei/PeiMain.inf
+=C2=A0 MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+=C2=A0 UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+=C2=A0 MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmen= tPciCfg2Pei.inf
+=C2=A0 MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.= inf
+=C2=A0 MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+=C2=A0 =C2=A0 <LibraryClasses>
+=C2=A0 =C2=A0 =C2=A0 PcdLib | MdePkg/Library/BasePcdLibNull/BasePcdLibNull= .inf
+=C2=A0 }
+=C2=A0 MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeR= outerPei.inf
+=C2=A0 MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.i= nf
+=C2=A0 MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf<= br> +=C2=A0 MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+=C2=A0 MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf
+=C2=A0 MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+=C2=A0 QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf
+=C2=A0 !if $(SMM_REQUIRED) =3D=3D TRUE
+=C2=A0 =C2=A0 OvmfPkg/SmmAccess/SmmAccessPei.inf
+=C2=A0 !endif
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc b/Pl= atform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc
new file mode 100644
index 000000000000..4b331c4ed1fc
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc
@@ -0,0 +1,31 @@
+## @file
+# Common DSC content to begin Stage 2 enabling
+#
+# @copyright
+# Copyright (C) 2022 Jehl Th=C3=A9o
Why is your name = backwards here (and in other places)?
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[LibraryClasses.Common]
+=C2=A0 ResetSystemLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/= ResetSystemLib/BaseResetSystemLib.inf
+=C2=A0 PciHostBridgeLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/PciHo= stBridgeLib/PciHostBridgeLib.inf
+=C2=A0 PciHostBridgeUtilityLib | OvmfPkg/Library/PciHostBridgeUtilityLib/P= ciHostBridgeUtilityLib.inf
+=C2=A0 DxeHardwareInfoLib=C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/HardwareIn= foLib/DxeHardwareInfoLib.inf
+
+[LibraryClasses.Common.PEIM]
+=C2=A0 MpInitLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| U= efiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+=C2=A0 TimerLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | O= vmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+
+[LibraryClasses.Common.DXE_DRIVER, LibraryClasses.Common.DXE_RUNTIME_DRIVE= R, LibraryClasses.Common.DXE_SMM_DRIVER, LibraryClasses.Common.UEFI_DRIVER,= LibraryClasses.Common.UEFI_APPLICATION, LibraryClasses.Common.SMM_CORE] +=C2=A0 PciLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 | OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf
+
+[Components.$(PEI_ARCH)]
+=C2=A0 UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+=C2=A0 MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf
+=C2=A0 MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf=
+=C2=A0 MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+[Components.$(DXE_ARCH)]
+=C2=A0 MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.= inf
+=C2=A0 MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc b/Pl= atform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc
new file mode 100644
index 000000000000..0435fb2da81d
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc
@@ -0,0 +1,100 @@
+## @file
+# Common DSC content to begin Stage 3 enabling
+#
+# @copyright
+# Copyright (C) 2022 Jehl Th=C3=A9o
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[LibraryClasses.Common]
+=C2=A0 PlatformBootManagerLib=C2=A0 | OvmfPkg/Library/PlatformBootManagerL= ib/PlatformBootManagerLib.inf
+=C2=A0 BootLogoLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| MdeMod= ulePkg/Library/BootLogoLib/BootLogoLib.inf
+=C2=A0 NvVarsFileLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| OvmfPkg/Lib= rary/NvVarsFileLib/NvVarsFileLib.inf
+=C2=A0 QemuFwCfgS3Lib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/= QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf
+=C2=A0 QemuLoadImageLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/X86Qe= muLoadImageLib/X86QemuLoadImageLib.inf
+=C2=A0 QemuBootOrderLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/QemuB= ootOrderLib/QemuBootOrderLib.inf
+=C2=A0 PlatformBmPrintScLib=C2=A0 =C2=A0 | OvmfPkg/Library/PlatformBmPrint= ScLib/PlatformBmPrintScLib.inf
+=C2=A0 XenPlatformLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/= XenPlatformLib/XenPlatformLib.inf
+=C2=A0 LoadLinuxLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Lib= rary/LoadLinuxLib/LoadLinuxLib.inf
+=C2=A0 SerializeVariablesLib=C2=A0 =C2=A0| OvmfPkg/Library/SerializeVariab= lesLib/SerializeVariablesLib.inf
+=C2=A0 BoardBootManagerLib=C2=A0 =C2=A0 =C2=A0| QemuOpenBoardPkg/Library/B= oardBootManagerLib/BoardBootManagerLib.inf
+=C2=A0 LocalApicLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | UefiCpuPkg/= Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
+=C2=A0 IoLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0| MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+=C2=A0 PciExpressLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| MdePkg/Libr= ary/BasePciExpressLib/BasePciExpressLib.inf
+=C2=A0 PcdLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 | MdePkg/Library/DxePcdLib/DxePcdLib.inf
+=C2=A0 PciLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 | MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+=C2=A0 DebugLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | M= dePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+=C2=A0 SerialPortLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| PcAtChipset= Pkg/Library/SerialIoLib/SerialIoLib.inf
+
+[Components.$(DXE_ARCH)]
+=C2=A0 MdeModulePkg/Core/Dxe/DxeMain.inf {
+=C2=A0 =C2=A0 <LibraryClasses>
+=C2=A0 =C2=A0 =C2=A0 NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/Lzm= aCustomDecompressLib.inf
+=C2=A0 }
+=C2=A0 MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+=C2=A0 =C2=A0 <LibraryClasses>
+=C2=A0 =C2=A0 =C2=A0 PcdLib | MdePkg/Library/BasePcdLibNull/BasePcdLibNull= .inf
+=C2=A0 =C2=A0 }
+=C2=A0 MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStat= usCodeRouterRuntimeDxe.inf
+=C2=A0 MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandl= erRuntimeDxe.inf
+=C2=A0 MdeModulePkg/Universal/Metronome/Metronome.inf
+=C2=A0 MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+=C2=A0 PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime= Dxe.inf
+=C2=A0 MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+=C2=A0 MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +=C2=A0 MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterR= untimeDxe.inf
+=C2=A0 MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+=C2=A0 MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+=C2=A0 MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+=C2=A0 MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+=C2=A0 UefiCpuPkg/CpuDxe/CpuDxe.inf
+=C2=A0 PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+=C2=A0 MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+=C2=A0 MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.= inf
+=C2=A0 MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.= inf
+=C2=A0 MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDx= e.inf
+=C2=A0 MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +=C2=A0 MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +=C2=A0 MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+=C2=A0 MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+=C2=A0 UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+=C2=A0 OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
+=C2=A0 MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+=C2=A0 MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+=C2=A0 MdeModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
+=C2=A0 MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+=C2=A0 MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+=C2=A0 MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+=C2=A0 PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf
+=C2=A0 MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+=C2=A0 FatPkg/EnhancedFatDxe/Fat.inf
+=C2=A0 OvmfPkg/QemuRamfbDxe/QemuRamfbDxe.inf
+
+=C2=A0 ShellPkg/Application/Shell/Shell.inf {
+=C2=A0 =C2=A0 <LibraryClasses>
+=C2=A0 =C2=A0 =C2=A0 ShellCommandLib | ShellPkg/Library/UefiShellCommandLi= b/UefiShellCommandLib.inf
+=C2=A0 =C2=A0 =C2=A0 NULL | ShellPkg/Library/UefiShellLevel2CommandsLib/Ue= fiShellLevel2CommandsLib.inf
+=C2=A0 =C2=A0 =C2=A0 NULL | ShellPkg/Library/UefiShellLevel1CommandsLib/Ue= fiShellLevel1CommandsLib.inf
+=C2=A0 =C2=A0 =C2=A0 NULL | ShellPkg/Library/UefiShellLevel3CommandsLib/Ue= fiShellLevel3CommandsLib.inf
+=C2=A0 =C2=A0 =C2=A0 NULL | ShellPkg/Library/UefiShellDriver1CommandsLib/U= efiShellDriver1CommandsLib.inf
+=C2=A0 =C2=A0 =C2=A0 NULL | ShellPkg/Library/UefiShellDebug1CommandsLib/Ue= fiShellDebug1CommandsLib.inf
+=C2=A0 =C2=A0 =C2=A0 NULL | ShellPkg/Library/UefiShellInstall1CommandsLib/= UefiShellInstall1CommandsLib.inf
+=C2=A0 =C2=A0 =C2=A0 NULL | ShellPkg/Library/UefiShellNetwork1CommandsLib/= UefiShellNetwork1CommandsLib.inf
+=C2=A0 =C2=A0 =C2=A0 HandleParsingLib | ShellPkg/Library/UefiHandleParsing= Lib/UefiHandleParsingLib.inf
+=C2=A0 =C2=A0 =C2=A0 PrintLib | MdePkg/Library/BasePrintLib/BasePrintLib.i= nf
+=C2=A0 =C2=A0 =C2=A0 BcfgCommandLib | ShellPkg/Library/UefiShellBcfgComman= dLib/UefiShellBcfgCommandLib.inf
+=C2=A0 =C2=A0 <PcdsFixedAtBuild>
+=C2=A0 =C2=A0 =C2=A0 gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask | 0xFF<= br> +=C2=A0 =C2=A0 =C2=A0 gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize = | FALSE
+=C2=A0 =C2=A0 =C2=A0 gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize= | 8000
+=C2=A0 }
+
+=C2=A0 MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+=C2=A0 OvmfPkg/PlatformDxe/Platform.inf
+=C2=A0 MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf<= br> +=C2=A0 MdeModulePkg/Application/UiApp/UiApp.inf
+=C2=A0 OvmfPkg/IoMmuDxe/IoMmuDxe.inf
+=C2=A0 MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+=C2=A0 OvmfPkg/SioBusDxe/SioBusDxe.inf
+=C2=A0 MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc b/Pl= atform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc
new file mode 100644
index 000000000000..4a1f9c7d0124
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc
@@ -0,0 +1,56 @@
+## @file
+# Common DSC content to begin Stage 4 enabling
+#
+# @copyright
+# Copyright (C) 2022 Jehl Th=C3=A9o
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[LibraryClasses]
+=C2=A0 !if $(SMM_REQUIRED) =3D=3D TRUE
+=C2=A0 =C2=A0 SpiFlashCommonLib=C2=A0 =C2=A0 =C2=A0| IntelSiliconPkg/Libra= ry/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+=C2=A0 !endif
+
+[LibraryClasses.Common.DXE_SMM_DRIVER]
+=C2=A0 LockBoxLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | MdeMod= ulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
+=C2=A0 SmmCpuPlatformHookLib=C2=A0 =C2=A0| OvmfPkg/Library/SmmCpuPlatformH= ookLibQemu/SmmCpuPlatformHookLibQemu.inf
+=C2=A0 SmmCpuFeaturesLib=C2=A0 =C2=A0 =C2=A0 =C2=A0| OvmfPkg/Library/SmmCp= uFeaturesLib/SmmCpuFeaturesLib.inf
+
+[Components.$(DXE_ARCH)]
+=C2=A0 OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
+=C2=A0 MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+=C2=A0 OvmfPkg/SataControllerDxe/SataControllerDxe.inf
+=C2=A0 MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+=C2=A0 MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+=C2=A0 MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+=C2=A0 MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+=C2=A0 MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+=C2=A0 MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+=C2=A0 MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+=C2=A0 !if $(SMM_REQUIRED) =3D=3D TRUE
+=C2=A0 =C2=A0 OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
+=C2=A0 =C2=A0 OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf
+=C2=A0 =C2=A0 MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+=C2=A0 =C2=A0 MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+
+=C2=A0 =C2=A0 MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+=C2=A0 =C2=A0 UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+
+=C2=A0 =C2=A0 MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStat= usCodeRouterSmm.inf
+=C2=A0 =C2=A0 MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandl= erSmm.inf
+=C2=A0 =C2=A0 UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+=C2=A0 =C2=A0 MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWr= iteSmm.inf
+=C2=A0 =C2=A0 IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm= .inf
+=C2=A0 !endif
+
+=C2=A0 #
+=C2=A0 # SMBIOS Support
+=C2=A0 #
+=C2=A0 MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf {
+=C2=A0 =C2=A0 <LibraryClasses>
+=C2=A0 =C2=A0 =C2=A0 NULL | OvmfPkg/Library/SmbiosVersionLib/DetectSmbiosV= ersionLib.inf
+=C2=A0 }
+=C2=A0 OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc b/Platform= /Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc
new file mode 100644
index 000000000000..958d6b9537c9
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc
@@ -0,0 +1,144 @@
+## @file
+#=C2=A0 QemuOpenBoardPkg.dsc
+#
+#=C2=A0 Description file for QemuOpenBoardPkg
+#
+#=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl
+#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+=C2=A0 DSC_SPECIFICATION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D 0x000= 1001C
+=C2=A0 PLATFORM_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0=3D 94797875-D562-40CF-8D55-ADD623C8D46C
+=C2=A0 PLATFORM_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0=3D QemuOpenBoardPkg
+=C2=A0 PLATFORM_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 0.1 +=C2=A0 SUPPORTED_ARCHITECTURES=C2=A0 =C2=A0 =C2=A0=3D IA32 | X64
+=C2=A0 FLASH_DEFINITION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D $(PLA= TFORM_NAME)/$(PLATFORM_NAME).fdf
+=C2=A0 OUTPUT_DIRECTORY=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D Build= /$(PLATFORM_NAME)
+=C2=A0 BUILD_TARGETS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0=3D DEBUG | RELEASE | NOOPT
+=C2=A0 SKUID_IDENTIFIER=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D ALL +=C2=A0 SMM_REQUIRED=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D FALSE
+
+!ifndef $(PEI_ARCH)
+=C2=A0 !error "PEI_ARCH must be specified to build this feature!"= ;
s/feature/package/
+!endif
+!ifndef $(DXE_ARCH)
+=C2=A0 !error "DXE_ARCH must be specified to build this feature!"= ;
s/feature/package/
+!endif
+
+[SkuIds]
+=C2=A0 0 | DEFAULT
+
+[Packages]
+=C2=A0 MdePkg/MdePkg.dec
+=C2=A0 MdeModulePkg/MdeModulePkg.dec
+=C2=A0 MinPlatformPkg/MinPlatformPkg.dec
+=C2=A0 QemuOpenBoardPkg/QemuOpenBoardPkg.dec
+=C2=A0 UefiCpuPkg/UefiCpuPkg.dec
+
+[PcdsFixedAtBuild]
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdBootStage | 4
+
+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel=C2=A0 =C2=A0 =C2= =A0 =C2=A0 | 0x802A00C7
+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel=C2=A0 =C2=A0|= 0x802A00C7
+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0| 0x17
+
+=C2=A0 # QEMU "memory" is functional even in SEC.=C2=A0 For simp= licity, we just use that
+=C2=A0 # "memory" for the temporary RAM
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase | 0x1000000
=
16MB is way too high for a temporary RAM base, although i= n practice that shouldn't matter (QEMU defaults to 128MB and I'm no= t sure anyone runs it with less). Is it possible to pick something lower?
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize | 0x010000
+
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid.PcdDebugIoPort=C2=A0 =C2=A0 | 0x402=
+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdFSBClock=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 | 100000000
+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress | 0xB0000000
<= /blockquote>
Please explain why we pick this address (no magic values!)= . Most people don't have the same context you do.
+
+=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| TRUE
+=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChang= e=C2=A0 | FALSE
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase | 0x00000000 # Wil= l be updated by build
+
+[PcdsFeatureFlag]
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable=C2=A0 | TR= UE
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable=C2=A0 =C2=A0 = =C2=A0| FALSE
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable=C2=A0 =C2=A0 =C2= =A0 =C2=A0 | FALSE
+=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|TRUE<= br> +
+=C2=A0 !if $(DXE_ARCH) =3D=3D X64
+=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode=C2= =A0 | TRUE
+=C2=A0 !else
+=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode=C2= =A0 | FALSE
+=C2=A0 !endif
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 | TRUE
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable=C2=A0 =C2=A0 = =C2=A0| TRUE
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| FALSE
+
+=C2=A0 !if $(SMM_REQUIRED) =3D=3D TRUE
+=C2=A0 =C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| TRUE
+=C2=A0 =C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | FALSE
+=C2=A0 =C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache= =C2=A0 | FALSE
+=C2=A0 !endif
+
+[PcdsDynamicDefault]
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId | 0
+
+=C2=A0 # Video setup
+=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution=C2= =A0 | 640
+=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution=C2= =A0 =C2=A0 | 480
+
+=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion | 0x0208
+=C2=A0 gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev=C2=A0 | 0x0
+
+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut | 3
+
+=C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber=C2=A0 =C2= =A0| 0
+=C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber=C2=A0 | = 0
+
+=C2=A0 !if $(SMM_REQUIRED) =3D=3D TRUE
+=C2=A0 =C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 8
+=C2=A0 =C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase=C2=A0 = =C2=A0 =C2=A0| FALSE
+=C2=A0 =C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 0x01
+=C2=A0 =C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 | 100000
+=C2=A0 !endif
+
+# Include Common libraries and then stage specific libraries and component= s
+!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+!include QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc
+!include QemuOpenBoardPkg/Include/Dsc/Stage2.dsc.inc
+!include QemuOpenBoardPkg/Include/Dsc/Stage3.dsc.inc
+!include QemuOpenBoardPkg/Include/Dsc/Stage4.dsc.inc
= As discussed in private, I'm torn on this StageN.dsc.inc thing. It'= s great to understand what each specific stage requires, horrible to unders= tand how the platform works in general.
+
+[LibraryClasses.Common]
+=C2=A0 OpenQemuFwCfgLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 | QemuOpenBoardPkg/Libr= ary/OpenQemuFwCfgLib/OpenQemuFwCfgLib.inf
+=C2=A0 PlatformHookLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| MdeModulePkg/Lib= rary/BasePlatformHookLibNull/BasePlatformHookLibNull.inf
+=C2=A0 PlatformSecLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | QemuOpenBoardPkg= /Library/PlatformSecLib/PlatformSecLib.inf
+=C2=A0 DebugLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | M= dePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+=C2=A0 PciCf8Lib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| M= dePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+=C2=A0 TimerLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | O= vmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+
+[LibraryClasses.Common.DXE_CORE]
+=C2=A0 TimerLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | O= vmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.inf
+
+[LibraryClasses.Common.DXE_DRIVER, LibraryClasses.Common.DXE_RUNTIME_DRIVE= R, LibraryClasses.Common.DXE_SMM_DRIVER, LibraryClasses.Common.UEFI_DRIVER,= LibraryClasses.Common.UEFI_APPLICATION, LibraryClasses.Common.SMM_CORE] +=C2=A0 TimerLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | O= vmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf
+=C2=A0 QemuFwCfgLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Lib= rary/QemuFwCfgLib/QemuFwCfgDxeLib.inf
+=C2=A0 MemEncryptSevLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/BaseM= emEncryptSevLib/DxeMemEncryptSevLib.inf
+=C2=A0 MemEncryptTdxLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/BaseM= emEncryptTdxLib/BaseMemEncryptTdxLibNull.inf
+=C2=A0 Tcg2PhysicalPresenceLib | OvmfPkg/Library/Tcg2PhysicalPresenceLibNu= ll/DxeTcg2PhysicalPresenceLib.inf
+=C2=A0 ResetSystemLib=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | OvmfPkg/Library/= ResetSystemLib/DxeResetSystemLib.inf
+
+[LibraryClasses.Common.SEC]
+=C2=A0 DebugLib | OvmfPkg/Library/PlatformDebugLibIoPort/PlatformRomDebugL= ibIoPort.inf
+
+[Components.$(DXE_ARCH)]
+=C2=A0 MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+=C2=A0 MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+=C2=A0 OvmfPkg/SataControllerDxe/SataControllerDxe.inf
+=C2=A0 MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+=C2=A0 MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+=C2=A0 MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+=C2=A0 MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+=C2=A0 MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+=C2=A0 MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf b/Platform= /Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf
new file mode 100644
index 000000000000..2f39ce3860f6
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf
@@ -0,0 +1,313 @@
+## @file
+#=C2=A0 QemuOpenBoardPkg.fdf
+#
+#=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl
+#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress=C2=A0 =C2=A0 =C2= =A0 =3D 0xFF800000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0=3D 0x800000
+
+!include QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc
+
+[FD.QemuOpenBoardPkg]
+=C2=A0 BaseAddress=C2=A0 =C2=A0=3D 0xFF800000
+=C2=A0 Size=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 0x800000
+=C2=A0 ErasePolarity =3D 1
+=C2=A0 BlockSize=C2=A0 =C2=A0 =C2=A0=3D 0x1000
+=C2=A0 NumBlocks=C2=A0 =C2=A0 =C2=A0=3D 0x800
+
+=C2=A0 #
+=C2=A0 # Do not modify this block
+=C2=A0 # These three areas are tightly coupled and should be modified with= utmost care.
+=C2=A0 # The total size must match the size in the EFI_FIRMWARE_VOLUME_HEA= DER in NvStorage512K.fdf.
+=C2=A0 # The NvStorageVariableSize must also match the VARIABLE_STORE_HEAD= ER size in NvStorage512K.fdf.
+=C2=A0 # The EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER in CommonNvStorageFtw= Working.fdf doesn't have size info.
+=C2=A0 #
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset | gEf= iMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+=C2=A0 !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset | g= EfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+=C2=A0 !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.= fdf
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset | gEf= iMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+=C2=A0 DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next= PCD as Base/Size to be written
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset | gMinPlatfo= rmPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+=C2=A0 FV =3D FvAdvanced
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset | gMinPlatfo= rmPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+=C2=A0 FV =3D FvSecurity
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset | gMinPlatform= PkgTokenSpaceGuid.PcdFlashFvOsBootSize
+=C2=A0 FV =3D FvOsBoot
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset | gMinPlatfo= rmPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+=C2=A0 FV =3D FvUefiBoot
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset | gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvBspSize
+=C2=A0 FV =3D FvBsp
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset | gMinPlat= formPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+=C2=A0 FV =3D FvPostMemory
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset | gMinPlatformPk= gTokenSpaceGuid.PcdFlashFvFspSSize
+=C2=A0 FV =3D FvFspS
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset | gMinPlatformPk= gTokenSpaceGuid.PcdFlashFvFspMSize
+=C2=A0 FV =3D FvFspM
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset | gMinPlatformPk= gTokenSpaceGuid.PcdFlashFvFspTSize
+=C2=A0 FV =3D FvFspT
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset | gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+=C2=A0 FV =3D FvBspPreMemory
+
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset | gMinPlatf= ormPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+=C2=A0 FV =3D FvPreMemory
+
+###########################
+#
+# Stage 1 Firmware Volumes
+#
+###########################
+
+[FV.FvPreMemory]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =C2=A0 =3D BD479C6B-2EFF-401F-A7F1-566347B4= 1D07
+
+=C2=A0 FILE FV_IMAGE =3D 618FBA00-2231-41F6-9931-25A89DF501D3 {
+=C2=A0 =C2=A0 SECTION FV_IMAGE =3D FvSecurityPreMemory
+=C2=A0 }
+
+=C2=A0 INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+
+=C2=A0 INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusC= odeRouterPei.inf
+=C2=A0 INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+
+=C2=A0 INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWrite= Pei.inf
+=C2=A0 INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+=C2=A0 INF UefiCpuPkg/SecCore/SecCore.inf
+
+[FV.FvSecurityPreMemory]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =C2=A0 =3D F626B0FB-D759-44A8-B131-42408BB3= 533D
+
+[FV.FvBspPreMemory]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =C2=A0 =3D 5CF9C072-385F-44FC-B21B-00207425= 1C08
+
+=C2=A0 INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerP= ei.inf
+=C2=A0 INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.= inf
+=C2=A0 INF QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf
+
+=C2=A0 FILE FV_IMAGE =3D 90B948EA-FF73-4689-B90A-A54F86C1FC01 {
+=C2=A0 =C2=A0 SECTION FV_IMAGE =3D FvAdvancedPreMemory
+=C2=A0 }
+
+[FV.FvAdvancedPreMemory]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =C2=A0 =3D 43528CE0-812B-4074-B77E-C49E7A2F= 4FE1
+
+[FV.FvFspT]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =C2=A0 =3D 958CAF39-0B6C-40F1-B190-EC91C536= CFF9
+
+[FV.FvFspM]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =C2=A0 =3D 03982cf7-246a-4356-b6ba-436a2251= 595c
+
+=C2=A0 INF MdeModulePkg/Core/Pei/PeiMain.inf
+
+=C2=A0 FILE FV_IMAGE =3D 83B39C64-BFB9-42EC-A7A3-527854A5C4C3 {
+=C2=A0 =C2=A0 =C2=A0 SECTION FV_IMAGE =3D FvPreMemorySilicon
+=C2=A0 }
+
+[FV.FvPreMemorySilicon]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D F0205C0E-0AD1-499C-A5F9-96BAF98248A0 +
+=C2=A0 INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPr= eMem.inf
+
+=C2=A0 !if $(SMM_REQUIRED) =3D=3D TRUE
+=C2=A0 =C2=A0 INF OvmfPkg/SmmAccess/SmmAccessPei.inf
+=C2=A0 !endif
+
+[FV.FvFspS]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D C6786443-AFCA-471B-A8FC-E8C330708F99 +
+[FV.FvPostMemorySilicon]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D EF76DFDC-2B7D-423D-BFE4-8FD4BB22E770 +
+###########################
+#
+# Stage 2 Firmware Volumes
+#
+###########################
+[FV.FvPostMemory]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D 5A1D6978-BABE-42F9-A629-F7B3B6A1E1BD +
+=C2=A0 INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+=C2=A0 INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPo= stMem.inf
+=C2=A0 INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem= .inf
+
+=C2=A0 INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+
+=C2=A0 INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntime= Dxe.inf
+=C2=A0 INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+[FV.FvBsp]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D FCA0BC4A-994D-4EF9-BD56-A8C45872C2A8 +
+###########################
+#
+# Stage 3 Firmware Volumes
+#
+###########################
+
+[FV.FvUefiBootUnCompressed]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D D2F110DB-2388-4963-BEFD-5889EEE01569 +
+=C2=A0 INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+=C2=A0 INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/Report= StatusCodeRouterRuntimeDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeH= andlerRuntimeDxe.inf
+
+=C2=A0 INF MdeModulePkg/Universal/Metronome/Metronome.inf
+=C2=A0 INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+=C2=A0 INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+=C2=A0 INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+=C2=A0 INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRun= timeDxe.inf
+=C2=A0 INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.i= nf
+=C2=A0 INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCoun= terRuntimeDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf<= br> +=C2=A0 INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf +=C2=A0 INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+=C2=A0 INF OvmfPkg/IoMmuDxe/IoMmuDxe.inf
+=C2=A0 INF OvmfPkg/PlatformDxe/Platform.inf
+
+=C2=A0 INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/English= Dxe.inf
+=C2=A0 INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutput= Dxe.inf
+=C2=A0 INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConso= leDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.in= f
+=C2=A0 INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.in= f
+=C2=A0 INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+=C2=A0 INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.= inf
+=C2=A0 INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+=C2=A0 INF ShellPkg/Application/Shell/Shell.inf
+
+=C2=A0 INF OvmfPkg/SioBusDxe/SioBusDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+=C2=A0 INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+
+
+[FV.FvUefiBoot]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D D0C15ADB-FE38-4331-841C-0E96C1B0FBFA +
+=C2=A0 INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+=C2=A0 =C2=A0FILE FV_IMAGE =3D D2F110DB-2388-4963-BEFD-5889EEE01569 {
+=C2=A0 =C2=A0 SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSI= NG_REQUIRED =3D TRUE {
+=C2=A0 =C2=A0 =C2=A0 SECTION FV_IMAGE =3D FvUefiBootUncompressed
+=C2=A0 =C2=A0 }
+=C2=A0 }
+
+
+###########################
+#
+# Stage 4 Firmware Volumes
+#
+###########################
+[FV.FvOsBoot]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D AE8F0EA0-1614-422D-ABC1-C518596F1678 +
+=C2=A0 INF OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
+
+=C2=A0 INF PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf +=C2=A0 INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+=C2=A0 INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+=C2=A0 INF FatPkg/EnhancedFatDxe/Fat.inf
+
+=C2=A0 INF MdeModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf
+=C2=A0 INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
+
+=C2=A0 # ACPI
+=C2=A0 INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+=C2=A0 INF OvmfPkg/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+=C2=A0 # Buses
+
+=C2=A0 INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+=C2=A0 INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+=C2=A0 INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+=C2=A0 INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+=C2=A0 INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+
+=C2=A0 INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
+=C2=A0 INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
+
+=C2=A0 INF OvmfPkg/SataControllerDxe/SataControllerDxe.inf
+
+=C2=A0 INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+=C2=A0 INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+=C2=A0 INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+=C2=A0 !if $(SMM_REQUIRED) =3D=3D TRUE
+=C2=A0 =C2=A0 =C2=A0 INF OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
+=C2=A0 =C2=A0 =C2=A0 INF OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.inf
+=C2=A0 =C2=A0 =C2=A0 INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+=C2=A0 =C2=A0 =C2=A0 INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+=C2=A0 =C2=A0 =C2=A0 INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLock= Box.inf
+=C2=A0 =C2=A0 =C2=A0 INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm= /ReportStatusCodeRouterSmm.inf
+=C2=A0 =C2=A0 =C2=A0 INF MdeModulePkg/Universal/StatusCodeHandler/Smm/Stat= usCodeHandlerSmm.inf
+=C2=A0 =C2=A0 =C2=A0 INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
+=C2=A0 =C2=A0 =C2=A0 INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+=C2=A0 =C2=A0 =C2=A0 INF MdeModulePkg/Universal/FaultTolerantWriteDxe/Faul= tTolerantWriteSmm.inf
+=C2=A0 =C2=A0 =C2=A0 INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFv= bServiceSmm.inf
+=C2=A0 !endif
+=C2=A0 INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+=C2=A0 INF OvmfPkg/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
+
+
+###########################
+#
+# Stage 5 Firmware Volumes
+#
+###########################
+[FV.FvSecurity]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D 1AE6AB90-9431-425B-9A92-ED2708A4E982 +=C2=A0 !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fd= f
+
+
+###########################
+#
+# Stage 6 Firmware Volumes
+#
+###########################
+[FV.FvAdvanced]
+=C2=A0 !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+=C2=A0 FvNameGuid=C2=A0 =C2=A0 =3D 936D6D65-CB6C-4B87-A51C-70D56511CB55 +
+###########################
+#
+# File Construction Rules
+#
+###########################
+!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/Boa= rdBootManagerLib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootMana= gerLib/BoardBootManagerLib.inf
new file mode 100644
index 000000000000..37425d711010
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootM= anagerLib.inf
@@ -0,0 +1,39 @@
+## @file
+#=C2=A0 The module definition file for BoardBootManagerLib.
+#
+#=C2=A0 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR&= gt;
+#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D 0x00010005
+=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D BoardBootManagerLib
+=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 3fe4b589-8bd9-46df-9322-d06fa2c278d6
+=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D DXE_DRIVER
+=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0=3D 1.0
+=C2=A0 LIBRARY_CLASS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =3D BoardBootManagerLib|DXE_DRIVER
+
+
+#
+# The following information is for reference only and not required by the = build tools.
+#
+#=C2=A0 VALID_ARCHITECTURES=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D IA= 32 X64 EBC
+#
+
+[Sources]
+=C2=A0 BoardBootManager.c
+
+[LibraryClasses]
+=C2=A0 BaseLib
+=C2=A0 UefiBootServicesTableLib
+=C2=A0 DebugLib
+=C2=A0 UefiLib
+=C2=A0 HobLib
+=C2=A0 UefiBootManagerLib
+=C2=A0 TimerLib
+
+[Packages]
+=C2=A0 MdePkg/MdePkg.dec
+=C2=A0 MdeModulePkg/MdeModulePkg.dec
+=C2=A0 MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitL= ib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.i= nf
new file mode 100644
index 000000000000..8f75d1277070
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.inf<= br> @@ -0,0 +1,29 @@
+## @file
+#=C2=A0 QemuOpenBoardPkg BoardInitLib instance
+#
+#=C2=A0 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR&= gt;
+#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+[Defines]
+=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D 0x00010005
+=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D BoardInitLib
+=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 70EE7BD9-08FF-4D0E-AA7B-4320844F939A
+=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D BASE
+=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0=3D 1.0
+=C2=A0 LIBRARY_CLASS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =3D BoardInitLib
+
+[Sources]
+=C2=A0 BoardInitLib.c
+
+[Packages]
+=C2=A0 QemuOpenBoardPkg/QemuOpenBoardPkg.dec
+=C2=A0 MdePkg/MdePkg.dec
+=C2=A0 MinPlatformPkg/MinPlatformPkg.dec
+=C2=A0 OvmfPkg/OvmfPkg.dec
+
+[LibraryClasses]
+=C2=A0 DebugLib
+=C2=A0 PcdLib
+=C2=A0 IoLib
+=C2=A0 PciCf8Lib
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQe= muFwCfgLib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/Op= enQemuFwCfgLib.inf
new file mode 100644
index 000000000000..cfabf412d5bb
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfg= Lib.inf
@@ -0,0 +1,23 @@
+## @file
+#=C2=A0 OpenQemuFwCfgLib.inf
+#
+#=C2=A0 Simple implementation of the QemuFwCfgLib that reads data from the= QEMU
+#=C2=A0 FW_CFG device
+#
+#=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl
+#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+##
Please explain what FwCfg is and how it works here= in the .inf and in the .h.
+
+[Defines]
+=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D 0x00010005
+=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D QemuFwCfgLib
+=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 70EE7BD9-08FF-4D0E-AA7B-4320844F939A
+=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D BASE
+=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0=3D 1.0
+=C2=A0 LIBRARY_CLASS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =3D OpenQemuFwCfgLib
+
+[Sources]
+=C2=A0 OpenQemuFwCfgLib.c
+
+[LibraryClasses]
+=C2=A0 IoLib
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiRepor= tFvLib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiRepor= tFvLib.inf
new file mode 100644
index 000000000000..d416f1c64061
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.= inf
@@ -0,0 +1,63 @@
+### @file
+# Component information file for the Report Firmware Volume (FV) library.<= br> +#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR= >
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D 0x00010017
+=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D PeiReportFvLib
+=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 44328FA5-E4DD-4A15-ABDF-C6584AC363D9
+=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0=3D 1.0
+=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D PEIM
+=C2=A0 LIBRARY_CLASS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =3D ReportFvLib
+
+[LibraryClasses]
+=C2=A0 BaseMemoryLib
+=C2=A0 DebugLib
+=C2=A0 HobLib
+=C2=A0 PeiServicesLib
+
+[Packages]
+=C2=A0 MdePkg/MdePkg.dec
+=C2=A0 MdeModulePkg/MdeModulePkg.dec
+=C2=A0 MinPlatformPkg/MinPlatformPkg.dec
+=C2=A0 QemuOpenBoardPkg/QemuOpenBoardPkg.dec
+
+[Sources]
+=C2=A0 PeiReportFvLib.c
+
+[Pcd]
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdBootStage=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase=C2=A0= =C2=A0## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize=C2=A0= =C2=A0## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize=C2=A0 =C2= =A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase=C2=A0 =C2= =A0 =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset=C2=A0 = =C2=A0 =C2=A0 ## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0## CONSUMES
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Platform= SecLib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Platform= SecLib.inf
new file mode 100644
index 000000000000..a4c793af05cd
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.= inf
@@ -0,0 +1,49 @@
+## @file
+#=C2=A0 PlatformSecLib for QEMU OpenBoardPkg
+#
+#=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl
+#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+
+[Defines]
+=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D 0x00010005
+=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D PlatformSecLib
+=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 37b1bddc-5a53-4f2a-af7d-b78d5e80dcbd
+=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D SEC
+=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0=3D 1.0
+=C2=A0 LIBRARY_CLASS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =3D PlatformSecLib
+
+#
+# The following information is for reference only and not required by the = build tools.
+#
+#=C2=A0 VALID_ARCHITECTURES=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D IA= 32
+#
+
+[Sources.IA32]
+=C2=A0 Ia32/SecEntry.nasm
+
+[Sources]
+=C2=A0 PlatformSecLib.c
+
+[LibraryClasses]
+=C2=A0 DebugLib
+=C2=A0 BaseLib
+=C2=A0 BaseMemoryLib
+=C2=A0 PciLib
+=C2=A0 PcdLib
+=C2=A0 HobLib
+=C2=A0 MtrrLib
+
+[Packages]
+=C2=A0 MdePkg/MdePkg.dec
+=C2=A0 UefiCpuPkg/UefiCpuPkg.dec
+=C2=A0 QemuOpenBoardPkg/QemuOpenBoardPkg.dec
+=C2=A0 IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+=C2=A0 MinPlatformPkg/MinPlatformPkg.dec
+
+[Ppis]
+=C2=A0 gTopOfTemporaryRamPpiGuid
+
+[Pcd]
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase
+=C2=A0 gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize
+=C2=A0 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei= .inf b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf new file mode 100644
index 000000000000..c800d14a02b5
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf @@ -0,0 +1,59 @@
+## @file
+#=C2=A0 PlatformInitPei
+#
+#=C2=A0 Simple PEIM for QEMU PIIX4/Q35 Memory, SMP and PCI/PCI Express ini= tialization
+#
+#=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl
+#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+
+[Defines]
+=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D 0x00010005
+=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D PlatformInitPei
+=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 82d851fe-3106-4175-8b6c-87fda1f2d0ac
+=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D PEIM
+=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0=3D 1.0
+=C2=A0 ENTRY_POINT=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D PlatformInit
+
+[Packages]
+=C2=A0 OvmfPkg/OvmfPkg.dec
+=C2=A0 MdePkg/MdePkg.dec
+=C2=A0 QemuOpenBoardPkg/QemuOpenBoardPkg.dec
+=C2=A0 UefiCpuPkg/UefiCpuPkg.dec
+
+[Sources]
+=C2=A0 PlatformInit.h
+=C2=A0 PlatformInit.c
+=C2=A0 Memory.c
+=C2=A0 Pcie.c
+=C2=A0 Pci.c
+=C2=A0 Cpu.c
+
+[LibraryClasses]
+=C2=A0 PeimEntryPoint
+=C2=A0 OpenQemuFwCfgLib
+=C2=A0 HobLib
+=C2=A0 PcdLib
+=C2=A0 PciLib
+
+[Guids]
+=C2=A0 gUefiOvmfPkgPlatformInfoGuid
+
+[Pcd]
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+=C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber
+=C2=A0 gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size
+=C2=A0 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes
+
+[FeaturePcd]
+=C2=A0 gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire
+
+[Depex]
+=C2=A0 TRUE
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Library/OpenQemuFwCfgLi= b.h b/Platform/Qemu/QemuOpenBoardPkg/Include/Library/OpenQemuFwCfgLib.h
new file mode 100644
index 000000000000..ec82cc9c89f0
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Library/OpenQemuFwCfgLib.h
@@ -0,0 +1,102 @@
+/** @file OpenQemuFwCfgLib.h
+=C2=A0 OpenQemuFwCfgLib Headers
+
+=C2=A0 Implements a minimal library to interact with Qemu FW CFG device +
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+#ifndef QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_
+#define QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_
+
+#include <PiPei.h>
+#include <Library/IoLib.h>
+
+// QEMU fw_cfg registers
+#define FW_CFG_PORT_SEL=C2=A0 =C2=A00x510
+#define FW_CFG_PORT_DATA=C2=A0 0x511
+#define FW_CFG_PORT_DMA=C2=A0 =C2=A00x514
+
+// QEMU Selectors
+#define FW_CFG_SIGNATURE=C2=A0 0x0000
+#define FW_CFG_ID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x0001
+#define FW_CFG_FILE_DIR=C2=A0 =C2=A00x0019
+
+#define FW_CFG_QEMU_SIGNATURE SIGNATURE_32('Q', 'E', '= M', 'U')
+
+typedef struct {
+=C2=A0 UINT32=C2=A0 =C2=A0 Size;
+=C2=A0 UINT16=C2=A0 =C2=A0 Select;
+=C2=A0 UINT16=C2=A0 =C2=A0 Reserved;
+=C2=A0 CHAR8=C2=A0 =C2=A0 =C2=A0Name[56];
+} QEMU_FW_CFG_FILE;
+
+/**
+=C2=A0 Checks for Qemu fw_cfg device by reading "QEMU" using the= signature selector
+
+=C2=A0 @return EFI_SUCCESS - The fw_cfg device is present
+=C2=A0 @return EFI_UNSUPPORTED - The device is absent
+ */
+EFI_STATUS
+EFIAPI
+QemuFwCfgIsPresent (
+=C2=A0 VOID
+=C2=A0 );
+
+/**
+ Sets the selector register to the specified value
+
+=C2=A0 @param[in] Selector
+
+=C2=A0 @return EFI_SUCCESS
+=C2=A0 @return EFI_UNSUPPORTED
+ */
+EFI_STATUS
+EFIAPI
+QemuFwCfgSelectItem (
+=C2=A0 IN UINT16=C2=A0 Selector
+=C2=A0 );
+
+/**
+ Reads 8 bits from the data register
+
+=C2=A0 @return UINT8
+ */
+UINT8
+EFIAPI
+QemuFwCfgRead8 (
+=C2=A0 VOID
+=C2=A0 );
+
+/**
+=C2=A0 Reads N bytes from the data register
+
+=C2=A0 @param Size
+=C2=A0 @param Buffer
+ */
+VOID
+EFIAPI
+QemuFwCfgReadBytes (
+=C2=A0 IN UINTN=C2=A0 Size,
+=C2=A0 OUT VOID=C2=A0 *Buffer
+=C2=A0 );
+
+/**
+=C2=A0 Finds a file in fw_cfg by its name
+
+=C2=A0 @param[in] String Pointer to an ASCII string to match in the databa= se
+=C2=A0 @param[out] FWConfigFile Buffer for the config file
+
+=C2=A0 @return EFI_STATUS - Entry was found, FWConfigFile is populated
+=C2=A0 @return EFI_ERROR - Entry was not found
+ */
+EFI_STATUS
+EFIAPI
+QemuFwCfgFindFile (
+=C2=A0 IN CHAR8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *String, +=C2=A0 OUT QEMU_FW_CFG_FILE=C2=A0 *FWConfigFile
+=C2=A0 );
+
+#endif // QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_
diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h = b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h
new file mode 100644
index 000000000000..7f84e5d9724b
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h
@@ -0,0 +1,59 @@
+/** @file PlatformInit.h
+=C2=A0 Headers for PlatformInitPei PEIM
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_
+#define QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_
+
+#include <PiPei.h>
+#include <Uefi.h>
+
+#define PIIX4_PCI_IO_BASE=C2=A0 0xC000
+#define PIIX4_PCI_IO_SIZE=C2=A0 0x4000
+
+#define Q35_PCI_IO_BASE=C2=A0 0x6000
+#define Q35_PCI_IO_SIZE=C2=A0 0xA000
+
+#define PCI_MMIO_TOP_ADDRESS=C2=A0 0xFC000000
+
+EFI_STATUS
+EFIAPI
+PlatformInit (
+=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 =C2=A0EFI_PEI_FILE_HANDLE=C2=A0 FileHandle,<= br> +=C2=A0 IN CONST EFI_PEI_SERVICES=C2=A0 =C2=A0 =C2=A0**PeiServices
+=C2=A0 );
+
+UINT32
+EFIAPI
+GetMemoryBelow4Gb (
+=C2=A0 VOID
+=C2=A0 );
+
+EFI_STATUS
+EFIAPI
+InstallMemory (
+=C2=A0 IN CONST EFI_PEI_SERVICES=C2=A0 **PeiServices
+=C2=A0 );
+
+EFI_STATUS
+EFIAPI
+InitializePcie (
+=C2=A0 VOID
+=C2=A0 );
+
+EFI_STATUS
+EFIAPI
+InitializePciPIIX4 (
+=C2=A0 VOID
+=C2=A0 );
+
+EFI_STATUS
+EFIAPI
+MaxCpuInit (
+=C2=A0 VOID
+=C2=A0 );
+
+#endif //QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/Boa= rdBootManager.c b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLi= b/BoardBootManager.c
new file mode 100644
index 000000000000..9fad6bc56dfd
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardBootManagerLib/BoardBootM= anager.c
@@ -0,0 +1,105 @@
+/** @file
+=C2=A0 This file include board specific boot manager callbacks
+
+=C2=A0 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR&g= t;
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PlatformBootManagerLib.h>
+#include <Library/UefiLib.h>
+#include <Library/HobLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PerformanceLib.h>
+#include <Library/BoardBootManagerLib.h>
+
+BOOLEAN=C2=A0 =C2=A0 mHotKeypressed =3D FALSE;
+EFI_EVENT=C2=A0 HotKeyEvent=C2=A0 =C2=A0 =3D NULL;
+UINTN=C2=A0 =C2=A0 =C2=A0 mBootMenuOptionNumber;
+
+/**
+=C2=A0 This function is called each second during the boot manager waits t= imeout.
+
+=C2=A0 @param TimeoutRemain=C2=A0 The remaining timeout.
+**/
+VOID
+EFIAPI
+BoardBootManagerWaitCallback (
+=C2=A0 UINT16=C2=A0 TimeoutRemain
+=C2=A0 )
+{
+=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Status;
+=C2=A0 EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL=C2=A0 *TxtInEx;
+=C2=A0 EFI_KEY_DATA=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0KeyData;
+=C2=A0 BOOLEAN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PausePressed;
+
+=C2=A0 //
+=C2=A0 // Pause on PAUSE key
+=C2=A0 //
+=C2=A0 Status =3D gBS->HandleProtocol (gST->ConsoleInHandle, &gE= fiSimpleTextInputExProtocolGuid, (VOID **)&TxtInEx);
+=C2=A0 ASSERT_EFI_ERROR (Status);
+
+=C2=A0 PausePressed =3D FALSE;
+
+=C2=A0 while (TRUE) {
+=C2=A0 =C2=A0 Status =3D TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyDat= a);
+=C2=A0 =C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 if (KeyData.Key.ScanCode =3D=3D SCAN_PAUSE) {
+=C2=A0 =C2=A0 =C2=A0 PausePressed =3D TRUE;
+=C2=A0 =C2=A0 =C2=A0 break;
+=C2=A0 =C2=A0 }
+=C2=A0 }
+
+=C2=A0 //
+=C2=A0 // Loop until non-PAUSE key pressed
+=C2=A0 //
+=C2=A0 while (PausePressed) {
+=C2=A0 =C2=A0 Status =3D TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyDat= a);
+=C2=A0 =C2=A0 if (!EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 =C2=A0 DEBUG (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG_INFO, "[PauseC= allback] %x/%x %x/%x\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 KeyData.Key.ScanCode, Key= Data.Key.UnicodeChar,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 KeyData.KeyState.KeyShift= State, KeyData.KeyState.KeyToggleState
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0);
+=C2=A0 =C2=A0 =C2=A0 PausePressed =3D (BOOLEAN)(KeyData.Key.ScanCode =3D= =3D SCAN_PAUSE);
+=C2=A0 =C2=A0 }
+=C2=A0 }
+}
+
+/**
+=C2=A0 The function is called when no boot option could be launched,
+=C2=A0 including platform recovery options and options pointing to applica= tions
+=C2=A0 built into firmware volumes.
+
+=C2=A0 If this function returns, BDS attempts to enter an infinite loop. +**/
+VOID
+EFIAPI
+BoardBootManagerUnableToBoot (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 Status;
+=C2=A0 EFI_BOOT_MANAGER_LOAD_OPTION=C2=A0 BootDeviceList;
+=C2=A0 CHAR16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 OptionName[sizeof ("Boot####")];
+
+=C2=A0 if (mBootMenuOptionNumber =3D=3D LoadOptionNumberUnassigned) {
+=C2=A0 =C2=A0 return;
+=C2=A0 }
+
+=C2=A0 UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x&quo= t;, mBootMenuOptionNumber);
+=C2=A0 Status =3D EfiBootManagerVariableToLoadOption (OptionName, &Boo= tDeviceList);
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 return;
+=C2=A0 }
+
+=C2=A0 for ( ;;) {
+=C2=A0 =C2=A0 EfiBootManagerBoot (&BootDeviceList);
+=C2=A0 }
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitL= ib.c b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c new file mode 100644
index 000000000000..ae7c77915b5e
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c @@ -0,0 +1,222 @@
+/** @file
+=C2=A0 Board initialization library
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/BoardInitLib.h>
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciCf8Lib.h>
+#include <IndustryStandard/Pci.h>
+#include <IndustryStandard/I440FxPiix4.h>
+#include <IndustryStandard/Q35MchIch9.h>
+#include <Library/HobLib.h>
+
+#define QEMU_IO_DEBUG_MAGIC=C2=A0 0xE9
+
+/**
+=C2=A0 This board service detects the board type.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board was detected successfully= .
+=C2=A0 @retval EFI_NOT_FOUND The board could not be detected.
+**/
+EFI_STATUS
+EFIAPI
+BoardDetect (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 UINT16=C2=A0 DeviceID, VendorID;
+
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardDetect()\n"));
+
+=C2=A0 DeviceID =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, PCI_DEVICE= _ID_OFFSET));
+=C2=A0 VendorID =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, PCI_VENDOR= _ID_OFFSET));
+
Please add a comment explaining what you're doin= g here.
+=C2=A0 switch (DeviceID) {
+=C2=A0 =C2=A0 case INTEL_82441_DEVICE_ID:
+=C2=A0 =C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "PIIX4\n"));
+=C2=A0 =C2=A0 =C2=A0 return EFI_SUCCESS;
+
+=C2=A0 =C2=A0 case INTEL_Q35_MCH_DEVICE_ID:
+=C2=A0 =C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "ICH9\n"));
+=C2=A0 =C2=A0 =C2=A0 return EFI_SUCCESS;
+
Possibly edit these DEBUG such that they're not = just stray chipset names in the log.
+=C2=A0 =C2=A0 default:
+=C2=A0 =C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "Unable to detect board (De= vice id %u Vendor ID %u)\n", DeviceID, VendorID));
+=C2=A0 =C2=A0 =C2=A0 return EFI_NOT_FOUND;
+=C2=A0 }
+}
+
+/**
+=C2=A0 This board service initializes board-specific debug devices.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0Board-specific debug initialization= was successful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardDebugInit (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+BoardBootModeDetect (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardBootModeDetect()\n"));
+=C2=A0 return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+=C2=A0 A hook for board-specific initialization prior to memory initializa= tion.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitBeforeMemoryInit (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitBeforeMemoryInit()\n")); +=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 A hook for board-specific initialization after memory initializatio= n.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitAfterMemoryInit (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitAfterMemoryInit()\n"));
+=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 A hook for board-specific initialization prior to disabling tempora= ry RAM.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitBeforeTempRamExit (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitBeforeTempRamExit()\n")); +=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 A hook for board-specific initialization after disabling temporary = RAM.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitAfterTempRamExit (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitAfterTempRamExit()\n")); +=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 A hook for board-specific initialization prior to silicon initializ= ation.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitBeforeSiliconInit (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitBeforeSiliconInit()\n")); +=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 A hook for board-specific initialization after silicon initializati= on.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitAfterSiliconInit (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitAfterSiliconInit()\n")); +=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 A hook for board-specific initialization after PCI enumeration.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitAfterPciEnumeration (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitAfterPciEnumeration()\n"));=
+=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 A hook for board-specific functionality for the ReadyToBoot event.<= br> +
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitReadyToBoot (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitReadyToBoot()\n"));
+=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 A hook for board-specific functionality for the ExitBootServices ev= ent.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0The board initialization was succes= sful.
+=C2=A0 @retval EFI_NOT_READY The board has not been detected yet.
+**/
+EFI_STATUS
+EFIAPI
+BoardInitEndOfFirmware (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 DEBUG ((DEBUG_INFO, "BoardInitEndOfFirmware()\n"));
+=C2=A0 return EFI_SUCCESS;
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQe= muFwCfgLib.c b/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/Open= QemuFwCfgLib.c
Why is this path .../OpenQemuFwCfgLib w= hen the package is called QemuOpenBoardPkg?
new file mode 100644
index 000000000000..c02c263f03b3
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/OpenQemuFwCfgLib/OpenQemuFwCfg= Lib.c
@@ -0,0 +1,130 @@
+/** @file
+=C2=A0 Qemu FW CFG device library
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/OpenQemuFwCfgLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+
+/**
+=C2=A0 Reads 8 bits from the data register
+
+=C2=A0 @retval UINT8
+**/
+UINT8
+EFIAPI
+QemuFwCfgRead8 (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 return IoRead8 (FW_CFG_PORT_DATA);
+}
+
+/**
+=C2=A0 Sets the selector register to the specified value
+
+=C2=A0 @param Selector
+
+=C2=A0 @retval EFI_SUCCESS
+=C2=A0 @retval EFI_UNSUPPORTED
+**/
+EFI_STATUS
+EFIAPI
+QemuFwCfgSelectItem (
+=C2=A0 IN UINT16=C2=A0 Selector
+=C2=A0 )
+{
+=C2=A0 UINT16=C2=A0 WritenSelector;
+
+=C2=A0 WritenSelector =3D IoWrite16 (FW_CFG_PORT_SEL, Selector);
+
+=C2=A0 if (WritenSelector !=3D Selector) {
+=C2=A0 =C2=A0 return EFI_UNSUPPORTED;
+=C2=A0 }
+
+=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 Reads N bytes from the data register
+
+=C2=A0 @param Size
+=C2=A0 @param Buffer
+**/
+VOID
+EFIAPI
+QemuFwCfgReadBytes (
+=C2=A0 IN UINTN=C2=A0 Size,
+=C2=A0 OUT VOID=C2=A0 *Buffer
+=C2=A0 )
+{
+=C2=A0 IoReadFifo8 (FW_CFG_PORT_DATA, Size, Buffer);
+}
+
+/**
+=C2=A0 Checks for Qemu fw_cfg device by reading "QEMU" using the= signature selector
+
+=C2=A0 @retval EFI_SUCCESS - The fw_cfg device is present
+=C2=A0 @retval EFI_UNSUPPORTED - The device is absent
+**/
+EFI_STATUS
+EFIAPI
+QemuFwCfgIsPresent (
+=C2=A0 )
+{
+=C2=A0 EFI_STATUS=C2=A0 Status;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 Control;
+
+=C2=A0 Status =3D QemuFwCfgSelectItem (FW_CFG_SIGNATURE);
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 return Status;
+=C2=A0 }
+
+=C2=A0 QemuFwCfgReadBytes (4, &Control);
+=C2=A0 if (Control !=3D FW_CFG_QEMU_SIGNATURE) {
+=C2=A0 =C2=A0 ASSERT (Control =3D=3D FW_CFG_QEMU_SIGNATURE);
+=C2=A0 =C2=A0 return EFI_UNSUPPORTED;
+=C2=A0 }
+
+=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 Finds a file in fw_cfg by its name
+
+=C2=A0 @param String Pointer to an ASCII string to match in the database +=C2=A0 @param FWConfigFile Buffer for the config file
+=C2=A0 @retval EFI_STATUS - Entry was found, FWConfigFile is populated
+=C2=A0 @retval EFI_ERROR - Entry was not found
+**/
+EFI_STATUS
+EFIAPI
+QemuFwCfgFindFile (
+=C2=A0 IN CHAR8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *String, +=C2=A0 OUT QEMU_FW_CFG_FILE=C2=A0 *FWConfigFile
+=C2=A0 )
+{
+=C2=A0 QEMU_FW_CFG_FILE=C2=A0 FirmwareConfigFile;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 FilesCount;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Idx;
+
+=C2=A0 QemuFwCfgSelectItem (FW_CFG_FILE_DIR);
+=C2=A0 QemuFwCfgReadBytes (sizeof (UINT32), &FilesCount);
+
+=C2=A0 FilesCount =3D SwapBytes32 (FilesCount);
+
+=C2=A0 for (Idx =3D 0; Idx < FilesCount; Idx++) {
+=C2=A0 =C2=A0 QemuFwCfgReadBytes (sizeof (QEMU_FW_CFG_FILE), &Firmware= ConfigFile);
+=C2=A0 =C2=A0 if (AsciiStrCmp ((CHAR8 *)&(FirmwareConfigFile.Name), St= ring) =3D=3D 0) {
+=C2=A0 =C2=A0 =C2=A0 FirmwareConfigFile.Select =3D SwapBytes16 (FirmwareCo= nfigFile.Select);
+=C2=A0 =C2=A0 =C2=A0 FirmwareConfigFile.Size=C2=A0 =C2=A0=3D SwapBytes32 (= FirmwareConfigFile.Size);
+=C2=A0 =C2=A0 =C2=A0 CopyMem (FWConfigFile, &FirmwareConfigFile, sizeo= f (QEMU_FW_CFG_FILE));
+=C2=A0 =C2=A0 =C2=A0 return EFI_SUCCESS;
+=C2=A0 =C2=A0 }
+=C2=A0 }
+
+=C2=A0 return EFI_UNSUPPORTED;
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiRepor= tFvLib.c b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportF= vLib.c
new file mode 100644
index 000000000000..809e69ce4381
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.= c
@@ -0,0 +1,285 @@
+/** @file PeiReportFvLib.c
+=C2=A0 Source code file for Report Firmware Volume (FV) library
+
+=C2=A0 Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.&= lt;BR>
+
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ReportFvLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Ppi/FirmwareVolumeInfo2.h>
+
+// Use a FV pointer PCD to get a pointer to the FileSystemGuid in the FV h= eader
+#define PCD_TO_FV_HEADER_FILE_SYSTEM_GUID(Pcd)=C2=A0 =C2=A0(&((EFI_FIR= MWARE_VOLUME_HEADER *)(UINTN) PcdGet32 (Pcd))->FileSystemGuid)
+
+/**
+=C2=A0 Reports FVs necessary for MinPlarform pre-memory initialization
+ */
+VOID
+ReportPreMemFv (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Index=C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D 0;
+=C2=A0 EFI_PEI_PPI_DESCRIPTOR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*Descriptor =3D NULL;
+=C2=A0 EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI=C2=A0 *Ppi=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =3D NULL;
+=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Status=C2=A0 =C2=A0 =C2=A0 =3D EFI_SUCCES= S;
+=C2=A0 EFI_FIRMWARE_VOLUME_HEADER=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*FvHead= er=C2=A0 =C2=A0=3D NULL;
+=C2=A0 EFI_BOOT_MODE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 BootMode=C2=A0 =C2=A0 =3D BOOT_WITH_FULL_CONFIGURA= TION;
+
+=C2=A0 Status =3D PeiServicesGetBootMode (&BootMode);
+=C2=A0 ASSERT_EFI_ERROR (Status);
+
+=C2=A0 DEBUG_CODE (
+=C2=A0 =C2=A0 for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) {
+=C2=A0 =C2=A0 =C2=A0 Status =3D PeiServicesLocatePpi (&gEfiPeiFirmware= VolumeInfo2PpiGuid, Index, &Descriptor, (VOID**) &Ppi);
+=C2=A0 =C2=A0 =C2=A0 if (!EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi= ->FvInfo;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Found FV at 0x%x, si= ze 0x%x\n", FvHeader, FvHeader->FvLength));
+=C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+=C2=A0 );
+
+=C2=A0 //
+=C2=A0 // FvBspPreMemory and FvPreMemory are required for all stages.
+=C2=A0 //
+
+=C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvBspPreMemory - 0x%x, 0x%x\= n", PcdGet32 (PcdFlashFvBspPreMemoryBase), PcdGet32 (PcdFlashFvBspPreM= emorySize)));
+=C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (P= cdFlashFvBspPreMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdFlashFvB= spPreMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvBspPreMemorySize= ),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvPreMemory - 0x%x, 0x%x\n&q= uot;, PcdGet32 (PcdFlashFvPreMemoryBase), PcdGet32 (PcdFlashFvPreMemorySize= )));
+=C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (P= cdFlashFvPreMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdFlashFvP= reMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvPreMemorySize),<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 //
+=C2=A0 // In API mode, do not publish FSP FV.
+=C2=A0 //
+=C2=A0 if (!PcdGetBool (PcdFspWrapperBootMode)) {
+=C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 // FvFspT may be required for all stages
+=C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n= ", PcdGet32 (PcdFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize)));
+=C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_= GUID (PcdFlashFvFspTBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdF= lashFvFspTBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvFspTSize)= ,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 // FvFspM required for stage 2 and above
+=C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 if (PcdGet8 (PcdBootStage) >=3D 2) {
+=C2=A0 =C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvFspM - 0x%x,= 0x%x\n", PcdGet32 (PcdFlashFvFspMBase), PcdGet32 (PcdFlashFvFspMSize)= ));
+=C2=A0 =C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_= SYSTEM_GUID (PcdFlashFvFspMBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet3= 2 (PcdFlashFvFspMBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvFs= pMSize),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+=C2=A0 =C2=A0 }
+=C2=A0 }
+
+=C2=A0 //
+=C2=A0 // FvAdvanced not needed until stage 6
+=C2=A0 //
+=C2=A0 if (PcdGet8 (PcdBootStage) >=3D 6) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvAdvancedPreMemory -= 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), PcdGet32 (= PcdFlashFvAdvancedPreMemorySize)));
+=C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_= GUID (PcdFlashFvAdvancedPreMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdF= lashFvAdvancedPreMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvAdvancedP= reMemorySize),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+=C2=A0 }
+}
+/**
+=C2=A0 Reports FVs for MinPlarform post-memory initialization
+=C2=A0 This function also publish FV HOBs to ensure DXE phase is aware of = those FVs
+ */
+VOID
+ReportPostMemFv (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Index=C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D 0;
+=C2=A0 EFI_PEI_PPI_DESCRIPTOR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*Descriptor =3D NULL;
+=C2=A0 EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI=C2=A0 *Ppi=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =3D NULL;
+=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Status=C2=A0 =C2=A0 =C2=A0 =3D EFI_SUCCES= S;
+=C2=A0 EFI_FIRMWARE_VOLUME_HEADER=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*FvHead= er=C2=A0 =C2=A0=3D NULL;
+
+=C2=A0 DEBUG_CODE (
+=C2=A0 =C2=A0 for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) {
+=C2=A0 =C2=A0 =C2=A0 Status =3D PeiServicesLocatePpi (&gEfiPeiFirmware= VolumeInfo2PpiGuid, Index, &Descriptor, (VOID**) &Ppi);
+=C2=A0 =C2=A0 =C2=A0 if (!EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi= ->FvInfo;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Found FV at 0x%x, si= ze 0x%x\n", FvHeader, FvHeader->FvLength));
+=C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+=C2=A0 );
+
+=C2=A0 //
+=C2=A0 // FvFspS, FvPostMemory, and FvBsp may be required for completing s= tage 2
+=C2=A0 //
+=C2=A0 if (PcdGet8 (PcdBootStage) >=3D 2) {
+=C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 // In API mode, do not publish FSP FV.
+=C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 if (!PcdGetBool (PcdFspWrapperBootMode)) {
+=C2=A0 =C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvFspS - 0x%x,= 0x%x\n", PcdGet32 (PcdFlashFvFspSBase), PcdGet32 (PcdFlashFvFspSSize)= ));
+=C2=A0 =C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_= SYSTEM_GUID (PcdFlashFvFspSBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet3= 2 (PcdFlashFvFspSBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvFs= pSSize),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, = 0x%x\n", PcdGet32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPost= MemorySize)));
+=C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_= GUID (PcdFlashFvPostMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdF= lashFvPostMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvPostMemor= ySize),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "%Build FlashFvPostMemory FV Hob at= %Lx \n", (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvPostMemoryBase)));=
+
+=C2=A0 =C2=A0 BuildFvHob (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (EFI_PHYSICAL_ADDR= ESS)PcdGet32 (PcdFlashFvPostMemoryBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlash= FvPostMemorySize)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvBsp - 0x%x, 0x%x\n&= quot;, PcdGet32 (PcdFlashFvBspBase), PcdGet32 (PcdFlashFvBspSize)));
+=C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_= GUID (PcdFlashFvBspBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdF= lashFvBspBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvBspSize),=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+=C2=A0 }
+
+=C2=A0 //
+=C2=A0 // FvUefiBoot required for completing stage 3
+=C2=A0 //
+=C2=A0 if (PcdGet8 (PcdBootStage) >=3D 3) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x= %x\n", PcdGet32 (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBoot= Size)));
+=C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_= GUID (PcdFlashFvUefiBootBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdF= lashFvUefiBootBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvUefiBootS= ize),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "%Build FlashFvUefiBoot FV Hob at %= Lx \n", (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvUefiBootBase)));
+
+=C2=A0 =C2=A0 BuildFvHob (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (EFI_PHYSICAL_ADDR= ESS)PcdGet32 (PcdFlashFvUefiBootBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlash= FvUefiBootSize)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+=C2=A0 }
+
+=C2=A0 //
+=C2=A0 // FvOsBoot required for completing stage 4
+=C2=A0 //
+=C2=A0 if (PcdGet8 (PcdBootStage) >=3D 4) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x= \n", PcdGet32 (PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize))= );
+=C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_= GUID (PcdFlashFvOsBootBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdF= lashFvOsBootBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvOsBootSiz= e),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "%Build FlashFvOsBoot FV Hob at %Lx= \n", (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvUefiBootBase)));
+
+=C2=A0 =C2=A0 BuildFvHob (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (EFI_PHYSICAL_ADDR= ESS)PcdGet32 (PcdFlashFvOsBootBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlash= FvOsBootSize)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+=C2=A0 }
+
+=C2=A0 //
+=C2=A0 // FvSecurity required for completing stage 5
+=C2=A0 //
+=C2=A0 if (PcdGet8 (PcdBootStage) >=3D 5) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x= %x\n", PcdGet32 (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecurity= Size)));
+=C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_= GUID (PcdFlashFvSecurityBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdF= lashFvSecurityBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvSecurityS= ize),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+=C2=A0 }
+
+=C2=A0 //
+=C2=A0 // FvAdvanced required for completing stage 6
+=C2=A0 //
+=C2=A0 if (PcdGet8 (PcdBootStage) >=3D 6) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x= %x\n", PcdGet32 (PcdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvanced= Size)));
+=C2=A0 =C2=A0 PeiServicesInstallFvInfo2Ppi (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PCD_TO_FV_HEADER_FILE_SYSTEM_= GUID (PcdFlashFvAdvancedBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (VOID *)(UINTN)PcdGet32 (PcdF= lashFvAdvancedBase),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet32 (PcdFlashFvAdvancedS= ize),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+=C2=A0 }
+
+=C2=A0 //
+=C2=A0 // Report resource related HOB for flash FV to reserve space in GCD= and memory map
+=C2=A0 //
+
+=C2=A0 BuildResourceDescriptorHob (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 EFI_RESOURCE_MEMORY_MAPPED_IO,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (EFI_RESOURCE_ATTRIBUTE_PRESENT=C2=A0 =C2= =A0 |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EFI_RESOURCE_ATTRIBUTE_INITIALIZED |<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN)PcdGet32 (PcdFlashAreaBaseAddress),<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (UINTN)PcdGet32 (PcdFlashAreaSize)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 BuildMemoryAllocationHob (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 (UINTN)PcdGet32 (PcdFlashAreaBaseAddress),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 (UINTN)PcdGet32 (PcdFlashAreaSize),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 EfiMemoryMappedIO
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 );
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Platform= SecLib.c b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSe= cLib.c
new file mode 100644
index 000000000000..ff632494c4a3
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.= c
@@ -0,0 +1,140 @@
+/** @file
+=C2=A0 PlatformSecLib library functions
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/TemporaryRamSupport.h>
+#include <Library/PcdLib.h>
+#include <Ppi/PeiCoreFvLocation.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HobLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/PlatformSecLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/IoLib.h>
+
+#include <Library/LocalApicLib.h>
+
+EFI_PEI_CORE_FV_LOCATION_PPI=C2=A0 gEfiPeiCoreFvLocationPpi =3D {
+=C2=A0 (VOID *)FixedPcdGet32 (PcdFlashFvFspMBase)
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR=C2=A0 mPeiSecPlatformPpi[] =3D {
+=C2=A0 //
+=C2=A0 // This must be the second PPI in the list because it will be patch= ed in SecPlatformMain ();
+=C2=A0 //
+=C2=A0 {
+=C2=A0 =C2=A0 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINAT= E_LIST,
+=C2=A0 =C2=A0 &gTopOfTemporaryRamPpiGuid,
+=C2=A0 =C2=A0 NULL
+=C2=A0 }
+};
+
+EFI_PEI_PPI_DESCRIPTOR=C2=A0 gEfiPeiCoreFvLocationDescriptor =3D {
+=C2=A0 EFI_PEI_PPI_DESCRIPTOR_PPI,
+=C2=A0 &gEfiPeiCoreFvLocationPpiGuid,
+=C2=A0 &gEfiPeiCoreFvLocationPpi
+};
+
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+=C2=A0 IN OUT=C2=A0 =C2=A0EFI_SEC_PEI_HAND_OFF=C2=A0 *SecCoreData
+=C2=A0 )
+{
+=C2=A0 // Use half of available heap size for PpiList
+=C2=A0 EFI_PEI_PPI_DESCRIPTOR=C2=A0 *PpiList;
+
+=C2=A0 PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + (= UINTN)SecCoreData->PeiTemporaryRamSize / 2);
+
+=C2=A0 CopyMem (PpiList, &gEfiPeiCoreFvLocationDescriptor, sizeof (EFI= _PEI_PPI_DESCRIPTOR));
+
+=C2=A0 CopyMem (&PpiList[1], &mPeiSecPlatformPpi, sizeof (EFI_PEI_= PPI_DESCRIPTOR));
+
+=C2=A0 // Patch the top of RAM PPI
+=C2=A0 PpiList[1].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase= + SecCoreData->TemporaryRamSize);
+=C2=A0 DEBUG ((DEBUG_INFO, "SecPlatformMain(): Top of memory %p\n&quo= t;, PpiList[1].Ppi));
+
+=C2=A0 return PpiList;
+}
+
+/**
+=C2=A0 This interface conveys state information out of the Security (SEC) = phase into PEI.
+
+=C2=A0 @param=C2=A0 PeiServices=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Pointer to the PEI Services Table.
+=C2=A0 @param=C2=A0 StructureSize=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0Pointer to the variable describing size of the input buffer.
+=C2=A0 @param=C2=A0 PlatformInformationRecord Pointer to the EFI_SEC_PLATF= ORM_INFORMATION_RECORD.
+
+=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0The dat= a was successfully returned.
+=C2=A0 @retval EFI_BUFFER_TOO_SMALL=C2=A0 The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+=C2=A0 IN CONST EFI_PEI_SERVICES=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 **PeiServices,
+=C2=A0 IN OUT=C2=A0 =C2=A0UINT64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *StructureSize,
+=C2=A0 OUT=C2=A0 =C2=A0EFI_SEC_PLATFORM_INFORMATION_RECORD=C2=A0 *Platform= InformationRecord
+=C2=A0 )
+{
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 TopOfTemporaryRam;
+=C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 *TopOfRamPpi;
+=C2=A0 EFI_STATUS=C2=A0 Status;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 Count;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 *BistStart;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 Length;
+
+=C2=A0 Status =3D (*PeiServices)->LocatePpi (PeiServices, &gTopOfTe= mporaryRamPpiGuid, 0, NULL, &TopOfRamPpi);
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 return Status;
+=C2=A0 }
+
+=C2=A0 TopOfTemporaryRam =3D (UINT32)TopOfRamPpi;
+
+=C2=A0 DEBUG ((DEBUG_INFO, "SecPlatformInformation: Top of memory is = %p\n", TopOfRamPpi));
+
+=C2=A0 Count=C2=A0 =3D *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)); +=C2=A0 Length =3D Count * sizeof (UINT32);
+
+=C2=A0 BistStart =3D (UINT32 *)(TopOfTemporaryRam - sizeof (UINT32) - Leng= th);
+
+=C2=A0 DEBUG ((DEBUG_INFO, "SecPlatformInformation: Found %u processo= rs with BISTs starting at %p\n", Count, BistStart));
+
+=C2=A0 if (*StructureSize < Length) {
+=C2=A0 =C2=A0 *StructureSize =3D Length;
+=C2=A0 =C2=A0 return EFI_BUFFER_TOO_SMALL;
+=C2=A0 }
+
+=C2=A0 CopyMem (PlatformInformationRecord, BistStart, Length);
+=C2=A0 *StructureSize =3D Length;
+
+=C2=A0 // Mask the PIC to avoid any interruption down the line
+=C2=A0 IoWrite8 (0x21, 0xff);
+=C2=A0 IoWrite8 (0xA1, 0xff);
+
+=C2=A0 DEBUG ((DEBUG_INFO, "Initialize APIC Timer \n"));
+=C2=A0 InitializeApicTimer (0, MAX_UINT32, TRUE, 5);
+
+=C2=A0 DEBUG ((DEBUG_INFO, "Disable APIC Timer interrupt\n")); +=C2=A0 DisableApicTimerInterrupt ();
+
+=C2=A0 return EFI_SUCCESS;
+}
+
+/**
+=C2=A0 This interface disables temporary memory in SEC Phase.
+**/
+VOID
+EFIAPI
+SecPlatformDisableTemporaryMemory (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 return;
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c b/Platfor= m/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c
new file mode 100644
index 000000000000..ff3e008aa96b
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c
@@ -0,0 +1,56 @@
+/** @file Cpu.c
+=C2=A0 CPU Count initialization
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformInit.h"
+#include <IndustryStandard/Pci.h>
+#include <Library/PciCf8Lib.h>
+#include <Library/OpenQemuFwCfgLib.h>
+#include <IndustryStandard/QemuFwCfg.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h&= gt;
+#include <Library/DebugLib.h>
+#include <IndustryStandard/Acpi30.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+
+/**
+=C2=A0 Probe Qemu FW CFG device for current CPU count and report to MpInit= Lib
+
+=C2=A0 @return EFI_SUCCESS Detection was successful
+=C2=A0 @retval EFI_UNSUPPORTED Qemu FW CFG device is not present
+ */
+EFI_STATUS
+EFIAPI
+MaxCpuInit (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 BootCpuCount;
+=C2=A0 EFI_STATUS=C2=A0 Status;
+
+=C2=A0 Status =3D QemuFwCfgIsPresent ();
+
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "QemuFwCfg not present, unable to = detect CPU count \n"));
+=C2=A0 =C2=A0 ASSERT_EFI_ERROR (Status);
+=C2=A0 =C2=A0 return EFI_UNSUPPORTED;
+=C2=A0 }
+
+=C2=A0 Status =3D QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
+
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 return Status;
+=C2=A0 }
+
+=C2=A0 QemuFwCfgReadBytes (sizeof (BootCpuCount), &BootCpuCount);
+
+=C2=A0 PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);
+
+=C2=A0 PcdSet32S (PcdCpuMaxLogicalProcessorNumber, 64);
+
+=C2=A0 return EFI_SUCCESS;
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c b/Plat= form/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c
new file mode 100644
index 000000000000..8e378c17d851
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c
@@ -0,0 +1,244 @@
+/** @file Memory.c
+=C2=A0 Memory probing and installation
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PlatformInit.h>
+#include <Library/DebugLib.h>
+#include <Library/OpenQemuFwCfgLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/HobLib.h>
+#include <IndustryStandard/E820.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+/**
+=C2=A0 Return the memory size below 4GB.
+
+=C2=A0 @return UINT32
+**/
+UINT32
+EFIAPI
+GetMemoryBelow4Gb (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 EFI_E820_ENTRY64=C2=A0 E820Entry;
+=C2=A0 QEMU_FW_CFG_FILE=C2=A0 FwCfgFile;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Processed;
+=C2=A0 UINT64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Size;
+=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 Status;
+
+=C2=A0 Status =3D QemuFwCfgIsPresent ();
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 return Status;
+=C2=A0 }
+
+=C2=A0 Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgFile)= ;
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 return Status;
+=C2=A0 }
+
+=C2=A0 Size =3D 0;
+=C2=A0 QemuFwCfgSelectItem (FwCfgFile.Select);
+=C2=A0 for (Processed =3D 0; Processed < FwCfgFile.Size / sizeof (EFI_E= 820_ENTRY); Processed++) {
+=C2=A0 =C2=A0 QemuFwCfgReadBytes (sizeof (EFI_E820_ENTRY), &E820Entry)= ;
+=C2=A0 =C2=A0 if (E820Entry.Type !=3D EfiAcpiAddressRangeMemory) {
+=C2=A0 =C2=A0 =C2=A0 continue;
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 if (E820Entry.BaseAddr + E820Entry.Length < SIZE_4GB) { +=C2=A0 =C2=A0 =C2=A0 Size +=3D E820Entry.Length;
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 return Size;
+=C2=A0 =C2=A0 }
+=C2=A0 }
+
+=C2=A0 return Size;
+}
+
+/**
+=C2=A0 Reserve an MMIO region
+
+=C2=A0 @param Start
+=C2=A0 @param Length
+**/
+STATIC
+VOID
+ReserveMmioRegion (
+=C2=A0 EFI_PHYSICAL_ADDRESS=C2=A0 Start,
+=C2=A0 UINT64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Lengt= h
+=C2=A0 )
+{
+=C2=A0 EFI_RESOURCE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Resource= Type;
+=C2=A0 EFI_RESOURCE_ATTRIBUTE_TYPE=C2=A0 ResourceAttributes;
+
+=C2=A0 ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURC= E_ATTRIBUTE_UNCACHEABLE | EFI_RESOURCE_ATTRIBUTE_TESTED;
+=C2=A0 ResourceType=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D EFI_RESOURCE_MEMORY_MAPP= ED_IO;
+
+=C2=A0 BuildResourceDescriptorHob (
+=C2=A0 =C2=A0 ResourceType,
+=C2=A0 =C2=A0 ResourceAttributes,
+=C2=A0 =C2=A0 Start,
+=C2=A0 =C2=A0 Length
+=C2=A0 =C2=A0 );
+}
+
+/**
+=C2=A0 Install EFI memory by probing Qemu FW CFG devices for valid E820 en= tries
+=C2=A0 It also reserve space for MMIO regions such as VGA, BIOS and APIC +
+=C2=A0 @param PeiServices
+=C2=A0 @retval EFI_SUCCESS Memory initialization succeded
+=C2=A0 @retval EFI_UNSUPPORTED Installation failed (etc/e820 file was not = found)
+=C2=A0 @retval EFI_NOT_FOUND=C2=A0 Qemu FW CFG device is not present
+**/
+EFI_STATUS
+EFIAPI
+InstallMemory (
+=C2=A0 IN CONST EFI_PEI_SERVICES=C2=A0 **PeiServices
+=C2=A0 )
+{
+=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Status;
+=C2=A0 CONST EFI_PEI_SERVICES=C2=A0 =C2=A0 =C2=A0 =C2=A0**PeiServicesTable= ;
+=C2=A0 EFI_E820_ENTRY64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0E82= 0Entry;
+=C2=A0 EFI_E820_ENTRY64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Lar= gestE820Entry;
+=C2=A0 QEMU_FW_CFG_FILE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0FwC= fgFile;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0Processed;
+=C2=A0 BOOLEAN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 ValidMemory;
+=C2=A0 EFI_RESOURCE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Resource= Type;
+=C2=A0 EFI_RESOURCE_ATTRIBUTE_TYPE=C2=A0 ResourceAttributes;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0MemoryBelow4G;
+=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0RequiredBySmm;
+
+=C2=A0 Status =3D QemuFwCfgIsPresent ();
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "QEMU fw_cfg device is not present\= n"));
+=C2=A0 =C2=A0 return EFI_NOT_FOUND;
+=C2=A0 } else {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "QEMU fw_cfg device is present\n&qu= ot;));
+=C2=A0 }
+
+=C2=A0 Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgFile)= ;
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "etc/e820 was not found \n"))= ;
+=C2=A0 =C2=A0 return EFI_UNSUPPORTED;
+=C2=A0 }
+
+=C2=A0 MemoryBelow4G =3D GetMemoryBelow4Gb ();
+
+=C2=A0 LargestE820Entry.Length =3D 0;
+=C2=A0 QemuFwCfgSelectItem (FwCfgFile.Select);
+=C2=A0 for (Processed =3D 0; Processed < FwCfgFile.Size / sizeof (EFI_E= 820_ENTRY); Processed++) {
+=C2=A0 =C2=A0 QemuFwCfgReadBytes (sizeof (EFI_E820_ENTRY), &E820Entry)= ;
+
+=C2=A0 =C2=A0 ValidMemory=C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D E820Entry.Type = =3D=3D EfiAcpiAddressRangeMemory;
+=C2=A0 =C2=A0 ResourceType=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D EFI_RESOURCE_MEMO= RY_RESERVED;
+=C2=A0 =C2=A0 ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_= RESOURCE_ATTRIBUTE_UNCACHEABLE | EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+=C2=A0 =C2=A0 if (ValidMemory) {
+=C2=A0 =C2=A0 =C2=A0 if (FeaturePcdGet (PcdSmmSmramRequire) && (E8= 20Entry.BaseAddr + E820Entry.Length =3D=3D MemoryBelow4G)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 RequiredBySmm =3D PcdGet16 (PcdQ35TsegMbytes) = * SIZE_1MB;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (E820Entry.Length < RequiredBySmm) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG ((
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG_ERROR,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "Error: There's not eno= ugh memory below TOLUD for SMM (%lx < %x)\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 E820Entry.Length,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 RequiredBySmm
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 E820Entry.Length -=3D RequiredBySmm;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG ((
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG_INFO,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "SMM is enabled! Stealing [%lx, %l= x](%u MiB) for SMRAM...\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 E820Entry.BaseAddr + E820Entry.Length,<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 E820Entry.BaseAddr + E820Entry.Length += RequiredBySmm - 1,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 PcdGet16 (PcdQ35TsegMbytes)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ));
+=C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 ResourceType=C2=A0 =C2=A0 =C2=A0 =C2=A0=3D EFI_RESOUR= CE_SYSTEM_MEMORY;
+=C2=A0 =C2=A0 =C2=A0 ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT= |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0EFI_RESOURCE_ATTRIBUTE_TESTED;
+
+=C2=A0 =C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 =C2=A0 // Lets handle the lower 1MB in a special way
+=C2=A0 =C2=A0 =C2=A0 //
+
+=C2=A0 =C2=A0 =C2=A0 if (E820Entry.BaseAddr =3D=3D 0) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 // 0 - 0xa0000 is system memory, everything ab= ove that up to 1MB is not
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 // Note that we check if we actually have 1MB<= br> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 //
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 BuildResourceDescriptorHob (
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ResourceType,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ResourceAttributes,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 MIN (0xa0000, E820Entry.Length)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 E820Entry.BaseAddr +=3D BASE_1MB;
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 E820Entry.Length=C2=A0 =C2=A0-=3D MIN (BASE_1M= B, E820Entry.Length);
+=C2=A0 =C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 =C2=A0 // Note that we can only check if this is the largest= entry after reserving everything we have to reserve
+=C2=A0 =C2=A0 =C2=A0 //
+
+=C2=A0 =C2=A0 =C2=A0 if ((E820Entry.Length > LargestE820Entry.Length) &= amp;& (E820Entry.BaseAddr + E820Entry.Length <=3D SIZE_4GB)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 CopyMem (&LargestE820Entry, &E820Entry= , sizeof (EFI_E820_ENTRY64));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG ((
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG_INFO,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "New largest entry for PEI: BaseAd= dress %lx, Size %lx\n",
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 LargestE820Entry.BaseAddr,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 LargestE820Entry.Length
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ));
+=C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 BuildResourceDescriptorHob (
+=C2=A0 =C2=A0 =C2=A0 ResourceType,
+=C2=A0 =C2=A0 =C2=A0 ResourceAttributes,
+=C2=A0 =C2=A0 =C2=A0 E820Entry.BaseAddr,
+=C2=A0 =C2=A0 =C2=A0 E820Entry.Length
+=C2=A0 =C2=A0 =C2=A0 );
+
+=C2=A0 =C2=A0 DEBUG ((
+=C2=A0 =C2=A0 =C2=A0 DEBUG_INFO,
+=C2=A0 =C2=A0 =C2=A0 "Processed E820 entry [%lx, %lx] with type %x\n&= quot;,
+=C2=A0 =C2=A0 =C2=A0 E820Entry.BaseAddr,
+=C2=A0 =C2=A0 =C2=A0 E820Entry.BaseAddr + E820Entry.Length - 1,
+=C2=A0 =C2=A0 =C2=A0 E820Entry.Type
+=C2=A0 =C2=A0 =C2=A0 ));
+=C2=A0 }
+
+=C2=A0 ASSERT (LargestE820Entry.Length !=3D 0);
+=C2=A0 DEBUG ((
+=C2=A0 =C2=A0 DEBUG_INFO,
+=C2=A0 =C2=A0 "Largest memory chunk found: [%lx, %lx]\n",
+=C2=A0 =C2=A0 LargestE820Entry.BaseAddr,
+=C2=A0 =C2=A0 LargestE820Entry.BaseAddr + LargestE820Entry.Length - 1
+=C2=A0 =C2=A0 ));
+
+=C2=A0 PeiServicesTable =3D GetPeiServicesTablePointer ();
+
+=C2=A0 Status =3D (*PeiServices)->InstallPeiMemory (PeiServicesTable, L= argestE820Entry.BaseAddr, LargestE820Entry.Length);
+
+=C2=A0 ASSERT_EFI_ERROR (Status);
+
+=C2=A0 // Reserve architectural PC MMIO regions
+=C2=A0 // VGA space + BIOS shadow mapping
Let's b= e consistent with other platforms (at least Intel ones) and use
/= /
// Comment
//
as is already used in other p= arts of the platform. This applies to all other non-conforming comments in = the patch.
+=C2=A0 ReserveMmioRegion (0xa0000, 0x100000 - 0xa0000);
+=C2=A0 // IO APIC and LAPIC space
+=C2=A0 ReserveMmioRegion (0xfec00000, 0xff000000 - 0xfec00000);
+=C2=A0 return Status;
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c b/Platfor= m/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c
new file mode 100644
index 000000000000..a66cbf6005fb
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c
@@ -0,0 +1,59 @@
+/** @file Pci.c
+=C2=A0 PCI Initialization for PIIX4 QEMU
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformInit.h"
+#include <IndustryStandard/Pci.h>
+#include <Library/PciCf8Lib.h>
+#include <Library/OpenQemuFwCfgLib.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h&= gt;
+#include <Library/DebugLib.h>
+#include <IndustryStandard/Acpi30.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+
+/**
+=C2=A0 Initialize PCI support for QEMU PIIX4 machine
+
+=C2=A0 It also publishes PCI MMIO and IO ranges PCDs for OVMF PciHostBridg= eLib
+
+=C2=A0 @retval EFI_SUCCESS Initialization was a success
+=C2=A0 @retval EFI_UNSUPPORTED Initialization failed (Memory below 4Gb pro= bing failed)
+**/
+EFI_STATUS
+EFIAPI
+InitializePciPIIX4 (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 UINTN=C2=A0 PciIoBase;
+=C2=A0 UINTN=C2=A0 PciIoSize;
+=C2=A0 UINTN=C2=A0 PciMmio32Base;
+=C2=A0 UINTN=C2=A0 PciMmio32Size;
+
+=C2=A0 PciIoBase =3D PIIX4_PCI_IO_BASE;
+=C2=A0 PciIoSize =3D PIIX4_PCI_IO_SIZE;
+
+=C2=A0 PcdSet64S (PcdPciIoBase, PciIoBase);
+=C2=A0 PcdSet64S (PcdPciIoSize, PciIoSize);
+
Explain why we're doing this.
+=C2=A0 PciMmio32Base =3D (UINTN) GetMemoryBelow4Gb ();
+
+=C2=A0 if (PciMmio32Base =3D=3D 0) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "Unable to detect memory below 4Gb= \n"));
+=C2=A0 =C2=A0 ASSERT (PciMmio32Base !=3D 0);
+=C2=A0 =C2=A0 return EFI_UNSUPPORTED;
+=C2=A0 }
+
+=C2=A0 DEBUG ((DEBUG_ERROR, "Memory below 4Gb: %x \n", PciMmio32= Base));
+=C2=A0 PciMmio32Size =3D PCI_MMIO_TOP_ADDRESS - PciMmio32Base;
+
+=C2=A0 PcdSet64S (PcdPciMmio32Base, PciMmio32Base);
+=C2=A0 PcdSet64S (PcdPciMmio32Size, PciMmio32Size);
+
+=C2=A0 return EFI_SUCCESS;
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c b/Platfo= rm/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c
new file mode 100644
index 000000000000..a61fd6447e91
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c
@@ -0,0 +1,91 @@
+/** @file Pcie.c
+=C2=A0 PCI Express initialization for QEMU Q35
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformInit.h"
+#include <IndustryStandard/Pci.h>
+#include <Library/PciCf8Lib.h>
+#include <IndustryStandard/Q35MchIch9.h>
+#include <Library/OpenQemuFwCfgLib.h>
+#include <IndustryStandard/QemuFwCfg.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h&= gt;
+#include <Library/DebugLib.h>
+#include <IndustryStandard/Acpi30.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+
+/**
+=C2=A0 Initialize PCI Express support for QEMU Q35 system
+=C2=A0 It also publishes PCI MMIO and IO ranges PCDs for OVMF PciHostBridg= eLib
+=C2=A0 @retval EFI_SUCCESS Initialization was successful
+**/
+EFI_STATUS
+EFIAPI
+InitializePcie (
+=C2=A0 VOID
+=C2=A0 )
+{
+=C2=A0 UINTN=C2=A0 PciBase;
+=C2=A0 UINTN=C2=A0 PciSize;
+=C2=A0 UINTN=C2=A0 PciIoBase;
+=C2=A0 UINTN=C2=A0 PciIoSize;
+
+=C2=A0 union {
+=C2=A0 =C2=A0 UINT64=C2=A0 =C2=A0 Uint64;
+=C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 Uint32[2];
+=C2=A0 } PciExBarBase;
+
+=C2=A0 PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); +
+=C2=A0 // Build a reserved memory space for PCIE MMIO
+=C2=A0 BuildResourceDescriptorHob (
+=C2=A0 =C2=A0 EFI_RESOURCE_MEMORY_RESERVED,
+=C2=A0 =C2=A0 EFI_RESOURCE_ATTRIBUTE_PRESENT |
+=C2=A0 =C2=A0 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+=C2=A0 =C2=A0 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+=C2=A0 =C2=A0 EFI_RESOURCE_ATTRIBUTE_TESTED,
+=C2=A0 =C2=A0 PciExBarBase.Uint64,
+=C2=A0 =C2=A0 SIZE_256MB
+=C2=A0 =C2=A0 );
+
+=C2=A0 BuildMemoryAllocationHob (
+=C2=A0 =C2=A0 PciExBarBase.Uint64,
+=C2=A0 =C2=A0 SIZE_256MB,
+=C2=A0 =C2=A0 EfiReservedMemoryType
+=C2=A0 =C2=A0 );
+
+=C2=A0 // Clear lower 32 bits of register
+=C2=A0 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);
+
+=C2=A0 // Program PCIE MMIO Base address in MCH PCIEXBAR register
+=C2=A0 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Ui= nt32[1]);
+
+=C2=A0 // Enable 256Mb MMIO space
+=C2=A0 PciWrite32 (
+=C2=A0 =C2=A0 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),
+=C2=A0 =C2=A0 PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_= EN
+=C2=A0 =C2=A0 );
+
+=C2=A0 // Disable Pci MMIO above 4Gb
+=C2=A0 PcdSet64S (PcdPciMmio64Size, 0);
+
+=C2=A0 // Set Pci MMIO space below 4GB
Nit: It should= be PCI and PCIe.
+=C2=A0 PciBase =3D (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + SIZE_256= MB);
+=C2=A0 PciSize =3D PCI_MMIO_TOP_ADDRESS - PciBase;
+
+=C2=A0 PcdSet64S (PcdPciMmio32Base, PciBase);
+=C2=A0 PcdSet64S (PcdPciMmio32Size, PciSize);
+
+=C2=A0 // Set Pci IO port range
+=C2=A0 PciIoBase =3D Q35_PCI_IO_BASE;
+=C2=A0 PciIoSize =3D Q35_PCI_IO_SIZE;
+
+=C2=A0 PcdSet64S (PcdPciIoBase, PciIoBase);
+=C2=A0 PcdSet64S (PcdPciIoSize, PciIoSize);
+
+=C2=A0 return EFI_SUCCESS;
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c = b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c
new file mode 100644
index 000000000000..f69518301cd2
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c
@@ -0,0 +1,67 @@
+/** @file PlarformInit.c
+=C2=A0 Platform initialization PEIM for QEMU
+
+=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.
+=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformInit.h"
+#include <Library/PeimEntryPoint.h>
+#include <Library/PeiServicesLib.h>
+#include "Library/DebugLib.h"
+#include <Library/PlatformInitLib.h>
+#include <Library/HobLib.h>
+#include <Library/PciCf8Lib.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Q35MchIch9.h>
+
+EFI_STATUS
+EFIAPI
+PlatformInit (
+=C2=A0 IN=C2=A0 =C2=A0 =C2=A0 =C2=A0EFI_PEI_FILE_HANDLE=C2=A0 FileHandle,<= br> +=C2=A0 IN CONST EFI_PEI_SERVICES=C2=A0 =C2=A0 =C2=A0**PeiServices
+=C2=A0 )
+{
+=C2=A0 EFI_STATUS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Status; +=C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0DeviceId;
+=C2=A0 EFI_HOB_PLATFORM_INFO=C2=A0 *EfiPlatformInfo;
+
+=C2=A0 // Install permanent memory
+=C2=A0 Status =3D InstallMemory (PeiServices);
+
+=C2=A0 if (EFI_ERROR (Status)) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "Memory installation failed\n"= ;));
+=C2=A0 =C2=A0 return Status;
+=C2=A0 } else {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Memory installation success\n"= ;));
+=C2=A0 }
+
+=C2=A0 // Report CPU core count to MPInitLib
+=C2=A0 MaxCpuInit ();
+
+=C2=A0 EfiPlatformInfo =3D AllocateZeroPool (sizeof (EFI_HOB_PLATFORM_INFO= ));
+=C2=A0 if (EfiPlatformInfo =3D=3D NULL) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_ERROR, "Failed to allocate pool for EFI_H= OB_PLATFORM_INFO\n"));
+=C2=A0 =C2=A0 return EFI_UNSUPPORTED;
+=C2=A0 }
+
+=C2=A0 // Report gUefiOvmfPkgPlatformInfo HOB with only the necessary data= for OVMF
+=C2=A0 DeviceId =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, PCI_DEVICE= _ID_OFFSET));
+=C2=A0 DEBUG ((DEBUG_INFO, "Building gUefiOvmfPkgPlatformInfoGuid wit= h Host bridge dev ID %x \n", DeviceId));
+=C2=A0 (*EfiPlatformInfo).HostBridgeDevId =3D DeviceId;
+
+=C2=A0 BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, EfiPlatformInf= o, sizeof (EFI_HOB_PLATFORM_INFO));
+
+=C2=A0 PcdSet16S (PcdOvmfHostBridgePciDevId, DeviceId);
+
+=C2=A0 // Initialize PCI or PCIe based on current emulated system
+=C2=A0 if (DeviceId =3D=3D INTEL_Q35_MCH_DEVICE_ID) {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Q35: Initialize PCIe\n")); +=C2=A0 =C2=A0 return InitializePcie ();
+=C2=A0 } else {
+=C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "PIIX4: Initialize PCI\n")); +=C2=A0 =C2=A0 return InitializePciPIIX4 ();
+=C2=A0 }
+}
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc b/= Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc
new file mode 100644
index 000000000000..29f49f914171
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc
@@ -0,0 +1,85 @@
+## @file
+# Flashmap and variable definitions for QemuOpenBoardPkg FVs and FD
+#
+# @copyright
+# Copyright (C) 2022 Jehl Th=C3=A9o
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# These three items are tightly coupled.
+# The spare area size must be >=3D the first two areas.
+# The total size must match the size in the EFI_FIRMWARE_VOLUME_HEADER. +# The NvStorageVariableSize must also match the VARIABLE_STORE_HEADER size= .
+# The EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER doesn't have size info.<= br> +#
+# There isn't really a benefit to a larger spare area unless the FLASH= device
+# block size is larger than the size specified.
+#
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=C2=A0 =C2= =A0 =3D 0x0003C000
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=C2=A0 = =3D 0x00004000
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=C2=A0 =C2= =A0 =3D gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfi= MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+#
+# Early FV
+#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0=3D 0x00081000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D 0x00040000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 0x00010000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 0x00040000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 0x00020000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 0x00080000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D 0x00020000
+
+#
+# Later FV
+#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D 0x00400000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D 0x00100000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D 0x00080000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize= - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize - gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize - gEfiMdeModulePkgTok= enSpaceGuid.PcdFlashNvStorageFtwSpareSize - gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvPreMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTok= enSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFs= pMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvBspPreMemorySize - gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+
+#
+# Calculate Offsets Once (Do not modify)
+# This layout is specified by the EDK II Minimum Platform Archicture speci= fication.
+# Each offset is the prior region's offset plus the prior region's= size.
+#
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset=C2=A0 = =C2=A0=3D 0x00000000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset=C2=A0 =C2=A0+ g= EfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset=C2=A0 = =C2=A0=3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset += gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtw= SpareOffset=C2=A0 =C2=A0+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageF= twSpareSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOf= fset=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpaceGuid.PcdF= lashFvAdvancedSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuri= tyOffset=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpaceGuid.= PcdFlashFvSecuritySize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffs= et=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvOsBootSize
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D gMinPlatformPkgTokenSpaceGuid.PcdFlas= hFvUefiBootOffset=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenS= paceGuid.PcdFlashFvUefiBootSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ gMinPlatformPkgTokenSpace= Guid.PcdFlashFvBspSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPo= stMemoryOffset=C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvPostMemorySize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFs= pSOffset=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvFspSSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFs= pMOffset=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvFspMSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset=C2=A0 =C2= =A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpaceGuid.PcdF= lashFvFspTSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0=3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemor= yOffset=C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPr= eMemorySize
+
+#
+# Calculate base addresses
+#
+
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase=C2=A0 =C2= =A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase=C2=A0 = =3D gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase=C2=A0 =C2= =A0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase=C2=A0 =C2= =A0 =3D gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase=C2= =A0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBase= Address=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedOffset
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvanc= edBase=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSe= curityBase=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenS= paceGuid.PcdFlashFvSecuritySize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBoot= Base=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgToken= SpaceGuid.PcdFlashFvOsBootSize
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D gMinPlatformPkgTokenSpaceGuid.= PcdFlashFvUefiBootBase=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatf= ormPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase=C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0+ gMinPlatformPk= gTokenSpaceGuid.PcdFlashFvBspSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFla= shFvPostMemoryBase=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgToken= SpaceGuid.PcdFlashFvPostMemorySize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFla= shFvFspSBase=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFla= shFvFspMBase=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase=C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpac= eGuid.PcdFlashFvFspTSize
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0=3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreM= emoryBase=C2=A0 =C2=A0 =C2=A0 =C2=A0 + gMinPlatformPkgTokenSpaceGuid.PcdFla= shFvBspPreMemorySize
diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/Sec= Entry.nasm b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/Sec= Entry.nasm
new file mode 100644
index 000000000000..bd90a466f790
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/SecEntry.n= asm
@@ -0,0 +1,117 @@
+;-------------------------------------------------------------------------= -----
+;=C2=A0 @file SecEntry
+;=C2=A0 Sec entry implementation
Nit: SEC
<= blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-l= eft:1px solid rgb(204,204,204);padding-left:1ex"> +;
+;=C2=A0 Copyright (c) 2022 Th=C3=A9o Jehl
+;=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;-------------------------------------------------------------------------= -----
+
+CODE_SEG equ CodeSegDescriptor - GDT_START
+DATA_SEG equ DataSegDescriptor - GDT_START
+
+extern ASM_PFX(SecStartup)
+
+extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
+extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
+
+SECTION .text
+
+BITS 16
+align 4
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+=C2=A0 cli
+=C2=A0 ; Save the BIST in mm0
+=C2=A0 movd mm0, eax
+=C2=A0 mov esi, GDT_Descriptor
+=C2=A0 db 66h
+=C2=A0 lgdt [cs:si]
+
+=C2=A0 mov=C2=A0 =C2=A0 =C2=A0eax, cr0
+=C2=A0 or=C2=A0 =C2=A0 =C2=A0 eax, 1
+=C2=A0 mov=C2=A0 =C2=A0 =C2=A0cr0, eax
+
+=C2=A0 mov ax, DATA_SEG
+=C2=A0 mov ds, ax
+=C2=A0 mov es, ax
+=C2=A0 mov fs, ax
+=C2=A0 mov gs, ax
+=C2=A0 mov ss, ax
+
+=C2=A0 mov esi, ProtectedModeEntryLinearAddress
+
+=C2=A0 jmp dword far [cs:si]
+
+BITS 32
+align 4
+ProtectedModeEntry:
+=C2=A0 PROTECTED_MODE equ $
+
+=C2=A0 mov ecx, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
+=C2=A0 mov edx, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
+
+=C2=A0 ;Initialize the stack at the end of base + size
Nit: space between ; and Initialize
+=C2=A0 mov esp, ecx
+=C2=A0 add esp, edx
+
+=C2=A0 ; TODO: Multiprocessor support
Remove this TOD= O and figure out if we want to actually keep BISTs or not (not like we'= re ever getting a bad one anyway).
+=C2=A0 push 1
+=C2=A0 ; For now, we push the BIST once
+=C2=A0 movd eax, mm0
+=C2=A0 push eax
+=C2=A0 ; Code in PlatformSecLib will look up this information we've ju= st pushed
+=C2=A0 ;=C2=A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D TOP OF = MEMORY =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=C2=A0 ;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 Count of BISTs
+=C2=A0 ;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 BISTs[1..n]
+=C2=A0 ;=C2=A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D REST OF= MEMORY =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
+=C2=A0 ; Each BIST is always a DWORD in size
+
+=C2=A0 mov edi, 0xFFFFFFFC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0;BFV
+
+=C2=A0 push DWORD [edi]=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ;Passes B= FV
+
+=C2=A0 push ecx=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 ;Passes RAM size
+
+=C2=A0 push edx=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 ;Passes RAM base
+
+=C2=A0 call ASM_PFX(SecStartup)
+
+align 8
+NULL_SEGMENT=C2=A0 =C2=A0 equ $ - GDT_START
+GDT_START:
+
+NullSegDescriptor:
+=C2=A0 dd 0x0
+=C2=A0 dd 0x0
+
+=C2=A0 CODE_SEL=C2=A0 =C2=A0 =C2=A0 =C2=A0 equ $ - GDT_START
+
+CodeSegDescriptor:
+=C2=A0 dw 0xFFFF
+=C2=A0 dw 0x0
+=C2=A0 db 0x0
+=C2=A0 db 0x9B
+=C2=A0 db 0xCF
+=C2=A0 db 0x0
+
+=C2=A0 DATA_SEL=C2=A0 =C2=A0 =C2=A0 =C2=A0 equ $ - GDT_START
+
+DataSegDescriptor:
+=C2=A0 dw 0xFFFF
+=C2=A0 dw 0x0
+=C2=A0 db 0x0
+=C2=A0 db 0x93
+=C2=A0 db 0xCF
+=C2=A0 db 0x0
+
+GDT_END:
+
+GDT_Descriptor:
+=C2=A0 dw GDT_END - GDT_START - 1
+=C2=A0 dd GDT_START
+
+ProtectedModeEntryLinearAddress:
+ProtectedModeEntryLinear:
+=C2=A0 DD=C2=A0 =C2=A0 =C2=A0 ProtectedModeEntry=C2=A0 ; Offset of our 32 = bit code
+=C2=A0 DW=C2=A0 =C2=A0 =C2=A0 CODE_SEL
diff --git a/Platform/Qemu/QemuOpenBoardPkg/README.md b/Platform/Qemu/QemuO= penBoardPkg/README.md
new file mode 100644
index 000000000000..e1238c1f4e3e
--- /dev/null
+++ b/Platform/Qemu/QemuOpenBoardPkg/README.md
@@ -0,0 +1,53 @@
+# QemuOpenBoardPkg
+
+This project brings UEFI support to QEMU x86_64 following the MinPlatform = specification.
+
+## Capabilities
+
+- Supports IA-32 and hybrid X64 (IA32 PEI Core and X64 DXE Core)
+- Modern QEMU (Tested on 7.0.0)
+=C2=A0 - PIIX4 and Q35 machines
+- Boot UEFI Linux
+- Boot UEFI Windows
+
+## How to build
+
+### Pre-requesites
+
+- EDK2
+=C2=A0 - How to setup a local tree: https://github.com/tianocore/tianocore.github.io/wiki/Get= ting-Started-with-EDK-II
+
+- EDK2 Platforms
+=C2=A0 - https://github.com/tianocore/edk2-platforms=
+
+- Environnements variables:
+=C2=A0 - WORKSPACE set to your current workspace
+=C2=A0 - PACKAGES_PATH should contain path to:
+=C2=A0 =C2=A0 - edk2
+=C2=A0 =C2=A0 - edk2-platforms
+=C2=A0 =C2=A0 - edk2-platforms/Platform/Intel
+=C2=A0 =C2=A0 - edk2-platforms/Platform/Qemu
+=C2=A0 =C2=A0 - edk2-platforms/Silicon/Intel
+
+Currently QemuOpenBoardPkg's PEI Core is 32 bits only, DXE supports ei= ther 32 bits or 64 bits
+
+QemuOpenBoardPkg (IA32 PEI - IA32 DXE)
+
+```build -a IA32 -D PEI_ARCH=3DIA32 -D DXE_ARCH=3DIA32```
+
+QemuOpenBoardPkg (IA32 PEI - X64 DXE)
+
+```build -a IA32 -a X64 -D PEI_ARCH=3DIA32 -D DXE_ARCH=3DX64```
+
+## How to use
+
+Using qemu-system-x86_64, use
+
+```-bios <path to QemuOpenBoard FV>```
+
+To redirect serial output to the console
+
+```-serial stdio```
+
+## Important notes
+- Secure boot is not yet available due to QemuOpenBoardPkg NVRAM storage n= ot being persistent yet.
--
2.32.1 (Apple Git-133)



--
Pedro Falcato
--000000000000f925e905e7682046--