From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-vs1-f50.google.com (mail-vs1-f50.google.com [209.85.217.50]) by mx.groups.io with SMTP id smtpd.web12.33490.1658180998052809501 for ; Mon, 18 Jul 2022 14:49:58 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Sb5g5Cys; spf=pass (domain: gmail.com, ip: 209.85.217.50, mailfrom: pedro.falcato@gmail.com) Received: by mail-vs1-f50.google.com with SMTP id 125so1308939vsd.5 for ; Mon, 18 Jul 2022 14:49:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Wsmix648FjUCiejwsIYwoWN+6ZSVgBWad01hPZ280AU=; b=Sb5g5CysErpvvWNvwk+7SLSxZ2zhwnKWe/ZfVoASwFZmSyx+cEBhDosjievyHaoUWO xYwzLH5mrzua6waAtlBzV4ejIWx1iZl0zgmtF356dFU0tqqQctOXwHF/gqn4wo8IIYzZ Shlk/TfZnp60XpS7t3V1sGwnToDGkkY4UEZom7NP7s8kHKWiNrwErVfYUZZfJCx9n4NX tUo4gj/OeJ+0T5cTcUQNcm4evFJBxBTNHq+mUl5EK07TITk1G+ON35UDuPFRvtVq4jEq 6ECYuin7jp9hFloigFCrvGk04vMqBXVatxkjKZqb+2w/p0PcPY2f7qYi3ZpwKFrHBF9H VXFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Wsmix648FjUCiejwsIYwoWN+6ZSVgBWad01hPZ280AU=; b=fJy1hbtBPuWM4c7i3dDehwL6sXcLr4HIlAc13CKDhIz+4GR2vYUhCSx8V0YEcWX3ua uMofEGej/eLJ/FcrH6rTfrB4F4QLvOwhalUGzh7lK0bikCHZlP9atxIne1HQ6FwZ9dNa iHgQjT8/hj2kE8mDFevQP5lqJxSAJdumsPQAI4g56cLsKSk3PCV6rYcyfh9tNmydl+6W 7Mr01RDMPG8oONULV/B6V9zXyLdshnya/g0rcb9ZKADrauRDXOcwLPw7+ZUbDbgyX6Yc hDRE6abzsRBSZ/CV7JKLK9d/i6dZHho0sMkaKYvTUeq7GSxqGVBuwqWefuAgBMBx0Lu+ z4Vg== X-Gm-Message-State: AJIora8rcg+1dsrY3sGvsZ6GdDOpL0vkdTsjAs7yJmlmwlxpIX6fWNuB z9Ado4MZakvaEEftZo6WflGl/7tdA7FqCb+k9nCoTXoT4s4= X-Google-Smtp-Source: AGRyM1vWQedQlcZ4Zzn91OWM6l74iejToDsZ7AjTE/Yuqd3I3wYJQMgvgf4bE/DMoCS5qrtKZSPvG5iFub/ALBd1VGM= X-Received: by 2002:a67:d602:0:b0:357:3eb9:eb0c with SMTP id n2-20020a67d602000000b003573eb9eb0cmr9968766vsj.62.1658180996707; Mon, 18 Jul 2022 14:49:56 -0700 (PDT) MIME-Version: 1.0 References: <20220714200428.1989-1-chasel.chiu@intel.com> In-Reply-To: From: "Pedro Falcato" Date: Mon, 18 Jul 2022 22:49:44 +0100 Message-ID: Subject: Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support. To: edk2-devel-groups-io , Nate DeSimone Cc: "Chiu, Chasel" , "Zhang, Hongbin1" , "Zeng, Star" Content-Type: multipart/alternative; boundary="000000000000483baf05e41b59cd" --000000000000483baf05e41b59cd Content-Type: text/plain; charset="UTF-8" On Mon, Jul 18, 2022 at 10:40 PM Nate DeSimone < nathaniel.l.desimone@intel.com> wrote: > Hi Chasel, > > Please see comments inline. Here is a summary of my feedback: > > #1) IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm - line 34 - Bug: eax > should be rax > #2) IntelFsp2Pkg/Include/FspEas/FspApi.h - Various unnecessary whitespace > changes that make the file look worse than before. > #3) IntelFsp2Pkg/Include/Guid/FspHeaderFile.h - Why indent the #pragma > lines? > > Thanks, > Nate > > > -----Original Message----- > > From: Chiu, Chasel > > Sent: Thursday, July 14, 2022 1:04 PM > > To: devel@edk2.groups.io > > Cc: Zhang, Hongbin1 ; Desimone, Nathaniel L > > ; Zeng, Star ; > Chiu, > > Chasel > > Subject: [PATCH] IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM support. > > > > From: Hongbin1 Zhang > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3993 > > Add FSP-I API entry point for SMM support. > > > > Cc: Nate DeSimone > > Cc: Star Zeng > > Signed-off-by: Chasel Chiu > > Signed-off-by: Hongbin1 Zhang > > --- > > IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 13 +++++++++++++ > > IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf | 54 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm | 44 > ++++++++++++++++++++++++++++++++++++++++++++ > > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm | 44 > ++++++++++++++++++++++++++++++++++++++++++++ > > IntelFsp2Pkg/Include/FspEas/FspApi.h | 57 > ++++++++++++++++++++++++++++++++++++++------------------- > > IntelFsp2Pkg/Include/FspGlobalData.h | 53 > ++++++++++++++++++++++++++++------------------------- > > IntelFsp2Pkg/Include/Guid/FspHeaderFile.h | 22 > +++++++++++++++------- > > IntelFsp2Pkg/IntelFsp2Pkg.dsc | 1 + > > IntelFsp2Pkg/Tools/GenCfgOpt.py | 26 > ++++++++++++++++---------- > > IntelFsp2Pkg/Tools/SplitFspBin.py | 6 +++--- > > 10 files changed, 256 insertions(+), 64 deletions(-) > > > > diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > > index e22a88cc84..35d223a404 100644 > > --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > > +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > > @@ -71,6 +71,19 @@ FspApiCallingCheck ( > > Status = EFI_INVALID_PARAMETER; > > } > > } > > + } else if (ApiIdx == FspSmmInitApiIndex) { > > + // > > + // FspSmmInitApiIndex check > > + // > > + if ((FspData == NULL) || ((UINTN)FspData == MAX_ADDRESS) || > ((UINTN)FspData == MAX_UINT32)) { > > + Status = EFI_UNSUPPORTED; > > + } else { > > + if (FspData->Signature != FSP_GLOBAL_DATA_SIGNATURE) { > > + Status = EFI_UNSUPPORTED; > > + } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, > ApiParam))) { > > + Status = EFI_INVALID_PARAMETER; > > + } > > + } > > } else { > > Status = EFI_UNSUPPORTED; > > } > > diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf > b/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf > > new file mode 100644 > > index 0000000000..d31576c00b > > --- /dev/null > > +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf > > @@ -0,0 +1,54 @@ > > +## @file > > +# Sec Core for FSP > > +# > > +# Copyright (c) 2022, Intel Corporation. All rights reserved.
> > +# > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > +# > > +## > > + > > +[Defines] > > + INF_VERSION = 0x00010005 > > + BASE_NAME = FspSecCoreI > > + FILE_GUID = 558782b5-782d-415e-ab9e-0ceb79dc3425 > > + MODULE_TYPE = SEC > > + VERSION_STRING = 1.0 > > + > > +# > > +# The following information is for reference only and not required by > the build tools. > > +# > > +# VALID_ARCHITECTURES = IA32 X64 > > +# > > + > > +[Sources] > > + SecFspApiChk.c > > + SecFsp.h > > + > > +[Sources.X64] > > + X64/FspApiEntryI.nasm > > + X64/FspApiEntryCommon.nasm > > + X64/FspHelper.nasm > > + > > +[Sources.IA32] > > + Ia32/FspApiEntryI.nasm > > + Ia32/FspApiEntryCommon.nasm > > + Ia32/FspHelper.nasm > > + > > +[Binaries.Ia32] > > + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + IntelFsp2Pkg/IntelFsp2Pkg.dec > > + > > +[LibraryClasses] > > + BaseMemoryLib > > + DebugLib > > + BaseLib > > + PciCf8Lib > > + SerialPortLib > > + FspSwitchStackLib > > + FspCommonLib > > + FspSecPlatformLib > > + > > + > > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm > > new file mode 100644 > > index 0000000000..e9365d6832 > > --- /dev/null > > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm > > @@ -0,0 +1,44 @@ > > +;; @file > > +; Provide FSP API entry points. > > +; > > +; Copyright (c) 2022, Intel Corporation. All rights reserved.
> > +; SPDX-License-Identifier: BSD-2-Clause-Patent > > +;; > > + > > + SECTION .text > > + > > +; > > +; Following functions will be provided in C > > +; > > +extern ASM_PFX(FspApiCommon) > > + > > > +;---------------------------------------------------------------------------- > > +; FspApiCommonContinue API > > +; > > +; This is the FSP API common entry point to resume the FSP execution > > +; > > > +;---------------------------------------------------------------------------- > > +global ASM_PFX(FspApiCommonContinue) > > +ASM_PFX(FspApiCommonContinue): > > + jmp $ > > + > > > +;---------------------------------------------------------------------------- > > +; FspSmmInit API > > +; > > +; This FSP API will notify the FSP about the different phases in the > boot > > +; process > > +; > > > +;---------------------------------------------------------------------------- > > +global ASM_PFX(FspSmmInitApi) > > +ASM_PFX(FspSmmInitApi): > > + mov eax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex > > + jmp ASM_PFX(FspApiCommon) > > + > > > +;---------------------------------------------------------------------------- > > +; Module Entrypoint API > > > +;---------------------------------------------------------------------------- > > +global ASM_PFX(_ModuleEntryPoint) > > +ASM_PFX(_ModuleEntryPoint): > > + jmp $ > > + ; Add reference to APIs so that it will not be optimized by compiler > > + jmp ASM_PFX(FspSmmInitApi) > > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm > > new file mode 100644 > > index 0000000000..e9365d6832 > > --- /dev/null > > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm > > @@ -0,0 +1,44 @@ > > +;; @file > > +; Provide FSP API entry points. > > +; > > +; Copyright (c) 2022, Intel Corporation. All rights reserved.
> > +; SPDX-License-Identifier: BSD-2-Clause-Patent > > +;; > > + > > + SECTION .text > > + > > +; > > +; Following functions will be provided in C > > +; > > +extern ASM_PFX(FspApiCommon) > > + > > > +;---------------------------------------------------------------------------- > > +; FspApiCommonContinue API > > +; > > +; This is the FSP API common entry point to resume the FSP execution > > +; > > > +;---------------------------------------------------------------------------- > > +global ASM_PFX(FspApiCommonContinue) > > +ASM_PFX(FspApiCommonContinue): > > + jmp $ > > + > > > +;---------------------------------------------------------------------------- > > +; FspSmmInit API > > +; > > +; This FSP API will notify the FSP about the different phases in the > boot > > +; process > > +; > > > +;---------------------------------------------------------------------------- > > +global ASM_PFX(FspSmmInitApi) > > +ASM_PFX(FspSmmInitApi): > > + mov eax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex > > This is a bug. It should be: > > mov rax, 7 ; FSP_API_INDEX.FspSmmInitApiIndex > Hi Nate, This is not actually a problem, a 32-bit mov to a 32-bit register in long mode will zero the upper part. > > Note that IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm compares > ApiIndex numbers using rax, so it is important to make sure that the upper > 32-bits are zero: > > > https://github.com/tianocore/edk2/blob/c966204049f3d5dae6d5e587ddc298c684142c5c/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm#L65 > > > + jmp ASM_PFX(FspApiCommon) > > + > > > +;---------------------------------------------------------------------------- > > +; Module Entrypoint API > > > +;---------------------------------------------------------------------------- > > +global ASM_PFX(_ModuleEntryPoint) > > +ASM_PFX(_ModuleEntryPoint): > > + jmp $ > > + ; Add reference to APIs so that it will not be optimized by compiler > > + jmp ASM_PFX(FspSmmInitApi) > > diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h > b/IntelFsp2Pkg/Include/FspEas/FspApi.h > > index b36bc2b9ae..1d6c2fb63d 100644 > > --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h > > +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h > > @@ -135,18 +135,18 @@ typedef struct { > > /// > > /// Revision of the structure is 2 for this version of the > specification. > > /// > > - UINT8 Revision; > > - UINT8 Reserved[3]; > > + UINT8 Revision; > > + UINT8 Reserved[3]; > > Any reason for these whitespace changes? It looks worse than before. > > > /// > > /// Length of the structure in bytes. The current value for this > field is 32. > > /// > > - UINT32 Length; > > + UINT32 Length; > > Any reason for this whitespace change? It looks worse than before. > > > /// > > /// FspDebugHandler Optional debug handler for the bootloader to > receive debug messages > > /// occurring during FSP execution. > > /// > > - EFI_PHYSICAL_ADDRESS FspDebugHandler; > > - UINT8 Reserved1[16]; > > + EFI_PHYSICAL_ADDRESS FspDebugHandler; > > + UINT8 Reserved1[16]; > > Any reason for these whitespace changes? It looks worse than before. > > > } FSPT_ARCH2_UPD; > > > > /// > > @@ -197,37 +197,37 @@ typedef struct { > > /// > > /// Revision of the structure is 3 for this version of the > specification. > > /// > > - UINT8 Revision; > > - UINT8 Reserved[3]; > > + UINT8 Revision; > > + UINT8 Reserved[3]; > > Any reason for these whitespace changes? It looks worse than before. > > > /// > > /// Length of the structure in bytes. The current value for this > field is 64. > > /// > > - UINT32 Length; > > + UINT32 Length; > > Any reason for this whitespace change? It looks worse than before. > > > /// > > /// Pointer to the temporary stack base address to be > > /// consumed inside FspMemoryInit() API. > > /// > > - EFI_PHYSICAL_ADDRESS StackBase; > > + EFI_PHYSICAL_ADDRESS StackBase; > > Any reason for this whitespace change? It looks worse than before. > > > /// > > /// Temporary stack size to be consumed inside > > /// FspMemoryInit() API. > > /// > > - UINT64 StackSize; > > + UINT64 StackSize; > > Any reason for this whitespace change? It looks worse than before. > > > /// > > /// Size of memory to be reserved by FSP below "top > > /// of low usable memory" for bootloader usage. > > /// > > - UINT32 BootLoaderTolumSize; > > + UINT32 BootLoaderTolumSize; > > Any reason for this whitespace change? It looks worse than before. > > > /// > > /// Current boot mode. > > /// > > - UINT32 BootMode; > > + UINT32 BootMode; > > Any reason for this whitespace change? It looks worse than before. > > > /// > > /// Optional event handler for the bootloader to be informed of > events occurring during FSP execution. > > /// This value is only valid if Revision is >= 2. > > /// > > - EFI_PHYSICAL_ADDRESS FspEventHandler; > > - UINT8 Reserved1[24]; > > + EFI_PHYSICAL_ADDRESS FspEventHandler; > > + UINT8 Reserved1[24]; > > Any reason for these whitespace changes? It looks worse than before. > > > } FSPM_ARCH2_UPD; > > > > /// > > @@ -266,18 +266,18 @@ typedef struct { > > /// > > /// Revision of the structure is 2 for this version of the > specification. > > /// > > - UINT8 Revision; > > - UINT8 Reserved[3]; > > + UINT8 Revision; > > + UINT8 Reserved[3]; > > Any reason for these whitespace changes? It looks worse than before. > > > /// > > /// Length of the structure in bytes. The current value for this > field is 32. > > /// > > - UINT32 Length; > > + UINT32 Length; > > Any reason for this whitespace change? It looks worse than before. > > > /// > > /// FspEventHandler Optional event handler for the bootloader to be > informed of events > > /// occurring during FSP execution. > > /// > > - EFI_PHYSICAL_ADDRESS FspEventHandler; > > - UINT8 Reserved1[16]; > > + EFI_PHYSICAL_ADDRESS FspEventHandler; > > + UINT8 Reserved1[16]; > > Any reason for these whitespace changes? It looks worse than before. > > > } FSPS_ARCH2_UPD; > > > > /// > > @@ -609,4 +609,23 @@ EFI_STATUS > > IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr > > ); > > > > +/** > > + This FSP API initializes SMM and provide any OS runtime silicon > services, > > + including Reliability, Availability, and Serviceability (RAS) > features implemented by the CPU. > > + > > + @param[in] FspiUpdDataPtr Pointer to the FSPI_UPD data structure. > > + If NULL, FSP will use the default > parameters. > > + > > + @retval EFI_SUCCESS FSP execution environment was > initialized successfully. > > + @retval EFI_INVALID_PARAMETER Input parameters are invalid. > > + @retval EFI_UNSUPPORTED The FSP calling conditions were > not met. > > + @retval EFI_DEVICE_ERROR FSP initialization failed. > > + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status > codes will not be returned during S3. > > +**/ > > +typedef > > +EFI_STATUS > > +(EFIAPI *FSP_SMM_INIT)( > > + IN VOID *FspiUpdDataPtr > > + ); > > + > > #endif > > diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h > b/IntelFsp2Pkg/Include/FspGlobalData.h > > index 445540abfa..697b20ed4c 100644 > > --- a/IntelFsp2Pkg/Include/FspGlobalData.h > > +++ b/IntelFsp2Pkg/Include/FspGlobalData.h > > @@ -10,9 +10,9 @@ > > > > #include > > > > -#define FSP_IN_API_MODE 0 > > -#define FSP_IN_DISPATCH_MODE 1 > > -#define FSP_GLOBAL_DATA_VERSION 1 > > +#define FSP_IN_API_MODE 0 > > +#define FSP_IN_DISPATCH_MODE 1 > > +#define FSP_GLOBAL_DATA_VERSION 1 > > > > #pragma pack(1) > > > > @@ -24,16 +24,17 @@ typedef enum { > > TempRamExitApiIndex, > > FspSiliconInitApiIndex, > > FspMultiPhaseSiInitApiIndex, > > + FspSmmInitApiIndex, > > FspApiIndexMax > > } FSP_API_INDEX; > > > > typedef struct { > > - VOID *DataPtr; > > - UINTN MicrocodeRegionBase; > > - UINTN MicrocodeRegionSize; > > - UINTN CodeRegionBase; > > - UINTN CodeRegionSize; > > - UINTN Reserved; > > + VOID *DataPtr; > > + UINTN MicrocodeRegionBase; > > + UINTN MicrocodeRegionSize; > > + UINTN CodeRegionBase; > > + UINTN CodeRegionSize; > > + UINTN Reserved; > > } FSP_PLAT_DATA; > > > > #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', > 'D') > > @@ -41,28 +42,28 @@ typedef struct { > > #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF > > > > typedef struct { > > - UINT32 Signature; > > - UINT8 Version; > > - UINT8 Reserved1[3]; > > + UINT32 Signature; > > + UINT8 Version; > > + UINT8 Reserved1[3]; > > /// > > /// Offset 0x08 > > /// > > - UINTN CoreStack; > > - UINTN Reserved2; > > + UINTN CoreStack; > > + UINTN Reserved2; > > /// > > /// IA32: Offset 0x10; X64: Offset 0x18 > > /// > > - UINT32 StatusCode; > > - UINT8 ApiIdx; > > + UINT32 StatusCode; > > + UINT8 ApiIdx; > > /// > > /// 0: FSP in API mode; 1: FSP in DISPATCH mode > > /// > > - UINT8 FspMode; > > - UINT8 OnSeparateStack; > > - UINT8 Reserved3; > > - UINT32 NumberOfPhases; > > - UINT32 PhasesExecuted; > > - UINT32 Reserved4[8]; > > + UINT8 FspMode; > > + UINT8 OnSeparateStack; > > + UINT8 Reserved3; > > + UINT32 NumberOfPhases; > > + UINT32 PhasesExecuted; > > + UINT32 Reserved4[8]; > > /// > > /// IA32: Offset 0x40; X64: Offset 0x48 > > /// Start of UINTN and pointer section > > @@ -75,21 +76,23 @@ typedef struct { > > VOID *TempRamInitUpdPtr; > > VOID *MemoryInitUpdPtr; > > VOID *SiliconInitUpdPtr; > > + VOID *SmmInitUpdPtr; > > /// > > - /// IA32: Offset 0x64; X64: Offset 0x90 > > + /// IA32: Offset 0x68; X64: Offset 0x98 > > /// To store function parameters pointer > > /// so it can be retrieved after stack switched. > > /// > > VOID *FunctionParameterPtr; > > FSP_INFO_HEADER *FspInfoHeader; > > VOID *UpdDataPtr; > > + UINTN Reserved5; > > /// > > /// End of UINTN and pointer section > > /// > > - UINT8 Reserved5[16]; > > + UINT8 Reserved6[16]; > > UINT32 PerfSig; > > UINT16 PerfLen; > > - UINT16 Reserved6; > > + UINT16 Reserved7; > > UINT32 PerfIdx; > > UINT64 PerfData[32]; > > } FSP_GLOBAL_DATA; > > diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > > index c660defac3..c7fb63168f 100644 > > --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > > +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h > > @@ -26,13 +26,13 @@ > > > > #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H') > > > > -#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0 > > -#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1 > > -#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2 > > -#define FSP_IA32 0 > > -#define FSP_X64 1 > > +#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT BIT0 > > +#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1 > > +#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT BIT2 > > +#define FSP_IA32 0 > > +#define FSP_X64 1 > > > > -#pragma pack(1) > > + #pragma pack(1) > > Why add an indent to the #pragma line? I'm pretty sure that edk2 coding > style guidelines don't require that and it certainly looks worse than > before. > > > > > /// > > /// FSP Information Header as described in FSP v2.0 Spec section 5.1.1. > > @@ -159,6 +159,14 @@ typedef struct { > > /// Byte 0x4E: Reserved4. > > /// > > UINT16 Reserved4; > > + /// > > + /// Byte 0x50: Offset for the API for the Multi-Phase memory > initialization. > > + /// > > + UINT32 FspMultiPhaseMemInitEntryOffset; > > + /// > > + /// Byte 0x54: Offset for the API to initialize SMM. > > + /// > > + UINT32 FspSmmInitEntryOffset; > > } FSP_INFO_HEADER; > > > > /// > > @@ -240,7 +248,7 @@ typedef struct { > > // UINT32 PatchData[]; > > } FSP_PATCH_TABLE; > > > > -#pragma pack() > > + #pragma pack() > > Why add an indent to the #pragma line? I'm pretty sure that edk2 coding > style guidelines don't require that and it certainly looks worse than > before. > > > > > extern EFI_GUID gFspHeaderFileGuid; > > > > diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc > b/IntelFsp2Pkg/IntelFsp2Pkg.dsc > > index 7cf7e88245..b2d7867880 100644 > > --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc > > +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc > > @@ -68,6 +68,7 @@ > > IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf > > IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf > > IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf > > + IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf > > IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf > > IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf > > > > diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py > b/IntelFsp2Pkg/Tools/GenCfgOpt.py > > index c4fb1f1bb2..128b896592 100644 > > --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py > > +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py > > @@ -953,8 +953,8 @@ EndList > > return NoFileChange > > > > def CreateSplitUpdTxt (self, UpdTxtFile): > > - GuidList = > ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID'] > > - SignatureList = ['0x545F', '0x4D5F','0x535F'] # _T, _M, > and _S signature for FSPT, FSPM, FSPS > > + GuidList = > ['FSP_T_UPD_TOOL_GUID','FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID','FSP_I_UPD_TOOL_GUID'] > > + SignatureList = ['0x545F', '0x4D5F','0x535F','0x495F'] > # _T, _M, _S and _I signature for FSPT, FSPM, FSPS, FSPI > > for Index in range(len(GuidList)): > > UpdTxtFile = '' > > FvDir = self._FvDir > > @@ -1288,19 +1288,21 @@ EndList > > Chars.append(chr(Value & 0xFF)) > > Value = Value >> 8 > > SignatureStr = ''.join(Chars) > > - # Signature will be _T / _M / _S for FSPT / FSPM / FSPS > accordingly > > + # Signature will be _T / _M / _S / _I for FSPT / FSPM / > FSPS /FSPI accordingly > > if '_T' in SignatureStr[6:6+2]: > > TxtBody.append("#define FSPT_UPD_SIGNATURE > %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) > > elif '_M' in SignatureStr[6:6+2]: > > TxtBody.append("#define FSPM_UPD_SIGNATURE > %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) > > elif '_S' in SignatureStr[6:6+2]: > > TxtBody.append("#define FSPS_UPD_SIGNATURE > %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) > > + elif '_I' in SignatureStr[6:6+2]: > > + TxtBody.append("#define FSPI_UPD_SIGNATURE > %s /* '%s' */\n\n" % (Item['value'], SignatureStr)) > > TxtBody.append("\n") > > > > for Region in ['UPD']: > > UpdOffsetTable = [] > > - UpdSignature = ['0x545F', '0x4D5F', '0x535F'] #['_T', > '_M', '_S'] signature for FSPT, FSPM, FSPS > > - UpdStructure = ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD'] > > + UpdSignature = ['0x545F', '0x4D5F', '0x535F', '0x495F'] > #['_T', '_M', '_S', '_I'] signature for FSPT, FSPM, FSPS, FSPI > > + UpdStructure = ['FSPT_UPD', 'FSPM_UPD', 'FSPS_UPD', > 'FSPI_UPD'] > > for Item in self._CfgItemList: > > if Item["cname"] == 'Signature' and Item["value"][0:6] > in UpdSignature: > > Item["offset"] = 0 # re-initialize offset to 0 when > new UPD structure starting > > @@ -1393,11 +1395,12 @@ EndList > > HeaderTFileName = 'FsptUpd.h' > > HeaderMFileName = 'FspmUpd.h' > > HeaderSFileName = 'FspsUpd.h' > > + HeaderIFileName = 'FspiUpd.h' > > > > - UpdRegionCheck = ['FSPT', 'FSPM', 'FSPS'] # FSPX_UPD_REGION > > - UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, > FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG > > - UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', > 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE'] > > - ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', > 'FSPS_ARCH_UPD'] > > + UpdRegionCheck = ['FSPT', 'FSPM', 'FSPS', 'FSPI'] # > FSPX_UPD_REGION > > + UpdConfigCheck = ['FSP_T', 'FSP_M', 'FSP_S', 'FSP_I'] # > FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG > > + UpdSignatureCheck = ['FSPT_UPD_SIGNATURE', > 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE', 'FSPI_UPD_SIGNATURE'] > > + ExcludedSpecificUpd = ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', > 'FSPS_ARCH_UPD', 'FSPI_ARCH_UPD'] > > ExcludedSpecificUpd1 = ['FSPT_ARCH2_UPD', 'FSPM_ARCH2_UPD', > 'FSPS_ARCH2_UPD'] > > > > IncLines = [] > > @@ -1420,6 +1423,9 @@ EndList > > elif UpdRegionCheck[item] == 'FSPS': > > HeaderFd = open(os.path.join(FvDir, HeaderSFileName), > "w") > > FileBase = os.path.basename(os.path.join(FvDir, > HeaderSFileName)) > > + elif UpdRegionCheck[item] == 'FSPI': > > + HeaderFd = open(os.path.join(FvDir, HeaderIFileName), > "w") > > + FileBase = os.path.basename(os.path.join(FvDir, > HeaderIFileName)) > > FileName = FileBase.replace(".", "_").upper() > > HeaderFd.write("%s\n" % (__copyright_h__ % > date.today().year)) > > HeaderFd.write("#ifndef __%s__\n" % FileName) > > @@ -1696,7 +1702,7 @@ EndList > > > > > > def Usage(): > > - print ("GenCfgOpt Version 0.57") > > + print ("GenCfgOpt Version 0.58") > > print ("Usage:") > > print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir > [-D Macros]") > > print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir > InputHFile [-D Macros]") > > diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py > b/IntelFsp2Pkg/Tools/SplitFspBin.py > > index f9151b5afd..317d9c1fa0 100644 > > --- a/IntelFsp2Pkg/Tools/SplitFspBin.py > > +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py > > @@ -1,6 +1,6 @@ > > ## @ SplitFspBin.py > > # > > -# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
> > +# Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
> > # SPDX-License-Identifier: BSD-2-Clause-Patent > > # > > ## > > @@ -492,7 +492,7 @@ class FspImage: > > self.FihOffset = fihoff > > self.Offset = offset > > self.FvIdxList = [] > > - self.Type = "XTMSXXXXOXXXXXXX"[(fih.ComponentAttribute >> > 12) & 0x0F] > > + self.Type = "XTMSIXXXXOXXXXXXX"[(fih.ComponentAttribute >> > 12) & 0x0F] > > self.PatchList = patch > > self.PatchList.append(fihoff + 0x1C) > > > > @@ -869,7 +869,7 @@ def main (): > > parser_rebase = subparsers.add_parser('rebase', help='rebase a > FSP into a new base address') > > parser_rebase.set_defaults(which='rebase') > > parser_rebase.add_argument('-f', '--fspbin' , dest='FspBinary', > type=str, help='FSP binary file path', required = True) > > - parser_rebase.add_argument('-c', '--fspcomp', > choices=['t','m','s','o'], nargs='+', dest='FspComponent', type=str, > help='FSP component to rebase', default = "['t']", required = True) > > + parser_rebase.add_argument('-c', '--fspcomp', > choices=['t','m','s','o','i'], nargs='+', dest='FspComponent', type=str, > help='FSP component to rebase', default = "['t']", required = True) > > parser_rebase.add_argument('-b', '--newbase', dest='FspBase', > nargs='+', type=str, help='Rebased FSP binary file name', default = '', > required = True) > > parser_rebase.add_argument('-o', '--outdir' , dest='OutputDir', > type=str, help='Output directory path', default = '.') > > parser_rebase.add_argument('-n', '--outfile', dest='OutputFile', > type=str, help='Rebased FSP binary file name', default = '') > > -- > > 2.35.0.windows.1 > > > > > > > -- Pedro Falcato --000000000000483baf05e41b59cd Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Mon, Jul 18, 2022 at 10:40 PM Nate= DeSimone <nathaniel.l= .desimone@intel.com> wrote:
Hi Chasel,

Please see comments inline. Here is a summary of my feedback:

#1) IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm - line 34 - Bug: eax shou= ld be rax
#2) IntelFsp2Pkg/Include/FspEas/FspApi.h - Various unnecessary whitespace c= hanges that make the file look worse than before.
#3) IntelFsp2Pkg/Include/Guid/FspHeaderFile.h - Why indent the #pragma line= s?

Thanks,
Nate

> -----Original Message-----
> From: Chiu, Chasel <chasel.chiu@intel.com>
> Sent: Thursday, July 14, 2022 1:04 PM
> To: devel@ed= k2.groups.io
> Cc: Zhang, Hongbin1 <hongbin1.zhang@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>; Chiu, > Chasel <= chasel.chiu@intel.com>
> Subject: [PATCH] IntelFsp2Pkg/FspSecCore: Add FSP-I API for SMM suppor= t.
>
> From: Hongbin1 Zhang <hongbin1.zhang@intel.com>
>
> REF: https://bugzilla.tianocore.org/show_b= ug.cgi?id=3D3993
> Add FSP-I API entry point for SMM support.
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Star Zeng <star.zeng@intel.com>
> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
> Signed-off-by: Hongbin1 Zhang <hongbin1.zhang@intel.com>
> ---
>=C2=A0 IntelFsp2Pkg/FspSecCore/SecFspApiChk.c=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| 13 +++++++++++++
>=C2=A0 IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf=C2=A0 =C2=A0 =C2=A0 =C2= =A0 | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
>=C2=A0 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm | 44 ++++++++++++= ++++++++++++++++++++++++++++++++
>=C2=A0 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm=C2=A0 | 44 +++++++= +++++++++++++++++++++++++++++++++++++
>=C2=A0 IntelFsp2Pkg/Include/FspEas/FspApi.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0| 57 ++++++++++++++++++++++++++++++++++++++-------------------=
>=C2=A0 IntelFsp2Pkg/Include/FspGlobalData.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0| 53 ++++++++++++++++++++++++++++-------------------------
>=C2=A0 IntelFsp2Pkg/Include/Guid/FspHeaderFile.h=C2=A0 =C2=A0 =C2=A0 | = 22 +++++++++++++++-------
>=C2=A0 IntelFsp2Pkg/IntelFsp2Pkg.dsc=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 1 +
>=C2=A0 IntelFsp2Pkg/Tools/GenCfgOpt.py=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 | 26 ++++++++++++++++----------
>=C2=A0 IntelFsp2Pkg/Tools/SplitFspBin.py=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 6 +++---
>=C2=A0 10 files changed, 256 insertions(+), 64 deletions(-)
>
> diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/Fsp= SecCore/SecFspApiChk.c
> index e22a88cc84..35d223a404 100644
> --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c
> @@ -71,6 +71,19 @@ FspApiCallingCheck (
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Status =3D EFI_INVALID_PARAMETER; >=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 } else if (ApiIdx =3D=3D FspSmmInitApiIndex) {
> +=C2=A0 =C2=A0 //
> +=C2=A0 =C2=A0 // FspSmmInitApiIndex check
> +=C2=A0 =C2=A0 //
> +=C2=A0 =C2=A0 if ((FspData =3D=3D NULL) || ((UINTN)FspData =3D=3D MAX= _ADDRESS) || ((UINTN)FspData =3D=3D MAX_UINT32)) {
> +=C2=A0 =C2=A0 =C2=A0 Status =3D EFI_UNSUPPORTED;
> +=C2=A0 =C2=A0 } else {
> +=C2=A0 =C2=A0 =C2=A0 if (FspData->Signature !=3D FSP_GLOBAL_DATA_S= IGNATURE) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 Status =3D EFI_UNSUPPORTED;
> +=C2=A0 =C2=A0 =C2=A0 } else if (EFI_ERROR (FspUpdSignatureCheck (FspS= mmInitApiIndex, ApiParam))) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 Status =3D EFI_INVALID_PARAMETER;
> +=C2=A0 =C2=A0 =C2=A0 }
> +=C2=A0 =C2=A0 }
>=C2=A0 =C2=A0 } else {
>=C2=A0 =C2=A0 =C2=A0 Status =3D EFI_UNSUPPORTED;
>=C2=A0 =C2=A0 }
> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf b/IntelFsp2Pkg/Fs= pSecCore/FspSecCoreI.inf
> new file mode 100644
> index 0000000000..d31576c00b
> --- /dev/null
> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf
> @@ -0,0 +1,54 @@
> +## @file
> +#=C2=A0 Sec Core for FSP
> +#
> +#=C2=A0 Copyright (c) 2022, Intel Corporation. All rights reserved.&l= t;BR>
> +#
> +#=C2=A0 SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +=C2=A0 INF_VERSION=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D 0x00010005
> +=C2=A0 BASE_NAME=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D FspSecCoreI
> +=C2=A0 FILE_GUID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =3D 558782b5-782d-415e-ab9e-0ceb79dc3425
> +=C2=A0 MODULE_TYPE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =3D SEC
> +=C2=A0 VERSION_STRING=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0=3D 1.0
> +
> +#
> +# The following information is for reference only and not required by= the build tools.
> +#
> +#=C2=A0 VALID_ARCHITECTURES=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =3D IA32 X64
> +#
> +
> +[Sources]
> +=C2=A0 SecFspApiChk.c
> +=C2=A0 SecFsp.h
> +
> +[Sources.X64]
> +=C2=A0 X64/FspApiEntryI.nasm
> +=C2=A0 X64/FspApiEntryCommon.nasm
> +=C2=A0 X64/FspHelper.nasm
> +
> +[Sources.IA32]
> +=C2=A0 Ia32/FspApiEntryI.nasm
> +=C2=A0 Ia32/FspApiEntryCommon.nasm
> +=C2=A0 Ia32/FspHelper.nasm
> +
> +[Binaries.Ia32]
> +=C2=A0 RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC
> +
> +[Packages]
> +=C2=A0 MdePkg/MdePkg.dec
> +=C2=A0 IntelFsp2Pkg/IntelFsp2Pkg.dec
> +
> +[LibraryClasses]
> +=C2=A0 BaseMemoryLib
> +=C2=A0 DebugLib
> +=C2=A0 BaseLib
> +=C2=A0 PciCf8Lib
> +=C2=A0 SerialPortLib
> +=C2=A0 FspSwitchStackLib
> +=C2=A0 FspCommonLib
> +=C2=A0 FspSecPlatformLib
> +
> +
> diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm b/IntelFsp= 2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm
> new file mode 100644
> index 0000000000..e9365d6832
> --- /dev/null
> +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryI.nasm
> @@ -0,0 +1,44 @@
> +;; @file
> +;=C2=A0 Provide FSP API entry points.
> +;
> +; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR&g= t;
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;;
> +
> +=C2=A0 =C2=A0 SECTION .text
> +
> +;
> +; Following functions will be provided in C
> +;
> +extern ASM_PFX(FspApiCommon)
> +
> +;--------------------------------------------------------------------= --------
> +; FspApiCommonContinue API
> +;
> +; This is the FSP API common entry point to resume the FSP execution<= br> > +;
> +;--------------------------------------------------------------------= --------
> +global ASM_PFX(FspApiCommonContinue)
> +ASM_PFX(FspApiCommonContinue):
> +=C2=A0 jmp $
> +
> +;--------------------------------------------------------------------= --------
> +; FspSmmInit API
> +;
> +; This FSP API will notify the FSP about the different phases in the = boot
> +; process
> +;
> +;--------------------------------------------------------------------= --------
> +global ASM_PFX(FspSmmInitApi)
> +ASM_PFX(FspSmmInitApi):
> +=C2=A0 mov=C2=A0 =C2=A0 eax,=C2=A0 7 ; FSP_API_INDEX.FspSmmInitApiInd= ex
> +=C2=A0 jmp=C2=A0 =C2=A0 ASM_PFX(FspApiCommon)
> +
> +;--------------------------------------------------------------------= --------
> +; Module Entrypoint API
> +;--------------------------------------------------------------------= --------
> +global ASM_PFX(_ModuleEntryPoint)
> +ASM_PFX(_ModuleEntryPoint):
> +=C2=A0 jmp=C2=A0 $
> +=C2=A0 ; Add reference to APIs so that it will not be optimized by co= mpiler
> +=C2=A0 jmp=C2=A0 ASM_PFX(FspSmmInitApi)
> diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm b/IntelFsp2= Pkg/FspSecCore/X64/FspApiEntryI.nasm
> new file mode 100644
> index 0000000000..e9365d6832
> --- /dev/null
> +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryI.nasm
> @@ -0,0 +1,44 @@
> +;; @file
> +;=C2=A0 Provide FSP API entry points.
> +;
> +; Copyright (c) 2022, Intel Corporation. All rights reserved.<BR&g= t;
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;;
> +
> +=C2=A0 =C2=A0 SECTION .text
> +
> +;
> +; Following functions will be provided in C
> +;
> +extern ASM_PFX(FspApiCommon)
> +
> +;--------------------------------------------------------------------= --------
> +; FspApiCommonContinue API
> +;
> +; This is the FSP API common entry point to resume the FSP execution<= br> > +;
> +;--------------------------------------------------------------------= --------
> +global ASM_PFX(FspApiCommonContinue)
> +ASM_PFX(FspApiCommonContinue):
> +=C2=A0 jmp $
> +
> +;--------------------------------------------------------------------= --------
> +; FspSmmInit API
> +;
> +; This FSP API will notify the FSP about the different phases in the = boot
> +; process
> +;
> +;--------------------------------------------------------------------= --------
> +global ASM_PFX(FspSmmInitApi)
> +ASM_PFX(FspSmmInitApi):
> +=C2=A0 mov=C2=A0 =C2=A0 eax,=C2=A0 7 ; FSP_API_INDEX.FspSmmInitApiInd= ex

This is a bug. It should be:

mov=C2=A0 =C2=A0 rax,=C2=A0 7 ; FSP_API_INDEX.FspSmmInitApiIndex
=C2=A0
Hi Nate,

This is not a= ctually a problem, a 32-bit mov to a 32-bit register in long mode will zero= the upper part.
=C2=A0

Note that IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm compares ApiIn= dex numbers using rax, so it is important to make sure that the upper 32-bi= ts are zero:

https://github.com/tianocore/edk2/blob/c9= 66204049f3d5dae6d5e587ddc298c684142c5c/IntelFsp2Pkg/FspSecCore/X64/FspApiEn= tryCommon.nasm#L65

> +=C2=A0 jmp=C2=A0 =C2=A0 ASM_PFX(FspApiCommon)
> +
> +;--------------------------------------------------------------------= --------
> +; Module Entrypoint API
> +;--------------------------------------------------------------------= --------
> +global ASM_PFX(_ModuleEntryPoint)
> +ASM_PFX(_ModuleEntryPoint):
> +=C2=A0 jmp=C2=A0 $
> +=C2=A0 ; Add reference to APIs so that it will not be optimized by co= mpiler
> +=C2=A0 jmp=C2=A0 ASM_PFX(FspSmmInitApi)
> diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Inclu= de/FspEas/FspApi.h
> index b36bc2b9ae..1d6c2fb63d 100644
> --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h
> +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h
> @@ -135,18 +135,18 @@ typedef struct {
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Revision of the structure is 2 for this version of th= e specification.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= evision;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= eserved[3];
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Revision;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Reserved[3];

Any reason for these whitespace changes? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Length of the structure in bytes. The current value f= or this field is 32.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0L= ength;
> +=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 Length;

Any reason for this whitespace change? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// FspDebugHandler Optional debug handler for the bootlo= ader to receive debug messages
>=C2=A0 =C2=A0 /// occurring during FSP execution.
>=C2=A0 =C2=A0 ///
> -=C2=A0 EFI_PHYSICAL_ADDRESS FspDebugHandler;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= eserved1[16];
> +=C2=A0 EFI_PHYSICAL_ADDRESS=C2=A0 =C2=A0 FspDebugHandler;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Reserved1[16];

Any reason for these whitespace changes? It looks worse than before.

>=C2=A0 } FSPT_ARCH2_UPD;
>=C2=A0
>=C2=A0 ///
> @@ -197,37 +197,37 @@ typedef struct {
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Revision of the structure is 3 for this version of th= e specification.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= evision;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= eserved[3];
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Revision;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Reserved[3];

Any reason for these whitespace changes? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Length of the structure in bytes. The current value f= or this field is 64.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0L= ength;
> +=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 Length;

Any reason for this whitespace change? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Pointer to the temporary stack base address to be
>=C2=A0 =C2=A0 /// consumed inside FspMemoryInit() API.
>=C2=A0 =C2=A0 ///
> -=C2=A0 EFI_PHYSICAL_ADDRESS StackBase;
> +=C2=A0 EFI_PHYSICAL_ADDRESS=C2=A0 =C2=A0 StackBase;

Any reason for this whitespace change? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Temporary stack size to be consumed inside
>=C2=A0 =C2=A0 /// FspMemoryInit() API.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0S= tackSize;
> +=C2=A0 UINT64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 StackSize;

Any reason for this whitespace change? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Size of memory to be reserved by FSP below "top<= br> >=C2=A0 =C2=A0 /// of low usable memory" for bootloader usage.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0B= ootLoaderTolumSize;
> +=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 BootLoaderTolumSize;

Any reason for this whitespace change? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Current boot mode.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0B= ootMode;
> +=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 BootMode;

Any reason for this whitespace change? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Optional event handler for the bootloader to be infor= med of events occurring during FSP execution.
>=C2=A0 =C2=A0 /// This value is only valid if Revision is >=3D 2. >=C2=A0 =C2=A0 ///
> -=C2=A0 EFI_PHYSICAL_ADDRESS FspEventHandler;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= eserved1[24];
> +=C2=A0 EFI_PHYSICAL_ADDRESS=C2=A0 =C2=A0 FspEventHandler;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Reserved1[24];

Any reason for these whitespace changes? It looks worse than before.

>=C2=A0 } FSPM_ARCH2_UPD;
>=C2=A0
>=C2=A0 ///
> @@ -266,18 +266,18 @@ typedef struct {
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Revision of the structure is 2 for this version of th= e specification.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= evision;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= eserved[3];
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Revision;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Reserved[3];

Any reason for these whitespace changes? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Length of the structure in bytes. The current value f= or this field is 32.
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0L= ength;
> +=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 Length;

Any reason for this whitespace change? It looks worse than before.

>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// FspEventHandler Optional event handler for the bootlo= ader to be informed of events
>=C2=A0 =C2=A0 /// occurring during FSP execution.
>=C2=A0 =C2=A0 ///
> -=C2=A0 EFI_PHYSICAL_ADDRESS FspEventHandler;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 R= eserved1[16];
> +=C2=A0 EFI_PHYSICAL_ADDRESS=C2=A0 =C2=A0 FspEventHandler;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0Reserved1[16];

Any reason for these whitespace changes? It looks worse than before.

>=C2=A0 } FSPS_ARCH2_UPD;
>=C2=A0
>=C2=A0 ///
> @@ -609,4 +609,23 @@ EFI_STATUS
>=C2=A0 =C2=A0 IN FSP_MULTI_PHASE_PARAMS=C2=A0 =C2=A0 =C2=A0*MultiPhaseS= iInitParamPtr
>=C2=A0 =C2=A0 );
>=C2=A0
> +/**
> +=C2=A0 This FSP API initializes SMM and provide any OS runtime silico= n services,
> +=C2=A0 including Reliability, Availability, and Serviceability (RAS) = features implemented by the CPU.
> +
> +=C2=A0 @param[in] FspiUpdDataPtr=C2=A0 =C2=A0 =C2=A0Pointer to the FS= PI_UPD data structure.
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 If NULL, FSP will use the defaul= t parameters.
> +
> +=C2=A0 @retval EFI_SUCCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0FSP execution environment was initialized successfully.=
> +=C2=A0 @retval EFI_INVALID_PARAMETER=C2=A0 =C2=A0 =C2=A0 =C2=A0Input = parameters are invalid.
> +=C2=A0 @retval EFI_UNSUPPORTED=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0The FSP calling conditions were not met.
> +=C2=A0 @retval EFI_DEVICE_ERROR=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 FSP initialization failed.
> +=C2=A0 @retval FSP_STATUS_RESET_REQUIREDx=C2=A0 A reset is required. = These status codes will not be returned during S3.
> +**/
> +typedef
> +EFI_STATUS
> +(EFIAPI *FSP_SMM_INIT)(
> +=C2=A0 IN VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 *FspiUpdDataPtr
> +=C2=A0 );
> +
>=C2=A0 #endif
> diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Inclu= de/FspGlobalData.h
> index 445540abfa..697b20ed4c 100644
> --- a/IntelFsp2Pkg/Include/FspGlobalData.h
> +++ b/IntelFsp2Pkg/Include/FspGlobalData.h
> @@ -10,9 +10,9 @@
>=C2=A0
>=C2=A0 #include <FspEas.h>
>=C2=A0
> -#define FSP_IN_API_MODE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00
> -#define FSP_IN_DISPATCH_MODE=C2=A0 =C2=A0 1
> -#define FSP_GLOBAL_DATA_VERSION 1
> +#define FSP_IN_API_MODE=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
> +#define FSP_IN_DISPATCH_MODE=C2=A0 =C2=A0 =C2=A01
> +#define FSP_GLOBAL_DATA_VERSION=C2=A0 1
>=C2=A0
>=C2=A0 #pragma pack(1)
>=C2=A0
> @@ -24,16 +24,17 @@ typedef enum {
>=C2=A0 =C2=A0 TempRamExitApiIndex,
>=C2=A0 =C2=A0 FspSiliconInitApiIndex,
>=C2=A0 =C2=A0 FspMultiPhaseSiInitApiIndex,
> +=C2=A0 FspSmmInitApiIndex,
>=C2=A0 =C2=A0 FspApiIndexMax
>=C2=A0 } FSP_API_INDEX;
>=C2=A0
>=C2=A0 typedef struct=C2=A0 {
> -=C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 *DataPtr;
> -=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0MicrocodeRegionBase;
> -=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0MicrocodeRegionSize;
> -=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0CodeRegionBase;
> -=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0CodeRegionSize;
> -=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0Reserved;
> +=C2=A0 VOID=C2=A0 =C2=A0 =C2=A0*DataPtr;
> +=C2=A0 UINTN=C2=A0 =C2=A0 MicrocodeRegionBase;
> +=C2=A0 UINTN=C2=A0 =C2=A0 MicrocodeRegionSize;
> +=C2=A0 UINTN=C2=A0 =C2=A0 CodeRegionBase;
> +=C2=A0 UINTN=C2=A0 =C2=A0 CodeRegionSize;
> +=C2=A0 UINTN=C2=A0 =C2=A0 Reserved;
>=C2=A0 } FSP_PLAT_DATA;
>=C2=A0
>=C2=A0 #define FSP_GLOBAL_DATA_SIGNATURE=C2=A0 =C2=A0 =C2=A0 =C2=A0 SIG= NATURE_32 ('F', 'S', 'P', 'D')
> @@ -41,28 +42,28 @@ typedef struct=C2=A0 {
>=C2=A0 #define FSP_PERFORMANCE_DATA_TIMER_MASK=C2=A0 0xFFFFFFFFFFFFFF >=C2=A0
>=C2=A0 typedef struct=C2=A0 {
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Signatur= e;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Version;=
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Reserved= 1[3];
> +=C2=A0 UINT32=C2=A0 =C2=A0 Signature;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0Version;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0Reserved1[3];
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// Offset 0x08
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 CoreStac= k;
> -=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Reserved= 2;
> +=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0CoreStack;
> +=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0Reserved2;
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// IA32: Offset 0x10; X64: Offset 0x18
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0StatusCo= de;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ApiIdx;<= br> > +=C2=A0 UINT32=C2=A0 =C2=A0 StatusCode;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0ApiIdx;
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// 0: FSP in API mode; 1: FSP in DISPATCH mode
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 FspMode;=
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 OnSepara= teStack;
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Reserved= 3;
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0NumberOf= Phases;
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PhasesEx= ecuted;
> -=C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Reserved= 4[8];
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0FspMode;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0OnSeparateStack;
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0Reserved3;
> +=C2=A0 UINT32=C2=A0 =C2=A0 NumberOfPhases;
> +=C2=A0 UINT32=C2=A0 =C2=A0 PhasesExecuted;
> +=C2=A0 UINT32=C2=A0 =C2=A0 Reserved4[8];
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// IA32: Offset 0x40; X64: Offset 0x48
>=C2=A0 =C2=A0 /// Start of UINTN and pointer section
> @@ -75,21 +76,23 @@ typedef struct=C2=A0 {
>=C2=A0 =C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*TempRamInitUpdPtr;
>=C2=A0 =C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*MemoryInitUpdPtr;
>=C2=A0 =C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*SiliconInitUpdPtr;
> +=C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*Sm= mInitUpdPtr;
>=C2=A0 =C2=A0 ///
> -=C2=A0 /// IA32: Offset 0x64; X64: Offset 0x90
> +=C2=A0 /// IA32: Offset 0x68; X64: Offset 0x98
>=C2=A0 =C2=A0 /// To store function parameters pointer
>=C2=A0 =C2=A0 /// so it can be retrieved after stack switched.
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*FunctionParameterPtr;
>=C2=A0 =C2=A0 FSP_INFO_HEADER=C2=A0 =C2=A0 *FspInfoHeader;
>=C2=A0 =C2=A0 VOID=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0*UpdDataPtr;
> +=C2=A0 UINTN=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Reserved= 5;
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 /// End of UINTN and pointer section
>=C2=A0 =C2=A0 ///
> -=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Reserved= 5[16];
> +=C2=A0 UINT8=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Reserved= 6[16];
>=C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Per= fSig;
>=C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Per= fLen;
> -=C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Reserved= 6;
> +=C2=A0 UINT16=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Reserved= 7;
>=C2=A0 =C2=A0 UINT32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Per= fIdx;
>=C2=A0 =C2=A0 UINT64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Per= fData[32];
>=C2=A0 } FSP_GLOBAL_DATA;
> diff --git a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/IntelFsp2Pkg/= Include/Guid/FspHeaderFile.h
> index c660defac3..c7fb63168f 100644
> --- a/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
> +++ b/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
> @@ -26,13 +26,13 @@
>=C2=A0
>=C2=A0 #define FSP_INFO_HEADER_SIGNATURE=C2=A0 SIGNATURE_32 ('F'= ;, 'S', 'P', 'H')
>=C2=A0
> -#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT=C2=A0 =C2=A0 =C2=A0 BIT0
> -#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT BIT1
> -#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT=C2=A0 =C2=A0 BIT2
> -#define FSP_IA32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0
> -#define FSP_X64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A01
> +#define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT=C2=A0 =C2=A0 =C2=A0 =C2=A0BI= T0
> +#define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT=C2=A0 BIT1
> +#define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT=C2=A0 =C2=A0 =C2=A0BIT2 > +#define FSP_IA32=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00
> +#define FSP_X64=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 1
>=C2=A0
> -#pragma pack(1)
> +=C2=A0 #pragma pack(1)

Why add an indent to the #pragma line? I'm pretty sure that edk2 coding= style guidelines don't require that and it certainly looks worse than = before.

>=C2=A0
>=C2=A0 ///
>=C2=A0 /// FSP Information Header as described in FSP v2.0 Spec section= 5.1.1.
> @@ -159,6 +159,14 @@ typedef struct {
>=C2=A0 =C2=A0 /// Byte 0x4E: Reserved4.
>=C2=A0 =C2=A0 ///
>=C2=A0 =C2=A0 UINT16=C2=A0 =C2=A0 Reserved4;
> +=C2=A0 ///
> +=C2=A0 /// Byte 0x50: Offset for the API for the Multi-Phase memory i= nitialization.
> +=C2=A0 ///
> +=C2=A0 UINT32=C2=A0 =C2=A0 FspMultiPhaseMemInitEntryOffset;
> +=C2=A0 ///
> +=C2=A0 /// Byte 0x54: Offset for the API to initialize SMM.
> +=C2=A0 ///
> +=C2=A0 UINT32=C2=A0 =C2=A0 FspSmmInitEntryOffset;
>=C2=A0 } FSP_INFO_HEADER;
>=C2=A0
>=C2=A0 ///
> @@ -240,7 +248,7 @@ typedef struct {
>=C2=A0 =C2=A0 // UINT32=C2=A0 PatchData[];
>=C2=A0 } FSP_PATCH_TABLE;
>=C2=A0
> -#pragma pack()
> +=C2=A0 #pragma pack()

Why add an indent to the #pragma line? I'm pretty sure that edk2 coding= style guidelines don't require that and it certainly looks worse than = before.

>=C2=A0
>=C2=A0 extern EFI_GUID=C2=A0 gFspHeaderFileGuid;
>=C2=A0
> diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg= .dsc
> index 7cf7e88245..b2d7867880 100644
> --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc
> +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc
> @@ -68,6 +68,7 @@
>=C2=A0 =C2=A0 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
>=C2=A0 =C2=A0 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
>=C2=A0 =C2=A0 IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> +=C2=A0 IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf
>=C2=A0 =C2=A0 IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf
>=C2=A0 =C2=A0 IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf
>=C2=A0
> diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenC= fgOpt.py
> index c4fb1f1bb2..128b896592 100644
> --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py
> +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py
> @@ -953,8 +953,8 @@ EndList
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return NoFileChange
>=C2=A0
>=C2=A0 =C2=A0 =C2=A0 def CreateSplitUpdTxt (self, UpdTxtFile):
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 GuidList =3D ['FSP_T_UPD_TOOL_GUID= 9;,'FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID']
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 SignatureList =3D ['0x545F', '= ;0x4D5F','0x535F']=C2=A0 =C2=A0 =C2=A0 =C2=A0 #=C2=A0 _T, _M, a= nd _S signature for FSPT, FSPM, FSPS
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 GuidList =3D ['FSP_T_UPD_TOOL_GUID= 9;,'FSP_M_UPD_TOOL_GUID','FSP_S_UPD_TOOL_GUID','FSP_I_U= PD_TOOL_GUID']
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 SignatureList =3D ['0x545F', '= ;0x4D5F','0x535F','0x495F']=C2=A0 =C2=A0 =C2=A0 =C2=A0 = #=C2=A0 _T, _M, _S and _I signature for FSPT, FSPM, FSPS, FSPI
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for Index in range(len(GuidList)): >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdTxtFile =3D '&#= 39;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 FvDir =3D self._FvDir<= br> > @@ -1288,19 +1288,21 @@ EndList
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0Chars.append(chr(Value & 0xFF))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0Value =3D Value >> 8
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Signature= Str =3D ''.join(Chars)
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0# Signature wi= ll be _T / _M / _S for FSPT / FSPM / FSPS accordingly
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0# Signature wi= ll be _T / _M / _S / _I for FSPT / FSPM / FSPS /FSPI accordingly
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if '_= T' in SignatureStr[6:6+2]:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0TxtBody.append("#define FSPT_UPD_SIGNATURE=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0%s=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* '%s&= #39; */\n\n" % (Item['value'], SignatureStr))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0elif '= ;_M' in SignatureStr[6:6+2]:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0TxtBody.append("#define FSPM_UPD_SIGNATURE=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0%s=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* '%s&= #39; */\n\n" % (Item['value'], SignatureStr))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0elif '= ;_S' in SignatureStr[6:6+2]:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0TxtBody.append("#define FSPS_UPD_SIGNATURE=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0%s=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* '%s&= #39; */\n\n" % (Item['value'], SignatureStr))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0elif '_I&#= 39; in SignatureStr[6:6+2]:
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= TxtBody.append("#define FSPI_UPD_SIGNATURE=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0%s=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* '%s' */= \n\n" % (Item['value'], SignatureStr))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 TxtBody.append("\n")
>=C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for Region in ['UPD']:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdOffsetTable =3D []<= br> > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdSignature =3D ['0x54= 5F', '0x4D5F', '0x535F']=C2=A0 =C2=A0#['_T', &#= 39;_M', '_S'] signature for FSPT, FSPM, FSPS
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdStructure =3D ['FSPT= _UPD', 'FSPM_UPD', 'FSPS_UPD']
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdSignature =3D ['0x54= 5F', '0x4D5F', '0x535F', '0x495F']=C2=A0 =C2=A0= #['_T', '_M', '_S', '_I'] signature for FSP= T, FSPM, FSPS, FSPI
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdStructure =3D ['FSPT= _UPD', 'FSPM_UPD', 'FSPS_UPD', 'FSPI_UPD']
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for Item in self._CfgI= temList:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if Item[= "cname"] =3D=3D 'Signature' and Item["value"][0= :6] in UpdSignature:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 Item["offset"] =3D 0 # re-initialize offset to 0 when new = UPD structure starting
> @@ -1393,11 +1395,12 @@ EndList
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 HeaderTFileName =3D 'FsptUpd.h&#= 39;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 HeaderMFileName =3D 'FspmUpd.h&#= 39;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 HeaderSFileName =3D 'FspsUpd.h&#= 39;
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 HeaderIFileName =3D 'FspiUpd.h' >=C2=A0
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdRegionCheck =3D ['FSPT', '= FSPM', 'FSPS']=C2=A0 =C2=A0 =C2=A0# FSPX_UPD_REGION
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdConfigCheck =3D ['FSP_T', '= ;FSP_M', 'FSP_S']=C2=A0 # FSP_X_CONFIG, FSP_X_TEST_CONFIG, FSP_= X_RESTRICTED_CONFIG
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdSignatureCheck =3D ['FSPT_UPD_SIGN= ATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE']
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 ExcludedSpecificUpd =3D ['FSPT_ARCH_U= PD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD']
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdRegionCheck =3D ['FSPT', '= FSPM', 'FSPS', 'FSPI']=C2=A0 =C2=A0 =C2=A0# FSPX_UPD_RE= GION
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdConfigCheck =3D ['FSP_T', '= ;FSP_M', 'FSP_S', 'FSP_I']=C2=A0 # FSP_X_CONFIG, FSP_X_= TEST_CONFIG, FSP_X_RESTRICTED_CONFIG
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 UpdSignatureCheck =3D ['FSPT_UPD_SIGN= ATURE', 'FSPM_UPD_SIGNATURE', 'FSPS_UPD_SIGNATURE', = 9;FSPI_UPD_SIGNATURE']
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 ExcludedSpecificUpd =3D ['FSPT_ARCH_U= PD', 'FSPM_ARCH_UPD', 'FSPS_ARCH_UPD', 'FSPI_ARCH_U= PD']
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ExcludedSpecificUpd1 =3D ['FSPT_= ARCH2_UPD', 'FSPM_ARCH2_UPD', 'FSPS_ARCH2_UPD']
>=C2=A0
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 IncLines =3D []
> @@ -1420,6 +1423,9 @@ EndList
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 elif UpdRegionCheck[it= em] =3D=3D 'FSPS':
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 HeaderFd= =3D open(os.path.join(FvDir, HeaderSFileName), "w")
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 FileBase= =3D os.path.basename(os.path.join(FvDir, HeaderSFileName))
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 elif UpdRegionCheck[item] = =3D=3D 'FSPI':
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 HeaderFd =3D = open(os.path.join(FvDir, HeaderIFileName), "w")
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 FileBase =3D = os.path.basename(os.path.join(FvDir, HeaderIFileName))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 FileName =3D FileBase.= replace(".", "_").upper()
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 HeaderFd.write("%= s\n"=C2=A0 =C2=A0% (__copyright_h__ % date.today().year))
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 HeaderFd.write("#= ifndef __%s__\n"=C2=A0 =C2=A0% FileName)
> @@ -1696,7 +1702,7 @@ EndList
>=C2=A0
>=C2=A0
>=C2=A0 def Usage():
> -=C2=A0 =C2=A0 print ("GenCfgOpt Version 0.57")
> +=C2=A0 =C2=A0 print ("GenCfgOpt Version 0.58")
>=C2=A0 =C2=A0 =C2=A0 print ("Usage:")
>=C2=A0 =C2=A0 =C2=A0 print ("=C2=A0 =C2=A0 GenCfgOpt=C2=A0 UPDTXT= =C2=A0 PlatformDscFile BuildFvDir=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0[-D Macros]")
>=C2=A0 =C2=A0 =C2=A0 print ("=C2=A0 =C2=A0 GenCfgOpt=C2=A0 HEADER= =C2=A0 PlatformDscFile BuildFvDir=C2=A0 InputHFile=C2=A0 =C2=A0 =C2=A0[-D M= acros]")
> diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/Sp= litFspBin.py
> index f9151b5afd..317d9c1fa0 100644
> --- a/IntelFsp2Pkg/Tools/SplitFspBin.py
> +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py
> @@ -1,6 +1,6 @@
>=C2=A0 ## @ SplitFspBin.py
>=C2=A0 #
> -# Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.&= lt;BR>
> +# Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.&= lt;BR>
>=C2=A0 # SPDX-License-Identifier: BSD-2-Clause-Patent
>=C2=A0 #
>=C2=A0 ##
> @@ -492,7 +492,7 @@ class FspImage:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 self.FihOffset =3D fihoff
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 self.Offset=C2=A0 =C2=A0 =3D offset<= br> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 self.FvIdxList =3D []
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.Type=C2=A0 =C2=A0 =C2=A0 =3D "X= TMSXXXXOXXXXXXX"[(fih.ComponentAttribute >> 12) & 0x0F]
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 self.Type=C2=A0 =C2=A0 =C2=A0 =3D "X= TMSIXXXXOXXXXXXX"[(fih.ComponentAttribute >> 12) & 0x0F]
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 self.PatchList =3D patch
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 self.PatchList.append(fihoff + 0x1C)=
>=C2=A0
> @@ -869,7 +869,7 @@ def main ():
>=C2=A0 =C2=A0 =C2=A0 parser_rebase=C2=A0 =3D subparsers.add_parser('= ;rebase',=C2=A0 help=3D'rebase a FSP into a new base address')<= br> >=C2=A0 =C2=A0 =C2=A0 parser_rebase.set_defaults(which=3D'rebase'= ;)
>=C2=A0 =C2=A0 =C2=A0 parser_rebase.add_argument('-f',=C2=A0 = 9;--fspbin' , dest=3D'FspBinary',=C2=A0 type=3Dstr, help=3D'= ;FSP binary file path', required =3D True)
> -=C2=A0 =C2=A0 parser_rebase.add_argument('-c',=C2=A0 '--f= spcomp', choices=3D['t','m','s','o'],= =C2=A0 nargs=3D'+', dest=3D'FspComponent', type=3Dstr, help= =3D'FSP component to rebase', default =3D "['t']"= , required =3D True)
> +=C2=A0 =C2=A0 parser_rebase.add_argument('-c',=C2=A0 '--f= spcomp', choices=3D['t','m','s','o',= 9;i'],=C2=A0 nargs=3D'+', dest=3D'FspComponent', type= =3Dstr, help=3D'FSP component to rebase', default =3D "['t= ']", required =3D True)
>=C2=A0 =C2=A0 =C2=A0 parser_rebase.add_argument('-b',=C2=A0 = 9;--newbase', dest=3D'FspBase', nargs=3D'+', type=3Dstr= , help=3D'Rebased FSP binary file name', default =3D '', re= quired =3D True)
>=C2=A0 =C2=A0 =C2=A0 parser_rebase.add_argument('-o',=C2=A0 = 9;--outdir' , dest=3D'OutputDir',=C2=A0 type=3Dstr, help=3D'= ;Output directory path', default =3D '.')
>=C2=A0 =C2=A0 =C2=A0 parser_rebase.add_argument('-n',=C2=A0 = 9;--outfile', dest=3D'OutputFile', type=3Dstr, help=3D'Reba= sed FSP binary file name', default =3D '')
> --
> 2.35.0.windows.1








--
Pedro Falcato
--000000000000483baf05e41b59cd--