From: "Pedro Falcato" <pedro.falcato@gmail.com>
To: devel@edk2.groups.io, marcin.juszkiewicz@linaro.org
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>,
Leif Lindholm <quic_llindhol@quicinc.com>,
Rebecca Cran <rebecca@bsdio.com>
Subject: Re: [edk2-devel] [PATCH v3] add ArmCpuInfo EFI application
Date: Fri, 7 Apr 2023 14:02:27 +0100 [thread overview]
Message-ID: <CAKbZUD1iRLmFtBgRkdO_OhX0G204ZXUdnL+ttE3gVvgfCcPuOQ@mail.gmail.com> (raw)
In-Reply-To: <20230407124731.121236-1-marcin.juszkiewicz@linaro.org>
On Fri, Apr 7, 2023 at 1:47 PM Marcin Juszkiewicz
<marcin.juszkiewicz@linaro.org> wrote:
>
> App goes through ID_AA64*_EL1 system registers and decode their values.
>
> Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
> ArmPkg/ArmPkg.dsc | 1 +
> ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf | 38 +
> ArmPkg/Application/ArmCpuInfo/readargs.h | 12 +
> ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2317 ++++++++++++++++++++
> ArmPkg/Application/ArmCpuInfo/readregs.s | 49 +
> 5 files changed, 2417 insertions(+)
>
> diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc
> index 3fb95d1951a9..6b938ce8b671 100644
> --- a/ArmPkg/ArmPkg.dsc
> +++ b/ArmPkg/ArmPkg.dsc
> @@ -166,6 +166,7 @@ [Components.AARCH64]
> ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf
> ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
> ArmPkg/Library/ArmMmuLib/ArmMmuPeiLib.inf
> + ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf
>
> [Components.AARCH64, Components.ARM]
> ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.inf
> diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf
> new file mode 100644
> index 000000000000..158f86a4740c
> --- /dev/null
> +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.inf
> @@ -0,0 +1,38 @@
> +## @file
> +#
> +# Attempt to have AArch64 cpu information.
> +#
> +# Based on HelloWorld:
> +# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2023 Marcin Juszkiewicz
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010019
> + BASE_NAME = ArmCpuInfo
> + FILE_GUID = b3134491-6502-4faf-a9da-007184e32163
> + MODULE_TYPE = UEFI_APPLICATION
> + VERSION_STRING = 1.0
> + ENTRY_POINT = UefiMain
> +
> +#
> +# This flag specifies whether HII resource section is generated into PE image.
> +#
> + UEFI_HII_RESOURCE_SECTION = TRUE
> +
> +[Sources]
> + ArmCpuInfo.c
> + readregs.s
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> +
> +[LibraryClasses]
> + UefiApplicationEntryPoint
> + UefiLib
> diff --git a/ArmPkg/Application/ArmCpuInfo/readargs.h b/ArmPkg/Application/ArmCpuInfo/readargs.h
> new file mode 100644
> index 000000000000..eaa52cf16145
> --- /dev/null
> +++ b/ArmPkg/Application/ArmCpuInfo/readargs.h
> @@ -0,0 +1,12 @@
> +UINT64 read_aa64pfr0_el1(void);
> +UINT64 read_aa64pfr1_el1(void);
> +UINT64 read_aa64dfr0_el1(void);
> +UINT64 read_aa64dfr1_el1(void);
> +UINT64 read_aa64isar0_el1(void);
> +UINT64 read_aa64isar1_el1(void);
> +UINT64 read_aa64isar2_el1(void);
> +UINT64 read_aa64mmfr0_el1(void);
> +UINT64 read_aa64mmfr1_el1(void);
> +UINT64 read_aa64mmfr2_el1(void);
> +UINT64 read_aa64smfr0_el1(void);
> +UINT64 read_aa64zfr0_el1(void);
> diff --git a/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c
> new file mode 100644
> index 000000000000..6c31ad4dbcb9
> --- /dev/null
> +++ b/ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c
> @@ -0,0 +1,2317 @@
> +/** @file
> +
> + Copyright (c) 2023 Marcin Juszkiewicz
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> + **/
> +
> +#include <Library/UefiLib.h>
> +#include "readargs.h"
> +
> +void
> +print_text (
> + const char *field,
> + const char *bits,
> + const char *value,
> + const char *description
> + )
> +{
> + AsciiPrint (" %-16a | %5a | %5a | %a\n", field, bits, value, description);
> +}
> +
> +void
> +print_values (
> + const char *field,
> + const char *bits,
> + const int value,
> + const char *description
> + )
> +{
> + STATIC CONST CHAR8 binaries[][5] = {
> + "0000", "0001", "0010", "0011",
> + "0100", "0101", "0110", "0111","1000", "1001", "1010", "1011",
> + "1100", "1101", "1110", "1111"
> + };
> +
> + AsciiPrint (" %-16a | %5a | %5a | %a\n", field, bits, binaries[value & 0xf], description);
> +}
> +
> +void
> +print_spacer (
> + void
> + )
> +{
> + AsciiPrint ("------------------|-------|-------|----------------------------------------------\n");
> +}
> +
> +void
> +handle_aa64mmfr0_el1 (
> + const UINT64 aa64mmfr0_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64MMFR0_EL1";
> + char *description;
> + char *bits;
> +
> + bits = "3:0 ";
> + value = aa64mmfr0_el1 & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "32 bits (4GB) of physical address range supported.";
> + break;
> + case 0b0001:
> + description = "36 bits (64GB) of physical address range supported.";
> + break;
> + case 0b0010:
> + description = "40 bits (1TB) of physical address range supported.";
> + break;
> + case 0b0011:
> + description = "42 bits (4TB) of physical address range supported.";
> + break;
> + case 0b0100:
> + description = "44 bits (16TB) of physical address range supported.";
> + break;
> + case 0b0101:
> + description = "48 bits (256TB) of physical address range supported.";
> + break;
> + case 0b0110:
> + description = "52 bits (4PB) of physical address range supported.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> + if (value == 0b0110) {
> + print_text ("", "", "", "FEAT_LPA implemented.");
> + }
> +
> + bits = "7:4 ";
> + value = (aa64mmfr0_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "ASID: 8 bits";
> + break;
> + case 0b0010:
> + description = "ASID: 16 bits";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "11:8 ";
> + value = (aa64mmfr0_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "No mixed-endian support.";
> + break;
> + case 0b0001:
> + description = "Mixed-endian support.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // only valid for BigEnd != 0b0000
> + if (((aa64mmfr0_el1 >> 8) & 0xf) != 0b0000 ) {
> + if (((aa64mmfr0_el1 >> 16) & 0xf) == 0b0000 ) {
> + print_values ("ID_AA64MMFR0_EL1", "19:16", 0b0000, "No mixed-endian support at EL0.");
> + }
> +
> + if (((aa64mmfr0_el1 >> 16) & 0xf) == 0b0001 ) {
> + print_values ("ID_AA64MMFR0_EL1", "19:16", 0b0001, "Mixed-endian support at EL0.");
> + }
> + }
> +
> + bits = "15:12";
> + value = (aa64mmfr0_el1 >> 12) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "No support for a distinction between Secure and Non-Secure Memory.";
> + break;
> + case 0b0001:
> + description = "Supports a distinction between Secure and Non-Secure Memory.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "31:28";
> + value = (aa64mmfr0_el1 >> 28) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = " 4KB granule supported.";
> + break;
> + case 0b1111:
> + description = " 4KB granule not supported.";
> + break;
> + case 0b0001: // add FEAT_LPA2 check
> + description = " 4KB granule supported for 52-bit address.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "43:40";
> + value = (aa64mmfr0_el1 >> 40) & 0xf;
> + switch (value) {
> + case 0b0001:
> + description = " 4KB granule not supported at stage 2.";
> + break;
> + case 0b0010:
> + description = " 4KB granule supported at stage 2.";
> + break;
> + case 0b0011:
> + description = " 4KB granule supported at stage 2 for 52-bit address.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "23:20";
> + value = (aa64mmfr0_el1 >> 20) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "16KB granule not supported.";
> + break;
> + case 0b0001:
> + description = "16KB granule supported.";
> + break;
> + case 0b0010: // add FEAT_LPA2 check
> + description = "16KB granule supported for 52-bit address.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "35:32";
> + value = (aa64mmfr0_el1 >> 32) & 0xf;
> + switch (value) {
> + case 0b0001:
> + description = "16KB granule not supported at stage 2.";
> + break;
> + case 0b0010:
> + description = "16KB granule supported at stage 2.";
> + break;
> + case 0b0011:
> + description = "16KB granule supported at stage 2 for 52-bit address.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "27:24";
> + value = (aa64mmfr0_el1 >> 24) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "64KB granule supported.";
> + break;
> + case 0b1111:
> + description = "64KB granule not supported.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "39:36";
> + value = (aa64mmfr0_el1 >> 36) & 0xf;
> + switch (value) {
> + case 0b0001:
> + description = "64KB granule not supported at stage 2.";
> + break;
> + case 0b0010:
> + description = "64KB granule supported at stage 2.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "47:44";
> + value = (aa64mmfr0_el1 >> 44) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_ExS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_ExS implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 55:48 reserved
> +
> + bits = "59:56";
> + value = (aa64mmfr0_el1 >> 56) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_FGT not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_FGT implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "63:60";
> + value = (aa64mmfr0_el1 >> 60) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_ECV not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_ECV implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_ECV implemented with extras.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +}
> +
> +void
> +handle_aa64mmfr1_el1 (
> + const UINT64 aa64mmfr1_el1,
> + const UINT64 aa64pfr0_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64MMFR1_EL1";
> + char *description;
> + char *bits;
> +
> + bits = "3:0 ";
> + value = aa64mmfr1_el1 & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_HAFDBS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_HAFDBS implemented without dirty status support.";
> + break;
> + case 0b0010:
> + description = "FEAT_HAFDBS implemented with dirty status support.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "7:4 ";
> + value = (aa64mmfr1_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_VMID16 not implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_VMID16 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "11:8 ";
> + value = (aa64mmfr1_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_VHE not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_VHE implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "15:12";
> + value = (aa64mmfr1_el1 >> 12) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_HPDS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_HPDS implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_HPDS2 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "19:16";
> + value = (aa64mmfr1_el1 >> 16) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_LOR not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_LOR implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "23:20";
> + value = (aa64mmfr1_el1 >> 20) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_PAN not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_PAN implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_PAN2 implemented.";
> + break;
> + case 0b0011:
> + description = "FEAT_PAN3 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // when FEAT_RAS implemented
> + if ((((aa64pfr0_el1 >> 28) & 0xf) == 0b0001) ||
> + (((aa64pfr0_el1 >> 28) & 0xf) == 0b0010))
> + {
> + if (((aa64mmfr1_el1 >> 24) & 0xf) == 0b0000 ) {
> + print_values ("ID_AA64MMFR1_EL1", "27:24", 0b0000, "The PE never generates an SError interrupt due to");
> + print_text ("", "", "", "an External abort on a speculative read.");
> + }
> +
> + if (((aa64mmfr1_el1 >> 24) & 0xf) == 0b0001 ) {
> + print_values ("ID_AA64MMFR1_EL1", "27:24", 0b0001, "The PE might generate an SError interrupt due to");
> + print_text ("", "", "", "an External abort on a speculative read.");
> + }
> + }
> +
> + bits = "31:28";
> + value = (aa64mmfr1_el1 >> 28) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_XNX not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_XNX implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "35:32";
> + value = (aa64mmfr1_el1 >> 32) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_TWED not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_TWED implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "39:36";
> + value = (aa64mmfr1_el1 >> 36) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_ETS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_ETS implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "43:40";
> + value = (aa64mmfr1_el1 >> 40) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_HCX not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_HCX implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "47:44";
> + value = (aa64mmfr1_el1 >> 44) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_AFP not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_AFP implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "51:48";
> + value = (aa64mmfr1_el1 >> 48) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_nTLBPA not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_nTLBPA implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "55:52";
> + value = (aa64mmfr1_el1 >> 52) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_TIDCP1 not implemented";
> + break;
> + case 0b0001:
> + description = "FEAT_TIDCP1 implemented";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "59:56";
> + value = (aa64mmfr1_el1 >> 56) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_CMOW not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_CMOW implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 63:60 reserved
> +}
> +
> +void
> +handle_aa64mmfr2_el1 (
> + const UINT64 aa64mmfr2_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64MMFR2_EL1";
> + char *description;
> + char *bits;
> +
> + bits = "3:0 ";
> + value = (aa64mmfr2_el1) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_TTCNP not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_TTCNP implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "7:4 ";
> + value = (aa64mmfr2_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_UAO not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_UAO implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "11:8 ";
> + value = (aa64mmfr2_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_LSMAOC not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_LSMAOC implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "15:12";
> + value = (aa64mmfr2_el1 >> 12) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_IESB not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_IESB implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "19:16";
> + value = (aa64mmfr2_el1 >> 16) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_LVA not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_LVA implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "23:20";
> + value = (aa64mmfr2_el1 >> 20) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_CCIDX not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_CCIDX implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "27:24";
> + value = (aa64mmfr2_el1 >> 24) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_NV not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_NV implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_NV2 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "31:28";
> + value = (aa64mmfr2_el1 >> 28) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_TTST not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_TTST implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "35:32";
> + value = (aa64mmfr2_el1 >> 32) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_LSE2 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_LSE2 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "39:36";
> + value = (aa64mmfr2_el1 >> 36) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_IDST not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_IDST implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "43:40";
> + value = (aa64mmfr2_el1 >> 40) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_S2FWB not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_S2FWB implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 47:44 reserved
> +
> + bits = "51:48";
> + value = (aa64mmfr2_el1 >> 48) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_TTL not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_TTL implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "55:52";
> + value = (aa64mmfr2_el1 >> 52) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_BBM: Level 0 support for changing block size is supported.";
> + break;
> + case 0b0001:
> + description = "FEAT_BBM: Level 1 support for changing block size is supported.";
> + break;
> + case 0b0010:
> + description = "FEAT_BBM: Level 2 support for changing block size is supported.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "59:56";
> + value = (aa64mmfr2_el1 >> 56) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_EVT not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_EVT: HCR_EL2.{TOCU, TICAB, TID4} traps are supported.";
> + break;
> + case 0b0010:
> + description = "FEAT_EVT: HCR_EL2.{TTLBOS, TTLSBIS, TOCU, TICAB, TID4} traps are supported.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "63:60";
> + value = (aa64mmfr2_el1 >> 60) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_E0PD not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_E0PD implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +}
> +
> +void
> +handle_aa64pfr0_el1 (
> + const UINT64 aa64pfr0_el1,
> + const UINT64 aa64pfr1_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64PFR0_EL1";
> + char *description;
> + char *bits;
> +
> + bits = "3:0 ";
> + value = (aa64pfr0_el1) & 0xf;
> + switch (value) {
> + case 0b0001:
> + description = "EL0 in AArch64 only";
> + break;
> + case 0b0010:
> + description = "EL0 in AArch64 and AArch32";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "7:4 ";
> + value = (aa64pfr0_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0001:
> + description = "EL1 in AArch64 only";
> + break;
> + case 0b0010:
> + description = "EL1 in AArch64 and AArch32";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "11:8 ";
> + value = (aa64pfr0_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "EL2 not implemented.";
> + break;
> + case 0b0001:
> + description = "EL2 in AArch64 only";
> + break;
> + case 0b0010:
> + description = "EL2 in AArch64 and AArch32";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "15:12";
> + value = (aa64pfr0_el1 >> 12) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "EL3 not implemented.";
> + break;
> + case 0b0001:
> + description = "EL3 in AArch64 only";
> + break;
> + case 0b0010:
> + description = "EL3 in AArch64 and AArch32";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "19:16";
> + value = (aa64pfr0_el1 >> 16) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Floating-point implemented.";
> + break;
> + case 0b0001:
> + description = "Floating-point with half-precision support (FEAT_FP16).";
> + break;
> + case 0b1111:
> + description = "Floating-point not implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "23:20";
> + value = (aa64pfr0_el1 >> 20) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Advanced SIMD implemented.";
> + break;
> + case 0b0001:
> + description = "Advanced SIMD with half precision support (FEAT_FP16).";
> + break;
> + case 0b1111:
> + description = "Advanced SIMD not implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "27:24";
> + value = (aa64pfr0_el1 >> 24) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "System registers of GIC CPU not implemented.";
> + break;
> + case 0b0001:
> + description = "System registers to versions 3.0/4.0 of GIC CPU implemented.";
> + break;
> + case 0b0011:
> + description = "System registers to versions 4.1 of GIC CPU implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "31:28";
> + value = (aa64pfr0_el1 >> 28) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_RAS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_RAS implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_RASv1p1 implemented.";
> + // 0b0010 FEAT_RASv1p1 implemented and, if EL3 is implemented, FEAT_DoubleFault implemented.
> + if ((((aa64pfr0_el1 >> 12) & 0xf) == 0b0001) ||
> + (((aa64pfr0_el1 >> 12) & 0xf) == 0b0010))
> + {
> + description = "FEAT_RASv1p1 implemented. FEAT_DoubleFault implemented.";
> + }
> +
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "35:32";
> + value = (aa64pfr0_el1 >> 32) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SVE not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SVE implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "39:36";
> + value = (aa64pfr0_el1 >> 36) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Secure EL2 not implemented.";
> + break;
> + case 0b0001:
> + description = "Secure EL2 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "43:40";
> + value = (aa64pfr0_el1 >> 40) & 0xf;
> + switch (value) {
> + case 0b0000:
> + if (((aa64pfr1_el1 >> 16) & 0xf) == 0b0000 ) {
> + description = "FEAT_MPAM not implemented.";
> + }
> +
> + if (((aa64pfr1_el1 >> 16) & 0xf) == 0b0001 ) {
> + description = "FEAT_MPAM v0.1 implemented.";
> + }
> +
> + break;
> + case 0b0001:
> + if (((aa64pfr1_el1 >> 16) & 0xf) == 0b0000 ) {
> + description = "FEAT_MPAM v1.0 implemented.";
> + }
> +
> + if (((aa64pfr1_el1 >> 16) & 0xf) == 0b0001 ) {
> + description = "FEAT_MPAM v1.1 implemented.";
> + }
> +
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "47:44";
> + value = (aa64pfr0_el1 >> 44) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_AMU not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_AMUv1 implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_AMUv1p1 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "51:48";
> + value = (aa64pfr0_el1 >> 48) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_DIT not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_DIT implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "55:52";
> + value = (aa64pfr0_el1 >> 52) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_RME not implemented";
> + break;
> + case 0b0001:
> + description = "FEAT_RME implemented";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "59:56";
> + value = (aa64pfr0_el1 >> 56) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "no info is FEAT_CSV2 implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_CSV2 implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_CSV2_2 implemented.";
> + break;
> + case 0b0011:
> + description = "FEAT_CSV2_3 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> + if (value == 0b0001) {
> + if (((aa64pfr1_el1 >> 32) & 0xf) == 0b0001 ) {
> + print_values ("ID_AA64PRF1_EL1", "35:32", 0b0001, "FEAT_CSV2_1p1 implemented.");
> + }
> +
> + if (((aa64pfr1_el1 >> 32) & 0xf) == 0b0010 ) {
> + print_values ("ID_AA64PRF1_EL1", "35:32", 0b0010, "FEAT_CSV2_1p2 implemented.");
> + }
> + }
> +
> + bits = "63:60";
> + value = (aa64pfr0_el1 >> 60) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_CSV3 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_CSV3 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +}
> +
> +void
> +handle_aa64pfr1_el1 (
> + const UINT64 aa64pfr1_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64PFR1_EL1";
> + char *description;
> + char *bits;
> +
> + bits = "3:0 ";
> + value = aa64pfr1_el1 & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_BTI not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_BTI implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "7:4 ";
> + value = (aa64pfr1_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SSBS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SSBS implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_SSBS2 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "11:8 ";
> + value = (aa64pfr1_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_MTE not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_MTE implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_MTE2 implemented.";
> + break;
> + case 0b0011:
> + description = "FEAT_MTE3 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 15:12 is RAS_frac
> + // 19:16 is MPAM_frac
> + // 23:20 is reserved
> +
> + bits = "27:24";
> + value = (aa64pfr1_el1 >> 24) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SME not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SME implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "31:28";
> + value = (aa64pfr1_el1 >> 28) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_RNG_TRAP not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_RNG_TRAP implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 35:32 is CSV2_frac
> +
> + bits = "39:36";
> + value = (aa64pfr1_el1 >> 36) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_NMI not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_NMI implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 63:40 are reserved
> +}
> +
> +void
> +handle_aa64isar0_el1 (
> + const UINT64 aa64isar0_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64ISAR0_EL1";
> + char *description;
> + char *bits;
> +
> + // 3:0 reserved
> +
> + bits = "7:4 ";
> + value = (aa64isar0_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_AES, FEAT_PMULL not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_AES implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_AES and FEAT_PMULL implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "11:8 ";
> + value = (aa64isar0_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SHA1 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SHA1 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "15:12";
> + value = (aa64isar0_el1 >> 12) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SHA256, FEAT_SHA512 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SHA256 implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_SHA512 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "19:16";
> + value = (aa64isar0_el1 >> 16) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "CRC32 not implemented.";
> + break;
> + case 0b0001:
> + description = "CRC32 instructions implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "23:20";
> + value = (aa64isar0_el1 >> 20) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_LSE not implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_LSE implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "27:24";
> + value = (aa64isar0_el1 >> 24) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "TME instructions not implemented.";
> + break;
> + case 0b0001:
> + description = "TME instructions implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "31:28";
> + value = (aa64isar0_el1 >> 28) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_RDM not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_RDM implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "35:32";
> + value = (aa64isar0_el1 >> 32) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SHA3 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SHA3 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "39:36";
> + value = (aa64isar0_el1 >> 36) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SM3 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SM3 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "43:40";
> + value = (aa64isar0_el1 >> 40) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SM4 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SM4 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "47:44";
> + value = (aa64isar0_el1 >> 44) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_DotProd not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_DotProd implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "51:48";
> + value = (aa64isar0_el1 >> 48) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_FHM not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_FHM implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "55:52";
> + value = (aa64isar0_el1 >> 52) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_FlagM/FEAT_FlagM2 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_FlagM implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_FlagM2 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "59:56";
> + value = (aa64isar0_el1 >> 56) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_TLBIOS/FEAT_TLBIRANGE not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_TLBIOS implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_TLBIRANGE implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "63:60";
> + value = (aa64isar0_el1 >> 60) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_RNG not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_RNG implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +}
> +
> +void
> +handle_aa64isar1_el1 (
> + const UINT64 aa64isar1_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64ISAR1_EL1";
> + char *description;
> + char *bits;
> +
> + bits = "3:0 ";
> + value = (aa64isar1_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "DC CVAP not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_DPB implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_DPB2 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "7:4 ";
> + value = (aa64isar1_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Address Authentication (APA) not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_PAuth implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_EPAC implemented.";
> + break;
> + case 0b0011:
> + description = "FEAT_PAuth2 implemented.";
> + break;
> + case 0b0100:
> + description = "FEAT_FPAC implemented.";
> + break;
> + case 0b0101:
> + description = "FEAT_FPACCOMBINE implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> + if (value > 0) {
> + print_text ("", "", "", "FEAT_PACQARMA5 implemented.");
> + }
> +
> + bits = "11:8 ";
> + value = (aa64isar1_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Address Authentication (API) not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_PAuth implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_EPAC implemented.";
> + break;
> + case 0b0011:
> + description = "FEAT_PAuth2 implemented.";
> + break;
> + case 0b0100:
> + description = "FEAT_FPAC implemented.";
> + break;
> + case 0b0101:
> + description = "FEAT_FPACCOMBINE implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> + if (value > 0) {
> + print_text ("", "", "", "FEAT_PACIMP implemented.");
> + }
> +
> + bits = "15:12";
> + value = (aa64isar1_el1 >> 12) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_JSCVT not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_JSCVT implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "19:16";
> + value = (aa64isar1_el1 >> 16) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_FCMA not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_FCMA implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "23:20";
> + value = (aa64isar1_el1 >> 20) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_LRCPC (2) not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_LRCPC implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_LRCPC2 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "27:24";
> + value = (aa64isar1_el1 >> 24) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_PACQARMA5 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_PACQARMA5 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "31:28";
> + value = (aa64isar1_el1 >> 28) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_PACIMP not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_PACIMP implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "35:32";
> + value = (aa64isar1_el1 >> 32) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_FRINTTS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_FRINTTS implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "39:36";
> + value = (aa64isar1_el1 >> 36) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SB not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SB implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "43:40";
> + value = (aa64isar1_el1 >> 40) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SPECRES not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SPECRES implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "47:44";
> + value = (aa64isar1_el1 >> 44) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_BF16 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_BF16 implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_EBF16 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "51:48";
> + value = (aa64isar1_el1 >> 48) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_DGH not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_DGH implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "55:52";
> + value = (aa64isar1_el1 >> 52) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_I8MM not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_I8MM implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "59:56";
> + value = (aa64isar1_el1 >> 56) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_XS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_XS implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "63:60";
> + value = (aa64isar1_el1 >> 60) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_LS64 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_LS64 implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_LS64_V implemented.";
> + break;
> + case 0b0011:
> + description = "FEAT_LS64_ACCDATA implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +}
> +
> +void
> +handle_aa64isar2_el1 (
> + const UINT64 aa64isar2_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64ISAR2_EL1";
> + char *description;
> + char *bits;
> +
> + bits = "3:0 ";
> + value = (aa64isar2_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_WFxT not implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_WFxT implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "7:4 ";
> + value = (aa64isar2_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_RPRES not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_RPRES implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "11:8 ";
> + value = (aa64isar2_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_PACQARMA3 not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_PACQARMA3 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "15:12";
> + value = (aa64isar2_el1 >> 12) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Address Authentication (APA3) not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_PAuth implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_EPAC implemented.";
> + break;
> + case 0b0011:
> + description = "FEAT_PAuth2 implemented.";
> + break;
> + case 0b0100:
> + description = "FEAT_FPAC implemented.";
> + break;
> + case 0b0101:
> + description = "FEAT_FPACCOMBINE implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "19:16";
> + value = (aa64isar2_el1 >> 16) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_MOPS not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_MOPS implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "23:20";
> + value = (aa64isar2_el1 >> 20) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_HBC not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_HBC implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "27:24";
> + value = (aa64isar2_el1 >> 24) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_CONSTPACFIELD not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_CONSTPACFIELD implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 63:28 reserved
> +}
> +
> +void
> +handle_aa64dfr0_el1 (
> + const UINT64 aa64dfr0_el1
> + )
> +{
> + UINT64 value;
> + STATIC CONST CHAR8 RegName[] = "ID_AA64DFR0_EL1";
> + char *description;
> + char *bits;
> +
> + bits = "3:0 ";
> + value = (aa64dfr0_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0110:
> + description = "Armv8 debug architecture";
> + break;
> + case 0b0111:
> + description = "Armv8 debug architecture with VHE";
> + break;
> + case 0b1000:
> + description = "FEAT_Debugv8p2 implemented.";
> + break;
> + case 0b1001:
> + description = "FEAT_Debugv8p4 implemented.";
> + break;
> + case 0b1010:
> + description = "FEAT_Debugv8p8 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "7:4 ";
> + value = (aa64dfr0_el1 >> 4) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Trace unit System registers not implemented.";
> + break;
> + case 0b0001:
> + description = "Trace unit System registers implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "11:8 ";
> + value = (aa64dfr0_el1 >> 8) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Performance Monitors Extension not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_PMUv3 implemented.";
> + break;
> + case 0b0100:
> + description = "FEAT_PMUv3p1 implemented.";
> + break;
> + case 0b0101:
> + description = "FEAT_PMUv3p4 implemented.";
> + break;
> + case 0b0110:
> + description = "FEAT_PMUv3p5 implemented.";
> + break;
> + case 0b0111:
> + description = "FEAT_PMUv3p7 implemented.";
> + break;
> + case 0b1000:
> + description = "FEAT_PMUv3p8 implemented.";
> + break;
> + case 0b1111:
> + description = "IMPLEMENTATION DEFINED form of performance monitors supported.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "15:12";
> + value = (aa64dfr0_el1 >> 12) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "reserved";
> + break;
> + default:
> + description = "Number of breakpoints, minus 1.";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 19:16 reserved
> +
> + bits = "23:20";
> + value = (aa64dfr0_el1 >> 20) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "reserved";
> + break;
> + default:
> + description = "Number of watchpoints, minus 1.";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 27:24 reserved
> +
> + bits = "31:28";
> + value = (aa64dfr0_el1 >> 28) & 0xf;
> + switch (value) {
> + default:
> + description = "Number of breakpoints that are context-aware, minus 1.";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "35:32";
> + value = (aa64dfr0_el1 >> 32) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_SPE not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_SPE implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_SPEv1p1 implemented.";
> + break;
> + case 0b0011:
> + description = "FEAT_SPEv1p2 implemented.";
> + break;
> + case 0b0100:
> + description = "FEAT_SPEv1p3 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "39:36";
> + value = (aa64dfr0_el1 >> 36) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_DoubleLock implemented.";
> + break;
> + case 0b1111:
> + description = "FEAT_DoubleLock not implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "43:40";
> + value = (aa64dfr0_el1 >> 40) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_TRF not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_TRF implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "47:44";
> + value = (aa64dfr0_el1 >> 44) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_TRBE not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_TRBE implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "51:48";
> + value = (aa64dfr0_el1 >> 48) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_MTPMU not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_MTPMU and FEAT_PMUv3 implemented.";
> + break;
> + case 0b1111:
> + description = "FEAT_MTPMU not implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + bits = "55:52";
> + value = (aa64dfr0_el1 >> 52) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "FEAT_BRBE not implemented.";
> + break;
> + case 0b0001:
> + description = "FEAT_BRBE implemented.";
> + break;
> + case 0b0010:
> + description = "FEAT_BRBEv1p1 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +
> + // 59:56 reserved
> +
> + bits = "63:60";
> + value = (aa64dfr0_el1 >> 60) & 0xf;
> + switch (value) {
> + case 0b0000:
> + description = "Setting MDCR_EL2.HPMN to zero has CONSTRAINED UNPREDICTABLE behavior.";
> + break;
> + case 0b0001:
> + description = "FEAT_HPMN0 implemented.";
> + break;
> + default:
> + description = "unknown";
> + break;
> + }
> +
> + print_values (RegName, bits, value, description);
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +UefiMain (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + UINT64 aa64dfr0_el1 = read_aa64dfr0_el1 ();
> + UINT64 aa64dfr1_el1 = read_aa64dfr1_el1 ();
> + UINT64 aa64isar0_el1 = read_aa64isar0_el1 ();
> + UINT64 aa64isar1_el1 = read_aa64isar1_el1 ();
> + UINT64 aa64isar2_el1 = read_aa64isar2_el1 ();
> + UINT64 aa64mmfr0_el1 = read_aa64mmfr0_el1 ();
> + UINT64 aa64mmfr1_el1 = read_aa64mmfr1_el1 ();
> + UINT64 aa64mmfr2_el1 = read_aa64mmfr2_el1 ();
> + UINT64 aa64pfr0_el1 = read_aa64pfr0_el1 ();
> + UINT64 aa64pfr1_el1 = read_aa64pfr1_el1 ();
EDK2 requires separation between declarations and code (something
alike old C89 semantics, but stricter). so:
UINT64 aa64pfr1_el1;
<...>
aa64pfr1_el1 = read_aa64pfr1_el1 ();
> +
> + /* UINT64 aa64smfr0_el1 = read_aa64smfr0_el1 ();*/
> + /* UINT64 aa64zfr0_el1 = read_aa64zfr0_el1 ();*/
Dead Code?
> +
> + AsciiPrint ("ID_AA64MMFR0_EL1 = 0x%016lx\n", aa64mmfr0_el1);
> + AsciiPrint ("ID_AA64MMFR1_EL1 = 0x%016lx\n", aa64mmfr1_el1);
> + AsciiPrint ("ID_AA64MMFR2_EL1 = 0x%016lx\n", aa64mmfr2_el1);
> + AsciiPrint ("ID_AA64PFR0_EL1 = 0x%016lx\n", aa64pfr0_el1);
> + AsciiPrint ("ID_AA64PFR1_EL1 = 0x%016lx\n", aa64pfr1_el1);
> + AsciiPrint ("ID_AA64ISAR0_EL1 = 0x%016lx\n", aa64isar0_el1);
> + AsciiPrint ("ID_AA64ISAR1_EL1 = 0x%016lx\n", aa64isar1_el1);
> + AsciiPrint ("ID_AA64ISAR2_EL1 = 0x%016lx\n", aa64isar2_el1);
> + AsciiPrint ("ID_AA64DFR0_EL1 = 0x%016lx\n", aa64dfr0_el1);
> + AsciiPrint ("ID_AA64DFR1_EL1 = 0x%016lx\n", aa64dfr1_el1); // ignore
Why ignore?
> + /* AsciiPrint ("ID_AA64SMFR0_EL1 = 0x%016lx\n", aa64smfr0_el1);*/
> + /* AsciiPrint ("ID_AA64ZFR0_EL1 = 0x%016lx\n", aa64zfr0_el1);*/
dead?
> +
> + AsciiPrint ("\n");
> + print_text ("Register", "Bits", "Value", "Feature");
> + print_spacer ();
> +
> + handle_aa64mmfr0_el1 (aa64mmfr0_el1);
> + print_spacer ();
> + handle_aa64mmfr1_el1 (aa64mmfr1_el1, aa64pfr0_el1);
> + print_spacer ();
> + handle_aa64mmfr2_el1 (aa64mmfr2_el1);
> +
> + print_spacer ();
> + handle_aa64pfr0_el1 (aa64pfr0_el1, aa64pfr1_el1);
> + print_spacer ();
> + handle_aa64pfr1_el1 (aa64pfr1_el1);
> +
> + print_spacer ();
> + handle_aa64isar0_el1 (aa64isar0_el1);
> + print_spacer ();
> + handle_aa64isar1_el1 (aa64isar1_el1);
> + print_spacer ();
> + handle_aa64isar2_el1 (aa64isar2_el1);
> +
> + print_spacer ();
> + handle_aa64dfr0_el1 (aa64dfr0_el1);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/ArmPkg/Application/ArmCpuInfo/readregs.s b/ArmPkg/Application/ArmCpuInfo/readregs.s
ASM files that require preprocessing should have a capital S here (.S vs .s)
> new file mode 100644
> index 000000000000..052834b3c3f2
> --- /dev/null
> +++ b/ArmPkg/Application/ArmCpuInfo/readregs.s
> @@ -0,0 +1,49 @@
> +#include <AsmMacroIoLibV8.h>
> +
> +ASM_FUNC(read_aa64pfr0_el1)
> + mrs x0, ID_AA64PFR0_EL1;
> + ret;
ASM lines (for GAS at least) don't usually end in semicolons. so
+ASM_FUNC(read_aa64pfr0_el1)
+ mrs x0, ID_AA64PFR0_EL1
+ ret
You'd only need the semicolons if you had multiple instructions in one
line (like mrs x0, ID_AA...; ret)
> +
> +ASM_FUNC(read_aa64pfr1_el1)
> + mrs x0, ID_AA64PFR1_EL1;
> + ret;
> +
> +ASM_FUNC(read_aa64dfr0_el1)
> + mrs x0, ID_AA64DFR0_EL1;
> + ret;
> +
> +ASM_FUNC(read_aa64dfr1_el1)
> + mrs x0, ID_AA64DFR1_EL1;
> + ret;
> +
> +ASM_FUNC(read_aa64isar0_el1)
> + mrs x0, ID_AA64ISAR0_EL1;
> + ret;
> +
> +ASM_FUNC(read_aa64isar1_el1)
> + mrs x0, ID_AA64ISAR1_EL1;
> + ret;
> +
> +ASM_FUNC(read_aa64isar2_el1)
> + mrs x0, ID_AA64ISAR2_EL1;
> + ret;
> +
> +ASM_FUNC(read_aa64mmfr0_el1)
> + mrs x0, ID_AA64MMFR0_EL1;
> + ret;
> +
> +ASM_FUNC(read_aa64mmfr1_el1)
> + mrs x0, ID_AA64MMFR1_EL1;
> + ret;
> +
> +ASM_FUNC(read_aa64mmfr2_el1)
> + mrs x0, ID_AA64MMFR2_EL1;
> + ret;
> +
> +# ASM_FUNC(read_aa64zfr0_el1)
> +# mrs x0, ID_AA64ZFR0_EL1;
> +# ret;
> +
> +# ASM_FUNC(read_aa64smfr0_el1)
> +# mrs x0, ID_AA64SMFR0_EL1;
> +# ret;
Dead code?
> --
> 2.40.0
Marcin,
Brief comments in general:
1) You use binary literals extensively, which are not portable (GNU C
extension, AFAIK not in MSVC)
2) Naming of identifiers (vars, functions, etc) needs to follow the
EDK2 style. eg:
description vs Description
read_aa64mmfr1_el1 vs ReadAa64MmfrEl1
etc...
--
Pedro
next prev parent reply other threads:[~2023-04-07 13:02 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-31 18:02 [PATCH] add ArmCpuInfo EFI application Marcin Juszkiewicz
2023-04-06 21:05 ` [edk2-devel] " Rebecca Cran
2023-04-07 10:39 ` [PATCH v2] " Marcin Juszkiewicz
2023-04-07 10:55 ` [edk2-devel] " Ard Biesheuvel
2023-04-07 12:46 ` Marcin Juszkiewicz
2023-04-07 13:07 ` Ard Biesheuvel
2023-04-07 12:47 ` [PATCH v3] " Marcin Juszkiewicz
2023-04-07 13:02 ` Pedro Falcato [this message]
2023-04-07 13:05 ` [edk2-devel] " Pedro Falcato
2023-04-07 13:29 ` Marcin Juszkiewicz
2023-04-07 13:40 ` Pedro Falcato
2023-04-07 13:41 ` Pedro Falcato
2023-04-07 13:42 ` Marcin Juszkiewicz
2023-04-07 14:02 ` [PATCH v4] " Marcin Juszkiewicz
[not found] ` <1753ABF1A296B040.11304@groups.io>
2023-04-07 15:11 ` [edk2-devel] " Marcin Juszkiewicz
2023-04-07 15:29 ` [PATCH v5 0/2] add ArmCpuInfo application Marcin Juszkiewicz
2023-04-07 15:29 ` [PATCH v5 1/2] ArmLib: add functions to read system registers Marcin Juszkiewicz
2023-04-20 10:54 ` Leif Lindholm
2023-04-07 15:29 ` [PATCH v5 2/2] add ArmCpuInfo EFI application Marcin Juszkiewicz
2023-04-20 12:43 ` Leif Lindholm
2023-04-20 14:42 ` [edk2-devel] " Marcin Juszkiewicz
2023-04-20 14:44 ` [PATCH v6 1/2] ArmLib: add functions to read system registers Marcin Juszkiewicz
2023-04-20 14:44 ` [PATCH v6 2/2] add ArmCpuInfo EFI application Marcin Juszkiewicz
2023-04-20 17:29 ` Leif Lindholm
2023-04-21 14:37 ` [edk2-devel] " Rebecca Cran
2023-04-21 14:59 ` Marcin Juszkiewicz
2023-04-21 15:15 ` Rebecca Cran
2023-04-21 15:51 ` [PATCH v7 1/2] ArmLib: add functions to read system registers Marcin Juszkiewicz
2023-04-21 15:51 ` [PATCH v7 2/2] add ArmCpuInfo EFI application Marcin Juszkiewicz
2023-04-21 20:18 ` Leif Lindholm
2023-04-21 16:33 ` [edk2-devel] [PATCH v6 " Leif Lindholm
2023-04-13 9:31 ` [PATCH v5 0/2] add ArmCpuInfo application Marcin Juszkiewicz
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