From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 08A40AC16A4 for ; Sun, 29 Oct 2023 19:12:34 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=D5PW0m0xeOqMjFeTj+OCHaV1RrnhasqNsTLjeqIQBpE=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1698606753; v=1; b=d2kTE1tU2a5Mln3soDzn8d57taRoz3b5yY4h5yNag8khQX372xADnOAyGvMHNFdkCcIwLm2f 3MQWxJW3U0+XuHJVQ0VP+wpbTYFo1HmV+XSI7w4WQOw8J4jErhZ8NRSQO5PEhd1MXaqDui+Cr/f zDNJYvIjJU3jmFv+u2su9OAs= X-Received: by 127.0.0.2 with SMTP id NzBMYY7687511xTyBUROdugR; Sun, 29 Oct 2023 12:12:33 -0700 X-Received: from mail-vk1-f182.google.com (mail-vk1-f182.google.com [209.85.221.182]) by mx.groups.io with SMTP id smtpd.web11.78785.1698606753059162605 for ; Sun, 29 Oct 2023 12:12:33 -0700 X-Received: by mail-vk1-f182.google.com with SMTP id 71dfb90a1353d-49dc95be8c3so1542084e0c.0 for ; Sun, 29 Oct 2023 12:12:32 -0700 (PDT) X-Gm-Message-State: LfPHsFhzsRIr3ACH0guHgMM1x7686176AA= X-Google-Smtp-Source: AGHT+IG5QzDf7aDqsKMiy7K3UvUqgk7+/dLRrzUuXTiEDjHby9fII+c5fWtsgIS8joLuWUn+p535W3RyEoKmhIhgP1s= X-Received: by 2002:a67:b24a:0:b0:45a:9bd5:b38a with SMTP id s10-20020a67b24a000000b0045a9bd5b38amr4622337vsh.19.1698606751849; Sun, 29 Oct 2023 12:12:31 -0700 (PDT) MIME-Version: 1.0 References: <20231029144613.150580-1-dhaval@rivosinc.com> <20231029144613.150580-4-dhaval@rivosinc.com> In-Reply-To: <20231029144613.150580-4-dhaval@rivosinc.com> From: "Pedro Falcato" Date: Sun, 29 Oct 2023 19:12:20 +0000 Message-ID: Subject: Re: [edk2-devel] [PATCH v7 3/5] MdePkg: Implement RISC-V Cache Management Operations To: devel@edk2.groups.io, dhaval@rivosinc.com Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Sunil V L , Daniel Schaefer , Laszlo Ersek Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,pedro.falcato@gmail.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=d2kTE1tU; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=gmail.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Sun, Oct 29, 2023 at 2:46=E2=80=AFPM Dhaval Sharma = wrote: > > Implement Cache Management Operations (CMO) defined by > RISC-V spec https://github.com/riscv/riscv-CMOs. > > Notes: > 1. CMO only supports block based Operations. Meaning cache > flush/invd/clean Operations are not available for the entire > range. In that case we fallback on fence.i instructions. > 2. Operations are implemented using Opcodes to make them compiler > independent. binutils 2.39+ compilers support CMO instructions. > > Test: > 1. Ensured correct instructions are refelecting in asm nit: reflecting > 2. Not able to verify actual instruction in HW as Qemu ignores > any actual cache operations. Do you have no way to test this in hardware? Since Rivos is a RISCV vendor and all ;) I don't like inviting the idea of merging CPU architectural changes without actually testing them in something resembling real silicon (i.e QEMU KVM is _fine_, QEMU TCG really isn't). --=20 Pedro -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110276): https://edk2.groups.io/g/devel/message/110276 Mute This Topic: https://groups.io/mt/102256466/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-