From: "Pedro Falcato" <pedro.falcato@gmail.com>
To: devel@edk2.groups.io, sunilvl@ventanamicro.com
Cc: Tuan Phan <tphan@ventanamicro.com>,
ray.ni@intel.com, michael.d.kinney@intel.com,
gaoliming@byosoft.com.cn, zhiguang.liu@intel.com,
git@danielschaefer.me, andrei.warkentin@intel.com,
ardb+tianocore@kernel.org, eric.dong@intel.com,
kraxel@redhat.com, rahul1.kumar@intel.com,
Dhaval Sharma <dhaval@rivosinc.com>
Subject: Re: [edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Date: Thu, 12 Oct 2023 19:29:59 +0100 [thread overview]
Message-ID: <CAKbZUD38yBg0MvVTMWkjnFBW2D9pZtafgzgNon9W1fKUUFK+cg@mail.gmail.com> (raw)
In-Reply-To: <ZSfinNFjpZfTjuIF@sunil-laptop>
On Thu, Oct 12, 2023 at 1:12 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> Hi Ray,
>
> On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> > Introduce a PCD to control the maximum SATP mode that MMU allowed
> > to use. This PCD helps RISC-V platform set bare or minimum SATP mode
> > during bring up to debug memory map issue.
> >
> Could you help with review of this?
It seems glaring to me that Maintainers.txt needs some sort of
RISCV
F: */*RiscV*/
pattern for riscv architectural changes across all packages - I'm not
sure how much value the x86 Intel folks can add to RISCV or ARM code
review and merging, apart from the traditional UEFI/tianocore
feedback.
--
Pedro
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next prev parent reply other threads:[~2023-10-12 18:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-04 18:34 [edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode Tuan Phan
2023-10-05 4:14 ` Sunil V L
2023-10-12 12:12 ` Sunil V L
2023-10-12 18:29 ` Pedro Falcato [this message]
2023-10-13 3:50 ` Sunil V L
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