[edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

[edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

[Tuan Phan]

Introduce a PCD to control the maximum SATP mode that MMU allowed
to use. This PCD helps RISC-V platform set bare or minimum SATP mode
during bring up to debug memory map issue.

Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com>
---
Changes:
V2
- Changed default mode to SV57 

 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c   | 6 +++++-
 UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
 UefiCpuPkg/UefiCpuPkg.dec                              | 8 ++++++++
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
index 9cca5fc128af..826a1d32a1d4 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
@@ -36,7 +36,7 @@
 #define PTE_PPN_SHIFT         10
 #define RISCV_MMU_PAGE_SHIFT  12
 
-STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 };
+STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
 STATIC UINTN  mMaxRootTableLevel;
 STATIC UINTN  mBitPerLevel;
 STATIC UINTN  mTableEntryCount;
@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode  (
   UINTN                            Index;
   EFI_STATUS                       Status;
 
+  if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
+    return EFI_DEVICE_ERROR;
+  }
+
   switch (SatpMode) {
     case SATP_MODE_OFF:
       return EFI_SUCCESS;
diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
index 9b28a98cb346..51ebe1750e97 100644
--- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
+++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
@@ -25,3 +25,6 @@
 
 [LibraryClasses]
   BaseLib
+
+[Pcd]
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 68473fc640e6..0b5431dbf70a 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -396,6 +396,14 @@
   # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
   gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
 
+[PcdsFixedAtBuild.RISCV64]
+  ## Indicate the maximum SATP mode allowed.
+  #  0 - Bare mode.
+  #  8 - 39bit mode.
+  #  9 - 48bit mode.
+  #  10 - 57bit mode.
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021
+
 [PcdsDynamic, PcdsDynamicEx]
   ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
   # @Prompt The pointer to a CPU S3 data buffer.
-- 
2.25.1



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Re: [edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

[Sunil V L]

On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> Introduce a PCD to control the maximum SATP mode that MMU allowed
> to use. This PCD helps RISC-V platform set bare or minimum SATP mode
> during bring up to debug memory map issue.
> 
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com>
> ---
> Changes:
> V2
> - Changed default mode to SV57 
> 
>  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c   | 6 +++++-
>  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
>  UefiCpuPkg/UefiCpuPkg.dec                              | 8 ++++++++
>  3 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
>  #define PTE_PPN_SHIFT         10
>  #define RISCV_MMU_PAGE_SHIFT  12
>  
> -STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 };
> +STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
>  STATIC UINTN  mMaxRootTableLevel;
>  STATIC UINTN  mBitPerLevel;
>  STATIC UINTN  mTableEntryCount;
> @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode  (
>    UINTN                            Index;
>    EFI_STATUS                       Status;
>  
> +  if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
> +    return EFI_DEVICE_ERROR;
> +  }
> +
>    switch (SatpMode) {
>      case SATP_MODE_OFF:
>        return EFI_SUCCESS;
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
>  
>  [LibraryClasses]
>    BaseLib
> +
> +[Pcd]
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
> diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..0b5431dbf70a 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
>    # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
>    gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
>  
> +[PcdsFixedAtBuild.RISCV64]
> +  ## Indicate the maximum SATP mode allowed.
> +  #  0 - Bare mode.
> +  #  8 - 39bit mode.
> +  #  9 - 48bit mode.
> +  #  10 - 57bit mode.
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021
> +
LGTM. Thanks!

Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>

>  [PcdsDynamic, PcdsDynamicEx]
>    ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
>    # @Prompt The pointer to a CPU S3 data buffer.
> -- 
> 2.25.1
> 


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Re: [edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

[Sunil V L]

Hi Ray,

On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> Introduce a PCD to control the maximum SATP mode that MMU allowed
> to use. This PCD helps RISC-V platform set bare or minimum SATP mode
> during bring up to debug memory map issue.
> 
Could you help with review of this?

Thanks,
Sunil
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com>
> ---
> Changes:
> V2
> - Changed default mode to SV57 
> 
>  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c   | 6 +++++-
>  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
>  UefiCpuPkg/UefiCpuPkg.dec                              | 8 ++++++++
>  3 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
>  #define PTE_PPN_SHIFT         10
>  #define RISCV_MMU_PAGE_SHIFT  12
>  
> -STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 };
> +STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
>  STATIC UINTN  mMaxRootTableLevel;
>  STATIC UINTN  mBitPerLevel;
>  STATIC UINTN  mTableEntryCount;
> @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode  (
>    UINTN                            Index;
>    EFI_STATUS                       Status;
>  
> +  if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
> +    return EFI_DEVICE_ERROR;
> +  }
> +
>    switch (SatpMode) {
>      case SATP_MODE_OFF:
>        return EFI_SUCCESS;
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
>  
>  [LibraryClasses]
>    BaseLib
> +
> +[Pcd]
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
> diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..0b5431dbf70a 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
>    # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
>    gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
>  
> +[PcdsFixedAtBuild.RISCV64]
> +  ## Indicate the maximum SATP mode allowed.
> +  #  0 - Bare mode.
> +  #  8 - 39bit mode.
> +  #  9 - 48bit mode.
> +  #  10 - 57bit mode.
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021
> +
>  [PcdsDynamic, PcdsDynamicEx]
>    ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
>    # @Prompt The pointer to a CPU S3 data buffer.
> -- 
> 2.25.1
> 


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Re: [edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

[Pedro Falcato]

On Thu, Oct 12, 2023 at 1:12 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
>
> Hi Ray,
>
> On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> > Introduce a PCD to control the maximum SATP mode that MMU allowed
> > to use. This PCD helps RISC-V platform set bare or minimum SATP mode
> > during bring up to debug memory map issue.
> >
> Could you help with review of this?

It seems glaring to me that Maintainers.txt needs some sort of

RISCV
F: */*RiscV*/

pattern for riscv architectural changes across all packages - I'm not
sure how much value the x86 Intel folks can add to RISCV or ARM code
review and merging, apart from the traditional UEFI/tianocore
feedback.

-- 
Pedro


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Re: [edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode

[Sunil V L]

On Thu, Oct 12, 2023 at 07:29:59PM +0100, Pedro Falcato wrote:
> On Thu, Oct 12, 2023 at 1:12 PM Sunil V L <sunilvl@ventanamicro.com> wrote:
> >
> > Hi Ray,
> >
> > On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote:
> > > Introduce a PCD to control the maximum SATP mode that MMU allowed
> > > to use. This PCD helps RISC-V platform set bare or minimum SATP mode
> > > during bring up to debug memory map issue.
> > >
> > Could you help with review of this?
> 
> It seems glaring to me that Maintainers.txt needs some sort of
> 
> RISCV
> F: */*RiscV*/
> 
> pattern for riscv architectural changes across all packages - I'm not
> sure how much value the x86 Intel folks can add to RISCV or ARM code
> review and merging, apart from the traditional UEFI/tianocore
> feedback.
> 
I agree. For RISC-V only changes, I don't bother the PKG maintainers.
But like in this case, UefiCpuPkg.dec is modified, I think it is my duty
to make sure PKG maintainers are notified and sufficient time given for
them to ACK. I consider "no response" after few days as "no objection" and
merge the changes.

Thanks,
Sunil


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