Description according to Chapter 7.5.2 of USB 3.2 spec protocol.
When the Usb state machine is in Inactive, the software is required
to perform a warm reset operation.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Cheng Zhou <zhoucheng@phytium.com.cn>
---
 MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
index c05431ff30ec..938c8e2e28f7 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
@@ -558,6 +558,20 @@ XhcSetRootHubPortFeature (
       State |= XHC_PORTSC_RESET;
       XhcWriteOpReg (Xhc, Offset, State);
       XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
+
+      //
+      // Usb 3.2 spec 7.5.2
+      // When the USB state machine is Inactive state, the device is abnormal.
+      // eSS.Inactive is a state where a link has failed Enhanced SuperSpeed operation.Software
+      // is required for warm reset intervention.This flag only applies to USB3 protocol ports.
+      //
+      State = XhcReadOpReg (Xhc, Offset);
+      if ((((State & 0x1e0) >> 5) == 6) && ((State & 3) == 0)) {
+        State |= 0x80000000;

+        XhcWriteOpReg (Xhc, Offset, State);
+        XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);
+        DEBUG ((DEBUG_INFO, "Warm Reset Successful! \n"));
+      }
       break;

     case EfiUsbPortPower:
--
2.17.1