From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f180.google.com (mail-pg1-f180.google.com [209.85.215.180]) by mx.groups.io with SMTP id smtpd.web08.2011.1667500110937812234 for ; Thu, 03 Nov 2022 11:28:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=b3LGMrfu; spf=pass (domain: gmail.com, ip: 209.85.215.180, mailfrom: pedro.falcato@gmail.com) Received: by mail-pg1-f180.google.com with SMTP id e129so2391880pgc.9 for ; Thu, 03 Nov 2022 11:28:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=P1dYwyEi+CWadOcGp4HIRjZrZWgUuW4TjLaRJ2RVPFA=; b=b3LGMrfu/md42jlF145/8ThU3dUCvvo/XuKn+WcudqV6RZlX8JnyriCxYcO4ViOcPF TrTuHDw4Vb+QIBrRNQg0Xb3XniIo/9Lj6ZNRntJLcoWfdxS44JdOWcm2o2EfdVmygc7Q 3Iil5E2RLgxJ5Uqf+FDZM9soRdEQ0+O3pAoLsR6KJBnsBA6nkXorytfo8JtjTJTzQvXr ETETuYdDex/hfve6RX6R/3iW1IUJaDNQFGIKwPpEG/VZ/BGcxyTa93fZQAVN+IGLz3Ne +cvpWm4NvQwldup5iTl5EMH8RnX36gClI2vI9Bw9xbTmxe73NHT/4nBgU9tmt2MMGujM yoSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=P1dYwyEi+CWadOcGp4HIRjZrZWgUuW4TjLaRJ2RVPFA=; b=puEIDFfI4O5mbk97h5cXYOkXGhABkkOcqdQlzoOqcGbra3qaW9rIURGc8wFad+gbBx 2nItbzjCLUxgfMAi0F6kcjbyVF6QRhy9eUHn7DMtRcw8JSm5Gx+QE4tvILB0xZnFO67n Tz50nC15iCBrDCOEx3Bk2I2/kdc/AukQpsYjU5Ht++PrPGVRIvM3ECnkJ9JNi15H8za0 ff7TvtBg3k0NCMST+KsJjFnJuiUbYVKQVmME1EEEZYEy5Yst/WoGGNytTQNZAMKCSlol hy/lvam27EUBeVw2ZHxpIgdD83c2Bl7APUaHWVXoEKs/jRO9CAi/6ruZ44tUbS7mwoxp yyGw== X-Gm-Message-State: ACrzQf2StjqJFnq5mzp0+YfDSktTwsr9RgfPX8RUnHn9W5BPBscaHdzt frp4N1RRkl86arH62Q91z2LF3VaadS+ZgNw+ctc7dhwTAmIJjA== X-Google-Smtp-Source: AMsMyM4i8O1cEM4xZA8S2whXTeGb7FC9dfdmEwSnR6sEk+QJzoWVbAQ4jkOF/oolhFx6/NSq9AOUDj3+BJhAM+jM76E= X-Received: by 2002:a05:6a00:15c3:b0:56c:e8d0:aaf1 with SMTP id o3-20020a056a0015c300b0056ce8d0aaf1mr31530637pfu.75.1667500109980; Thu, 03 Nov 2022 11:28:29 -0700 (PDT) MIME-Version: 1.0 References: <20221103155315.3764-1-zhoucheng@phytium.com.cn> <20221103155315.3764-2-zhoucheng@phytium.com.cn> In-Reply-To: <20221103155315.3764-2-zhoucheng@phytium.com.cn> From: "Pedro Falcato" Date: Thu, 3 Nov 2022 18:28:18 +0000 Message-ID: Subject: Re: [edk2-devel] [PATCH v1 1/1] MdeModulePkg:Add Warm Reset for Xhc To: devel@edk2.groups.io, zhoucheng@phytium.com.cn Cc: Liming Gao , Hao A Wu , Ray Ni Content-Type: multipart/alternative; boundary="000000000000b7e9ed05ec951fa2" --000000000000b7e9ed05ec951fa2 Content-Type: text/plain; charset="UTF-8" On Thu, Nov 3, 2022 at 3:53 PM zhoucheng wrote: > Description according to Chapter 7.5.2 of USB 3.2 spec protocol. > When the Usb state machine is in Inactive, the software is required > to perform a warm reset operation. > > Cc: Liming Gao > Cc: Hao A Wu > Cc: Ray Ni > Signed-off-by: Cheng Zhou > --- > MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > index c05431ff30ec..938c8e2e28f7 100644 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > @@ -558,6 +558,20 @@ XhcSetRootHubPortFeature ( > State |= XHC_PORTSC_RESET; > XhcWriteOpReg (Xhc, Offset, State); > XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, > XHC_GENERIC_TIMEOUT); > + > + // > + // Usb 3.2 spec 7.5.2 > + // When the USB state machine is Inactive state, the device is > abnormal. > + // eSS.Inactive is a state where a link has failed Enhanced > SuperSpeed operation.Software > + // is required for warm reset intervention.This flag only applies > to USB3 protocol ports. > + // > + State = XhcReadOpReg (Xhc, Offset); > + if ((((State & 0x1e0) >> 5) == 6) && ((State & 3) == 0)) { > + State |= 0x80000000; > Please use defines for all of these magic values, it improves readability so much. > + XhcWriteOpReg (Xhc, Offset, State); > + XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TRUE, > XHC_GENERIC_TIMEOUT); > + DEBUG ((DEBUG_INFO, "Warm Reset Successful! \n")); > + } > break; > > case EfiUsbPortPower: > -- > 2.17.1 > > > > > > > -- Pedro Falcato --000000000000b7e9ed05ec951fa2 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Nov 3, 2022 at 3:53 PM zhouch= eng <zhoucheng@phytium.com.c= n> wrote:
Description according to Chapter 7.5.2 of USB 3.2 spec protocol.
When the Usb state machine is in Inactive, the software is required
to perform a warm reset operation.

Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Hao A Wu <ha= o.a.wu@intel.com>
Cc: Ray Ni <ray.ni= @intel.com>
Signed-off-by: Cheng Zhou <zhoucheng@phytium.com.cn>
---
=C2=A0MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 14 ++++++++++++++
=C2=A01 file changed, 14 insertions(+)

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c b/MdeModulePkg/Bus/Pci/Xhc= iDxe/Xhci.c
index c05431ff30ec..938c8e2e28f7 100644
--- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
@@ -558,6 +558,20 @@ XhcSetRootHubPortFeature (
=C2=A0 =C2=A0 =C2=A0 =C2=A0State |=3D XHC_PORTSC_RESET;
=C2=A0 =C2=A0 =C2=A0 =C2=A0XhcWriteOpReg (Xhc, Offset, State);
=C2=A0 =C2=A0 =C2=A0 =C2=A0XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, TR= UE, XHC_GENERIC_TIMEOUT);
+
+=C2=A0 =C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 =C2=A0 // Usb 3.2 spec 7.5.2
+=C2=A0 =C2=A0 =C2=A0 // When the USB state machine is Inactive state, the = device is abnormal.
+=C2=A0 =C2=A0 =C2=A0 // eSS.Inactive is a state where a link has failed En= hanced SuperSpeed operation.Software
+=C2=A0 =C2=A0 =C2=A0 // is required for warm reset intervention.This flag = only applies to USB3 protocol ports.
+=C2=A0 =C2=A0 =C2=A0 //
+=C2=A0 =C2=A0 =C2=A0 State =3D XhcReadOpReg (Xhc, Offset);
+=C2=A0 =C2=A0 =C2=A0 if ((((State & 0x1e0) >> 5) =3D=3D 6) &= & ((State & 3) =3D=3D 0)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 State |=3D 0x80000000;
Pl= ease use defines for all of these magic values, it improves readability so = much.
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 XhcWriteOpReg (Xhc, Offset, State);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 XhcWaitOpRegBit (Xhc, Offset, XHC_PORTSC_PRC, = TRUE, XHC_GENERIC_TIMEOUT);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 DEBUG ((DEBUG_INFO, "Warm Reset Successfu= l! \n"));
+=C2=A0 =C2=A0 =C2=A0 }
=C2=A0 =C2=A0 =C2=A0 =C2=A0break;

=C2=A0 =C2=A0 =C2=A0case EfiUsbPortPower:
--
2.17.1








--
Pedro Falcato
--000000000000b7e9ed05ec951fa2--