From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::143; helo=mail-it1-x143.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x143.google.com (mail-it1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1CAF921A143EF for ; Fri, 23 Nov 2018 05:20:29 -0800 (PST) Received: by mail-it1-x143.google.com with SMTP id m15so17909012itl.4 for ; Fri, 23 Nov 2018 05:20:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=/eZA/LxtoC5OxB2a8sZwK4l7LlVuqJt/TK8iyny1ClA=; b=cMPMtwkdXshnHqfdig0SP0E6TkS3YZpzfCZ4YbJWdUvSglec5hcIwUm9QEpBJ/VXmV q7KX2gncT96nQJRBM6TpCjh6QPuTMhpAJUaisa4W2bDyIIUkLFDURhBt9Pl4ny8tFJWX ikW/7ZEPoTZa3+N+OI40HhfyDTprKxmSkaHvs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/eZA/LxtoC5OxB2a8sZwK4l7LlVuqJt/TK8iyny1ClA=; b=nXkxs5Ph+n8yeSeAUmyOLGy7mmQ0M/JMqp0/J+3gN1Qk7zULDNzxqXriecDV6Fvm3/ f2lzwrY++kCY217NbCXJMiJTqBXhR+h4FvBmtpp1HoveEgQyRyi/V5vWyuhr/U9Xr+bq dCOSqBZPxSH3hH3Zo9vFpKaIzTfKnJcnLVAka951egjZGZ+2KAKnm5kPTqASGfE0S+6M Fx8kDtiko2IXUgnxVr+UZ3UUf259oXLCJCTOKmEuK2y1n+QGBaVochgk5qwh2dwQT/2U 2ozCbXQdRltU2LbHCSUHNKie/TveRHTPggoyydCCN4PWwqLLG/SDmyJZda0mmvApSAyR gLQQ== X-Gm-Message-State: AA+aEWavZYf9t7iq2bz9IC+Y1cIYp1PFd0/i5KLKpu2LOL1O74X7TX+n qizE7usitOfbWA8PlTFFH5LOpMwWZyzUX1jr4bWEbg== X-Google-Smtp-Source: AFSGD/XPiQiwySNwh2jdVmGWwLaqMnoaalz2EVaIerdGjwj/HSRF2CdofPiFCc5M8C/zGXn0avy0ilzRqcCyKiXRiJE= X-Received: by 2002:a02:4c9:: with SMTP id 192mr12911513jab.2.1542979228722; Fri, 23 Nov 2018 05:20:28 -0800 (PST) MIME-Version: 1.0 References: <20181123121431.22353-1-ard.biesheuvel@linaro.org> <20181123121431.22353-2-ard.biesheuvel@linaro.org> <20181123131631.ionb53xqzlyepaue@hawk.localdomain> In-Reply-To: <20181123131631.ionb53xqzlyepaue@hawk.localdomain> From: Ard Biesheuvel Date: Fri, 23 Nov 2018 14:20:17 +0100 Message-ID: To: Andrew Jones Cc: "edk2-devel@lists.01.org" , Laszlo Ersek , Leif Lindholm , Auger Eric , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Julien Grall Subject: Re: [PATCH 1/5] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 23 Nov 2018 13:20:30 -0000 Content-Type: text/plain; charset="UTF-8" On Fri, 23 Nov 2018 at 14:16, Andrew Jones wrote: > > On Fri, Nov 23, 2018 at 01:14:27PM +0100, Ard Biesheuvel wrote: > > Add a helper function that returns the maximum physical address space > > size as supported by the current CPU. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Ard Biesheuvel > > --- > > ArmPkg/Include/Library/ArmLib.h | 6 ++++++ > > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 16 ++++++++++++++++ > > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ > > 3 files changed, 30 insertions(+) > > > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > > index ffda50e9d767..9a804c15fdb6 100644 > > --- a/ArmPkg/Include/Library/ArmLib.h > > +++ b/ArmPkg/Include/Library/ArmLib.h > > @@ -733,4 +733,10 @@ ArmWriteCntvOff ( > > UINT64 Val > > ); > > > > +UINTN > > +EFIAPI > > +ArmGetPhysicalAddressBits ( > > + VOID > > + ); > > + > > #endif // __ARM_LIB__ > > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > index 1ef2f61f5979..75ab8dade485 100644 > > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > > @@ -196,4 +196,20 @@ ASM_FUNC(ArmWriteSctlr) > > 3:msr sctlr_el3, x0 > > 4:ret > > > > +ASM_FUNC(ArmGetPhysicalAddressBits) > > + mrs x0, id_aa64mmfr0_el1 > > + adr x1, .LPARanges > > + and x0, x0, #7 > > + ldrb w0, [x1, x0] > > + ret > > + > > +// > > +// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the > > +// physical address space support on this CPU: > > +// 0 == 32 bits, 1 == 36 bits, etc etc > > +// 6 and 7 are reserved > > +// > > +.LPARanges: > > + .byte 32, 36, 40, 42, 44, 48, -1, -1 > > Hi Ard, > > One of the things I was wondering is how much it matters what the > firmware's opinion of highest physical address is vs. the guest > kernel. Do they need to match? This patch series implies they do, > or at least that 40-bits won't always be sufficient for firmware. Yes. The size of the GCD space limits how much memory we can report as present to the OS. So it only matters if there is DRAM there. > However, guests using 64k pages running on supporting hardware can > use 52-bits. Considering ArmVirtPkg only uses 4k pages, that's not > an option for it, and that justifies not defining index 6 == 52 in > the above array, but will that also restrict the guest? > At the moment, yes. UEFI support for 52-bit/64k pages is still under discussion, and is presently not supported. > > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > > index f2a517671f0a..f2f3c9a25991 100644 > > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > > @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) > > isb > > bx lr > > > > +ASM_FUNC (ArmGetPhysicalAddressBits) > > + mrc p15, 0, r0, c0, c1, 4 // MMFR0 > > + and r0, r0, #0xf // VMSA [3:0] > > + cmp r0, #5 // >5 implies LPAE support > > + movlt r0, #32 // 32 bits if no LPAE > > + movge r0, #40 // 40 bits if LPAE > > + bx lr > > + > > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > > -- > > 2.17.1 > >