From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=ZLdCoyS9; spf=pass (domain: linaro.org, ip: 209.85.166.66, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-io1-f66.google.com (mail-io1-f66.google.com [209.85.166.66]) by groups.io with SMTP; Mon, 29 Apr 2019 05:06:26 -0700 Received: by mail-io1-f66.google.com with SMTP id m9so2300876iok.7 for ; Mon, 29 Apr 2019 05:06:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ffA3iHOwKQv3h9fNltukGq2ZtGpojMG7JDlpYB2R6PQ=; b=ZLdCoyS91qmn9x2QpQAkyMnlX4kPQPTAZExKidSo1kFiCaJZi3a0cqwWvSNW3x7pg+ 0WTlOcWSBOLvBPb1gYBx3yw4wk2E4QRv+oKQfqUnRGzmUSyCowc9ft/qDtY9kunRl858 Wft5Il4/fFS7KoYLEwub9ZHZSuiHq2Hq2NYMcwHC77n+0KvdmkBFLiDvgTVJqRlvtDNn OVM4gVOgjCpzw4rJY9hZ0RinNwhNYMhBILbxR1Wx7nBbInzfEbBiDKxle9fouH9GfRKD moIXPt/Eo76fFsDK1ZnxSN00LFhOJUxoiY+iY8YbyZePcmkbUN9wr6F8DnryZAl+nFQ+ tb4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ffA3iHOwKQv3h9fNltukGq2ZtGpojMG7JDlpYB2R6PQ=; b=T47/6knq7QBvuzlOfGSjrcGfP1s5K4g1+EnD7jLo1XxdEWm2U4txUimQIu30FuE1n2 FVcRloUXWNoe23bn9eMigSUMnX0+RG7A5n8nPx6r70UlD9SE00Bn+KzJ1hMPTVzGb36e DuJw9eUuYjoLHbMv/EpGwdHG7TO5m5X2jtWkEl6bMrWhTNkjmisAEdUB7ZpU9qbbVZJM Gjk9Ja/xZC3U11knmADGl5Je+CAObVkTNX6h49ak95P8JIev1L6sv2oPdAi2fGDVzkNh ZIp7AJLVuXtCbof/VIzT4ITpet+Ev0dI2sIXNZU4K/RE/ci+jeDNVqmZ+eizLP4x3Cg9 tT7g== X-Gm-Message-State: APjAAAV/d16V7TfBcm1XagkGjsBoDS2D0nolGmD+mu4hInMlrpb02lpn sWOA6zdWXX7wn+moXsE/38lk4Ec5Q6Y15HBo5L7glg== X-Google-Smtp-Source: APXvYqxYyMX19cY09elygQMXdB3Q2gZa9gYwbcXTOQUOkuQhSiuQFJMLhrjkNIp04iVVROeOS0fUjgWGMJCYgrL5A5w= X-Received: by 2002:a5e:8b0d:: with SMTP id g13mr26498494iok.170.1556539585303; Mon, 29 Apr 2019 05:06:25 -0700 (PDT) MIME-Version: 1.0 References: <20190425105127.26429-1-ard.biesheuvel@linaro.org> <20190426105812.gff7q3ybeanh4c2f@bivouac.eciton.net> In-Reply-To: <20190426105812.gff7q3ybeanh4c2f@bivouac.eciton.net> From: "Ard Biesheuvel" Date: Mon, 29 Apr 2019 14:06:13 +0200 Message-ID: Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: add ACPI description of GPIO controller and power button To: Leif Lindholm Cc: edk2-devel-groups-io , Graeme Gregory , Masahisa Kojima Content-Type: text/plain; charset="UTF-8" On Fri, 26 Apr 2019 at 12:58, Leif Lindholm wrote: > > On Thu, Apr 25, 2019 at 12:51:27PM +0200, Ard Biesheuvel wrote: > > Add ACPI descriptions of the GPIO and external interrupt (EXIU) > > controllers as well as the power button. Note that on rev 0.3 > > boards, the power button appears to reset the system (this was > > not the case on rev 0.1 boards), so it is included for reference > > primarily. The same GPIO event mechanism will be used in the future > > for reporting hardware errors to the OS. > > > > Signed-off-by: Ard Biesheuvel > > With a contibuted-under: > Reviewed-by: Leif Lindholm > Thanks, but I'll need to respin this in any case. > > --- > > Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 52 ++++++++++++++++++++ > > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++ > > 2 files changed, 56 insertions(+) > > > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > > index aab4fbf0e6b4..acb77739ded6 100644 > > --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl > > @@ -201,5 +201,57 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "SYNQUACR", > > } > > }) > > } > > + > > + Device (GPIO) { > > + Name (_HID, "SCX0007") > > + Name (_UID, Zero) > > + Name (_CRS, ResourceTemplate () { > > + Memory32Fixed (ReadWrite, SYNQUACER_GPIO_BASE, SYNQUACER_GPIO_SIZE) > > + Memory32Fixed (ReadWrite, SYNQUACER_EXIU_BASE, SYNQUACER_EXIU_SIZE) > > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 144 } > > + }) > > + Name (_DSD, > > + Package () // _DSD: Device-Specific Data > > + { > > + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > > + Package () > > + { > > + Package () { "socionext,spi-base", 112 }, > > + Package () > > + { > > + "gpio-line-names", > > + Package () > > + { > > + "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", > > + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", > > + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", > > + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", > > + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", > > + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", > > + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", > > + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31" > > + } > > + } > > + } > > + } > > + ) > > + Name (_AEI, ResourceTemplate () { > > + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault,, "\\_SB.GPIO") > > + { > > + 0x08 > > + } > > + }) > > + Method (_E08, 0x0, NotSerialized) { > > + Notify (\_SB.PWRB, 0x80) > > + } > > + } > > + > > + Device (PWRB) { > > + Name (_HID, "PNP0C0C") > > + Name (_UID, Zero) > > + Method (_STA, 0x0, NotSerialized) { > > + Return (0xF) > > + } > > + } > > } // Scope (_SB) > > } > > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > > index b0fcc306c1ae..cff981c4f8ae 100644 > > --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > > @@ -42,6 +42,10 @@ > > #define SYNQUACER_GPIO_BASE 0x51000000 > > #define SYNQUACER_GPIO_SIZE SIZE_4KB > > > > +// EXIU interrupt controller > > +#define SYNQUACER_EXIU_BASE 0x510c0000 > > +#define SYNQUACER_EXIU_SIZE 0x20 > > + > > // I2C0 block > > #define SYNQUACER_I2C0_BASE 0x51200000 > > #define SYNQUACER_I2C0_SIZE SIZE_4KB > > -- > > 2.20.1 > >