From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.groups.io with SMTP id smtpd.web12.7700.1574953675193065376 for ; Thu, 28 Nov 2019 07:07:55 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=PeErC7n+; spf=pass (domain: linaro.org, ip: 209.85.221.68, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wr1-f68.google.com with SMTP id y11so28411835wrt.6 for ; Thu, 28 Nov 2019 07:07:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=uz7DmUeCi0WHOUn4SnFhwXA/cn70oc8iQW0AGPMAs/Q=; b=PeErC7n+wqDgVNcxQgXEfjjOim8CrxZN3TYqfXU45n6mqqXBrIlGQTZD+iB+IbM4ZF xKInz4UN5voHLP+sARts3LmaQ4twI4tdxWA8WiiYksxDQyh4NCr8Hq5mzYdqFdHQLrFt QM3RFxeBgReABKXto/fvua5UZcDMLzSjYOFDj+v1+iFqio98RfSKO7N1mMrQy7KRXING 5fHNnqvg44Mo8hS92k5YCx6IVtIUWarioX7rJIvlkbB+AmCq4fg2m64gmijZzsSSCK9n gIs/XhEPPl7duT4LGHtZiDAyZPlnhYtEGVnNbBV2pi4lsu6wzvJw7slCM1mVtB2jctiJ W1sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=uz7DmUeCi0WHOUn4SnFhwXA/cn70oc8iQW0AGPMAs/Q=; b=T6001L7eeR4puF8nomOCGS8jCvN3eoLI08VsF0mlKW3qXGAu9OL0DmLtPtN2/AQEcP n+JIfqrPPvruRPQ139b/bY5PvNso8/CUT52+nBq5yUez4wpM+7FuZCfTLuvg8qHa0GG5 43Xp7XNQrdd1+/5pNFObbxjfy7inwIIn61naJp8l+xBAJZCejeLK2VEoAYcd2ad9y92s FrZMK0w4dLG+g2AXhIsnegEQnn5K3Lz9RRxWZU60iJSNLSr/mZv7kCD1zEmS8UZ0Vi20 dslskG91WVGsQ+yB9prImG6MqGvtxR5W2OzPgd1CNqgkJXbI9mLcxE/hPG2urV0UfhEN FboA== X-Gm-Message-State: APjAAAXi+bUjK15NoP0Pg8VM33EJ53O0kA4u3oj45bEm2juDkf6BYiec 7DyBv2z7E3Jm/+MyFypTEqQbpK+7iUQsCLEzQM1Ozw== X-Google-Smtp-Source: APXvYqwMboPXKoTeyzYAjy4j16s5BC+BaIoyJKNMYye6xYAd2TATKbSn+WnpSYH4Qwq8Q8OJVtgc2Ioceq1ZwuSw6I4= X-Received: by 2002:adf:e6d0:: with SMTP id y16mr24727192wrm.32.1574953673431; Thu, 28 Nov 2019 07:07:53 -0800 (PST) MIME-Version: 1.0 References: <20191127184439.16793-1-ard.biesheuvel@linaro.org> <20191127184439.16793-8-ard.biesheuvel@linaro.org> <20191128133754.GQ7359@bivouac.eciton.net> <20191128134004.GS7359@bivouac.eciton.net> In-Reply-To: <20191128134004.GS7359@bivouac.eciton.net> From: "Ard Biesheuvel" Date: Thu, 28 Nov 2019 16:07:42 +0100 Message-ID: Subject: Re: [PATCH edk2-platforms v2 7/8] Silicon/AMD/StyxDtbLoaderLib: use Cortex-A57 IDs instead of generic ARMv8 To: Leif Lindholm Cc: edk2-devel-groups-io Content-Type: text/plain; charset="UTF-8" On Thu, 28 Nov 2019 at 14:40, Leif Lindholm wrote: > > On Thu, Nov 28, 2019 at 14:39:23 +0100, Ard Biesheuvel wrote: > > On Thu, 28 Nov 2019 at 14:37, Leif Lindholm wrote: > > > > > > On Wed, Nov 27, 2019 at 19:44:38 +0100, Ard Biesheuvel wrote: > > > > Use the more precise Cortex-A57 based compatible strings to describe > > > > the CPUs and the PMUs in the device tree. > > > > > > > > Signed-off-by: Ard Biesheuvel > > > > --- > > > > Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c | 4 ++-- > > > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c > > > > index e723e77c7965..091d151ac722 100644 > > > > --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c > > > > +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c > > > > @@ -405,7 +405,7 @@ PrepareFdt ( > > > > ArmCoreInfoTable[Index].CoreId); > > > > MpId = cpu_to_fdt64 (MpId); > > > > fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId)); > > > > - fdt_setprop_string (Fdt, CpuNode, "compatible", "arm,armv8"); > > > > + fdt_setprop_string (Fdt, CpuNode, "compatible", "arm,cortex-a57"); > > > > fdt_setprop_string (Fdt, CpuNode, "device_type", "cpu"); > > > > > > > > fdt_setprop_cell (Fdt, CpuNode, "i-cache-size", 3 * SIZE_16KB); > > > > @@ -474,7 +474,7 @@ PrepareFdt ( > > > > // Create /pmu node > > > > PmuNode = fdt_add_subnode(Fdt, 0, "pmu"); > > > > if (PmuNode >= 0) { > > > > - fdt_setprop_string (Fdt, PmuNode, "compatible", "arm,armv8-pmuv3"); > > > > + fdt_setprop_string (Fdt, PmuNode, "compatible", "arm,cortex-a57-pmu"); > > > > > > Since we've always only published "arm,armv8-pmuv3" before, is it > > > worth keeping that around as a secondary compatible string rather > > > than replacing it outright? > > > > Yeah, good point. I'll change that. > > Thanks. With that: > Reviewed-by: Leif Lindholm Cheers. For the record, I'll need to apply the following on top: --- a/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c +++ b/Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c @@ -281,6 +281,8 @@ SetXgbeStatus ( } } +STATIC CONST CHAR8 mCpuCompatible[] = "arm,cortex-a57\0arm,armv8"; +STATIC CONST CHAR8 mPmuCompatible[] = "arm,cortex-a57-pmu\0arm,armv8-pmuv3"; STATIC EFI_STATUS @@ -405,7 +407,8 @@ PrepareFdt ( ArmCoreInfoTable[Index].CoreId); MpId = cpu_to_fdt64 (MpId); fdt_setprop (Fdt, CpuNode, "reg", &MpId, sizeof (MpId)); - fdt_setprop_string (Fdt, CpuNode, "compatible", "arm,cortex-a57"); + fdt_setprop (Fdt, CpuNode, "compatible", mCpuCompatible, + sizeof (mCpuCompatible)); fdt_setprop_string (Fdt, CpuNode, "device_type", "cpu"); fdt_setprop_cell (Fdt, CpuNode, "i-cache-size", 3 * SIZE_16KB); @@ -474,7 +477,8 @@ PrepareFdt ( // Create /pmu node PmuNode = fdt_add_subnode(Fdt, 0, "pmu"); if (PmuNode >= 0) { - fdt_setprop_string (Fdt, PmuNode, "compatible", "arm,cortex-a57-pmu"); + fdt_setprop (Fdt, PmuNode, "compatible", mPmuCompatible, + sizeof (mPmuCompatible)); // append PMU interrupts for (Index = 0; Index < ArmCoreCount; Index++) {