From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d41; helo=mail-io1-xd41.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd41.google.com (mail-io1-xd41.google.com [IPv6:2607:f8b0:4864:20::d41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3BDBB211AD343 for ; Sun, 13 Jan 2019 08:36:17 -0800 (PST) Received: by mail-io1-xd41.google.com with SMTP id f4so15901304ion.2 for ; Sun, 13 Jan 2019 08:36:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=WUjSnKvVxxZHtM9BXx1YObzJCtlDqsG4vUPiG8x0frc=; b=Aq5x9X9mbCf3bZXLl1ziuZJJkQwKtkBOedjU4HDyfuq0Irye6QvCNCvUZmefRrGhq1 vMsngWCZuQsOPdm/ZsJPwjKnZ3EcSqsU5cLw6PtNeunaRXKdWkX55ER/Wzidnuhua5Vq ZMdNw8QwZmRJxVhcg24IkQwiNQ2VPD0R1fW8A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=WUjSnKvVxxZHtM9BXx1YObzJCtlDqsG4vUPiG8x0frc=; b=BVjnDc+wXsbhgNJAmo6yVD40IWLzo+bl4csoutUxJGWArAedy1SxZTi6cXao2T6EQZ Y0oiTvzmLAoWrBcSaw9iRyMf89C948vJnoRdGef8TLLQljDrQIcNU4kxu4K/I6i5gdlW g7XS6RQfWsdhJBfeOIzIVjau/YoKxbk5l+0tzSBlWEiXXbAY7n9hxoLddL4pE6cu/2TX En2/dZic6YOQaPxsgGOisdTlmorCal5xTwAwNPyFdASdJ9rxuiJvL7TleHxCkctW1ALs mffpx1ND4Z9nc9CXPVUwmdoA03vAfV5RrT2omMWLVuxduhcxHGrnPVIv7oAy84tLgvOk vUdg== X-Gm-Message-State: AJcUukcGyWrjYQTOl+Nj7LU8AB6O7rRhK/vTtA8u82eNw5O+TOzaeS33 5OS3IOfgrkMO66ToJWSu0B4TmPhNc3T/zqUAy4l7cA== X-Google-Smtp-Source: ALg8bN7bcEDU9Z/+Ijxqa7024K+6WWkstgVysqat4u05CiuIgefB04fVncHlKhti6DVF54rKmcElZg7llFSQ3g3KaJQ= X-Received: by 2002:a5e:c206:: with SMTP id v6mr15044277iop.60.1547397376248; Sun, 13 Jan 2019 08:36:16 -0800 (PST) MIME-Version: 1.0 References: <20190104180432.24480-1-ard.biesheuvel@linaro.org> <20190104180432.24480-2-ard.biesheuvel@linaro.org> <20190111180732.ea3dl7mxw2z4hfgm@bivouac.eciton.net> In-Reply-To: <20190111180732.ea3dl7mxw2z4hfgm@bivouac.eciton.net> From: Ard Biesheuvel Date: Sun, 13 Jan 2019 17:36:04 +0100 Message-ID: To: Leif Lindholm , "Cohen, Eugene" Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH 2/2] ArmPkg/ArmMmuLib ARM: fix thinko in second level page table handling X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 13 Jan 2019 16:36:17 -0000 Content-Type: text/plain; charset="UTF-8" On Fri, 11 Jan 2019 at 19:07, Leif Lindholm wrote: > > On Fri, Jan 04, 2019 at 07:04:32PM +0100, Ard Biesheuvel wrote: > > PopulateLevel2PageTable () is invoked for [parts of] mappings that > > start or end on a non-1 MB aligned address (or both). The size of > > the mapping depends on both the start address modulo 1 MB and the > > length of the mapping, but the logic that calculates this size is > > flawed: subtracting 'start address modulo 1 MB' could result in a > > negative value for the remaining length, which is obviously wrong. > > > > So instead, take either RemainLength, or the rest of the 1 MB > > block, whichever is smaller. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Ard Biesheuvel > > Reviewed-by: Leif Lindholm > Series pushed as e3ad54faa855 ArmPkg/ArmMmuLib ARM: add missing support for non-shareable cached mappings 28ce4cb3590b ArmPkg/ArmMmuLib ARM: fix thinko in second level page table handling (with Eugene's tested-by added to the latter) Thanks > > --- > > ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > > index b237321a8d8b..3b3b20aa9b78 100644 > > --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > > +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > > @@ -294,8 +294,8 @@ FillTranslationTable ( > > PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE; > > RemainLength -= TT_DESCRIPTOR_SECTION_SIZE; > > } else { > > - PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE) - > > - (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE); > > + PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE - > > + (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE)); > > > > // Case: Physical address aligned on the Section Size (1MB) && the length > > // does not fill a section > > -- > > 2.17.1 > >