From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::243; helo=mail-io0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x243.google.com (mail-io0-x243.google.com [IPv6:2607:f8b0:4001:c06::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F0EB721130034 for ; Wed, 20 Jun 2018 09:39:33 -0700 (PDT) Received: by mail-io0-x243.google.com with SMTP id e15-v6so346815iog.1 for ; Wed, 20 Jun 2018 09:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=724RfZJMESc3Rf2Pt27YV1WlEB2vfX9JwdQbTj7hkHc=; b=Jlqlp9UcLyzOV3nArbusaDgeAln1Wm/L5JyK+8iiixq0GFBGrdVv61J1lnluEU8Io7 mjHfflJLd9YD6aPCLknMRooWwriWtSBhrc6RMV8Zn2ekiSEe3e0Pi+MbeVJ39o5nJw7g b2ZGZQV3LHqgqYLkosf0DIXETyMA0/5X6DdPs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=724RfZJMESc3Rf2Pt27YV1WlEB2vfX9JwdQbTj7hkHc=; b=qzjjXCgaT/nX4PQPifZHWs5q2YHlNgpK74VYFskWP6G6PKW2D0xG9VdN0yhMxYUINf GOn55X0/Xfo0IYrvFswGvXSShsL0B884l1E6fnlGGSO8v7YHHrumoM8Lcw4IqMaoyM6T FrNcgBPNJcW22ONShaJK8exwBoyVcDeI+Yry7JYqSjCKpLk0jzlkvBmXG6OxELdDzQj9 1OtX22PjkzqyN9uBNP0NOFQwszL0AEfhHXVfAAP2c5qjqBgJnsNFx76Jz5Oj4E5AC9uQ t8uQzQ8nA3nVg34BnltcldSjFtl5X81crmEc2LfojlFGeWRqhZ/uAUeVSwuG7S4XttDE 1WiQ== X-Gm-Message-State: APt69E2qqJt/1YLq2Tuq9eCP/ythM9a1z9MIYcJBDY+PMrcde/YClvVP qzeBSgkOe6YOLV0E/HdaG+yeNG/opO1u/CBaWRsrRA== X-Google-Smtp-Source: ADUXVKJFGeIusPdNxZXH/ZHJx+59ZQYlNWnaPqD6GePyb0mNB+tIPASn27O3fKpUI9Eb7rGjvSBS9syoGYDZH/YJicI= X-Received: by 2002:a6b:dd0b:: with SMTP id f11-v6mr17468899ioc.173.1529512772788; Wed, 20 Jun 2018 09:39:32 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:bbc7:0:0:0:0:0 with HTTP; Wed, 20 Jun 2018 09:39:31 -0700 (PDT) In-Reply-To: References: <20180416104412.npzwcvl6zlrh426k@bivouac.eciton.net> From: Ard Biesheuvel Date: Wed, 20 Jun 2018 18:39:31 +0200 Message-ID: To: Chris Co Cc: Leif Lindholm , "edk2-devel@lists.01.org" Subject: Re: [PATCH] ArmPkg/ArmMmuLib ARM: fix Mva to use idx instead of table base X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Jun 2018 16:39:34 -0000 Content-Type: text/plain; charset="UTF-8" On 19 June 2018 at 22:52, Chris Co wrote: > Hi, > > Just checking if there is anything needed on my end to get this patch merged in. > Well, the patch looks obviously correct, but I just tested it and it breaks ArmVirtQemu running in 32-bit mode. I will investigate >> -----Original Message----- >> From: Ard Biesheuvel >> Sent: Thursday, April 19, 2018 5:30 AM >> To: Chris Co >> Cc: Leif Lindholm ; edk2-devel@lists.01.org >> Subject: Re: [PATCH] ArmPkg/ArmMmuLib ARM: fix Mva to use idx instead >> of table base >> >> On 16 April 2018 at 21:45, Chris Co wrote: >> > Hi Leif, >> > >> >> -----Original Message----- >> >> From: Leif Lindholm >> >> Sent: Monday, April 16, 2018 3:44 AM >> >> To: Chris Co >> >> Cc: edk2-devel@lists.01.org; Ard Biesheuvel >> >> >> >> Subject: Re: [PATCH] ArmPkg/ArmMmuLib ARM: fix Mva to use idx >> instead >> >> of table base >> >> >> >> On Fri, Apr 13, 2018 at 11:43:27PM +0000, Chris Co wrote: >> >> > Mva address calculation should use the left-shifted current section >> >> > index instead of the left-shifted table base address. >> >> > >> >> > Using the table base address here has the side-effect of >> >> > potentially causing an access violation depending on the base address >> value. >> >> > >> >> > Cc: Leif Lindholm >> >> > Cc: Ard Biesheuvel >> >> > Contributed-under: TianoCore Contribution Agreement 1.1 >> >> > Signed-off-by: Christopher Co >> >> > --- >> >> > ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 2 +- >> >> > 1 file changed, 1 insertion(+), 1 deletion(-) >> >> > >> >> > diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c >> >> > b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c >> >> > index 774a7ccf59..9bf4ba03fd 100644 >> >> > --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c >> >> > +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c >> >> > @@ -716,7 +716,7 @@ UpdateSectionEntries ( >> >> > Descriptor |= EntryValue; >> >> > >> >> > if (CurrentDescriptor != Descriptor) { >> >> > - Mva = (VOID *)(UINTN)(((UINTN)FirstLevelTable) << >> >> TT_DESCRIPTOR_SECTION_BASE_SHIFT); >> >> > + Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << >> >> > + TT_DESCRIPTOR_SECTION_BASE_SHIFT); >> >> >> >> So, this clearly looks like you've found a bug - thanks! >> >> >> >> But I am a little bit confused about the patch - should this not need >> >> to incorporate the descriptor size in some way? >> >> I.e. something like >> >> Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + (i * sizeof(UINTN))) >> >> << TT_DESCRIPTOR_SECTION_BASE_SHIFT); >> >> or >> >> ... &FirstLevelTable[FirstLevelIndex + i] ... >> >> >> >> ? >> >> >> >> Regards, >> >> >> >> Leif >> >> >> > I don't think descriptor size is needed here. >> > >> > My understanding is that Mva is the base address of the current section. >> > >> > FirstLevelidx is derived by the first section's BaseAddress >> 20. >> > The current section index is then (FirstLevelIdx + i), which makes the >> > base address of the current section (FirstLeveLidx + i) << 20. >> > >> >> Indeed. 'Index' is a bit misleading here, given that it is the top level index into >> the entire VA space, and so it is congruent with the virtual base address >> itself. The use of 'FirstLevelTable' in this context is obviously incorrect, given >> that it refers to the [physical] address of the page tables itself, not to the >> virtual region they describe. >> >> Reviewed-by: Ard Biesheuvel