From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d29; helo=mail-io1-xd29.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd29.google.com (mail-io1-xd29.google.com [IPv6:2607:f8b0:4864:20::d29]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6C0E0211435AE for ; Tue, 25 Sep 2018 09:19:19 -0700 (PDT) Received: by mail-io1-xd29.google.com with SMTP id w11-v6so20956073iob.2 for ; Tue, 25 Sep 2018 09:19:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=3tyDTfG3qth55aCaaHa5PGefqx/mB0twu+EAr29fr14=; b=i8QB4x3pCbZWmjKMglMMz6BLX2ACNuyklrQpqV/VMHV4jipdd4DkaqTndZQeFxxgCe OgYbsdtWhKiIJ0oJK0FEjNEs+GjODR7O6d2PTSUERw0PKXVXBXtkF4lRjUrKbgvr9aaT g4DG8UVFdFuFzzNCI27Tt0+sSPbE9B6/a5MK8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=3tyDTfG3qth55aCaaHa5PGefqx/mB0twu+EAr29fr14=; b=V7Mql3juJHLDu3eMQ3cFNvP2POb6nov8Rbu5BRxKwMJmtj95ViphIJ6dOXNI4XzFeq 2Flg/Fuft/rDmuJHMLAjCiK/thhfVCJstbN6Pl0U8ZjY50bHpVbygPmRh99QB+8g4ozC LjuLFg/gBI4DIyFZRqA1PM5FPS2B5s5Rsk+FRrj6lTnV8ocfXFdKNGM4ryhJkIexMG3e 5Di0QcTk038S3TgUZ8xbe0d3H4GXS7kjpXg3VM0tvY7pqE5PfdvIHRoC3x41l0iDxY9y dQ5pRO7AmSDNS94Ah5vzUJYIl0Fm8kAmzGrnWT/SuT42VB4W7CvVDuXfigu/eRejshIj 4QHg== X-Gm-Message-State: ABuFfoiGVWH2d+gDwB8W2Qd83GHdNFMlTNdLx5cI0iO+Jg+MmS9Tz+OX Bf/7NxsJkDd3pfSVRCURKtAdka5ErNaM+u1Q8U/pxA== X-Google-Smtp-Source: ACcGV60lDxV+6vsvUiQPXuDW/b7tHgN+RXEZa2Eak2bxuIzMQAA4mQZLj41swR4vz4dlpwhuk24KAYvzYB/tBOv8T0s= X-Received: by 2002:a6b:3787:: with SMTP id e129-v6mr1683542ioa.60.1537892358755; Tue, 25 Sep 2018 09:19:18 -0700 (PDT) MIME-Version: 1.0 References: <1536631417-39920-1-git-send-email-star.zeng@intel.com> <734D49CCEBEEF84792F5B80ED585239D5BE028B7@SHSMSX104.ccr.corp.intel.com> In-Reply-To: From: Ard Biesheuvel Date: Tue, 25 Sep 2018 18:19:06 +0200 Message-ID: To: Marcin Wojtas Cc: "Zeng, Star" , "edk2-devel@lists.01.org" , Ruiyu Ni , fei1.wang@intel.com, Grzegorz Jaszczyk , Nadav Haklai Subject: Re: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 16:19:20 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 25 Sep 2018 at 17:51, Ard Biesheuvel wr= ote: > > On Tue, 25 Sep 2018 at 17:41, Marcin Wojtas wrote: > > > > Hi Star, Ard > > > > With this patch, my platforms which use NonDiscoverableDevices layer > > for supporting generic Xhci controller, fail in a strange way: > > "Synchronous Exception at 0x000000003F910AFC > > PC 0x00003F910AFC (0x00003F908000+0x00008AFC) [ 0] DxeCore.dll > > PC 0x00003F910AE0 (0x00003F908000+0x00008AE0) [ 0] DxeCore.dll > > PC 0x00003F91BDF4 (0x00003F908000+0x00013DF4) [ 0] DxeCore.dll > > PC 0x0000BF5BD000 (0x0000BF5AF000+0x0000E000) [ 1] XhciDxe.dll > > PC 0xAFAFAFAFAFAFAFAF > > > > Recursive exception occurred while dumping the CPU state" > > > > I've quickly checked and although XhcSetHsee() is eventually called > > from XhcDriverBindingStart() sequence, > > below line is not even executed: > > XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); > > The XhcDriverBindingStart() returns EFI_SUCCESS and we get the sync > > abort right afterwards (haven't found exact place yet). > > > > FYI I am seeing something similar with a Renesas uPD70201. > ... which notably is a PCI device. I need to dig into this further, I'll try to add more context tomorrow. > > What makes the difference is commenting out in XhcSetHsee(): > > // Status =3D PciIo->Pci.Read ( > > // PciIo, > > // EfiPciIoWidthUint16, > > // PCI_COMMAND_OFFSET, > > // sizeof (XhciCmd), > > // &XhciCmd > > // ); > > > > With that everything keeps working as usual. I'd appreciate any hint. > > > > Best regards. > > Marcin > > > > wt., 11 wrz 2018 o 04:30 Ni, Ruiyu napisa=C5=82(a)= : > > > > > > Reviewed-by: Ruiyu Ni > > > > > > Thanks/Ray > > > > > > > -----Original Message----- > > > > From: Zeng, Star > > > > Sent: Tuesday, September 11, 2018 10:04 AM > > > > To: edk2-devel@lists.01.org > > > > Cc: Zeng, Star ; Ni, Ruiyu ; Wang, > > > > Jian J ; Wang, Fei1 > > > > Subject: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable= Bit is > > > > set > > > > > > > > When the HSEE in the USBCMD bit is a '1' and the HSE bit in the USB= STS > > > > register is a '1', the xHC shall assert out-of-band error signaling= to the host > > > > and assert the SERR# pin. > > > > To prevent masking any potential issues with SERR, this patch is to= set > > > > USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bi= t is > > > > set. > > > > > > > > Cc: Ruiyu Ni > > > > Cc: Jian J Wang > > > > Cc: Fei1 Wang > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > > Signed-off-by: Star Zeng > > > > --- > > > > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 41 > > > > ++++++++++++++++++++++++++++++++++ > > > > 1 file changed, 41 insertions(+) > > > > > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > > > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > > > index 5f0736a516b6..89f073e1d83f 100644 > > > > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > > > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > > > @@ -587,6 +587,39 @@ XhcIsSysError ( > > > > } > > > > > > > > /** > > > > + Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# En= able > > > > Bit is set. > > > > + > > > > + The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Co= ntroller > > > > Reset(HCRST). > > > > + This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable B= it is set. > > > > + > > > > + @param Xhc The XHCI Instance. > > > > + > > > > +**/ > > > > +VOID > > > > +XhcSetHsee ( > > > > + IN USB_XHCI_INSTANCE *Xhc > > > > + ) > > > > +{ > > > > + EFI_STATUS Status; > > > > + EFI_PCI_IO_PROTOCOL *PciIo; > > > > + UINT16 XhciCmd; > > > > + > > > > + PciIo =3D Xhc->PciIo; > > > > + Status =3D PciIo->Pci.Read ( > > > > + PciIo, > > > > + EfiPciIoWidthUint16, > > > > + PCI_COMMAND_OFFSET, > > > > + sizeof (XhciCmd), > > > > + &XhciCmd > > > > + ); > > > > + if (!EFI_ERROR (Status)) { > > > > + if ((XhciCmd & EFI_PCI_COMMAND_SERR) !=3D 0) { > > > > + XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); > > > > + } > > > > + } > > > > +} > > > > + > > > > +/** > > > > Reset the XHCI host controller. > > > > > > > > @param Xhc The XHCI Instance. > > > > @@ -628,6 +661,14 @@ XhcResetHC ( > > > > // > > > > gBS->Stall (XHC_1_MILLISECOND); > > > > Status =3D XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, > > > > XHC_USBCMD_RESET, FALSE, Timeout); > > > > + > > > > + if (!EFI_ERROR (Status)) { > > > > + // > > > > + // The USBCMD HSEE Bit will be reset to default 0 by USBCMD = HCRST. > > > > + // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set. > > > > + // > > > > + XhcSetHsee (Xhc); > > > > + } > > > > } > > > > > > > > return Status; > > > > -- > > > > 2.7.0.windows.1 > > > > > > _______________________________________________ > > > edk2-devel mailing list > > > edk2-devel@lists.01.org > > > https://lists.01.org/mailman/listinfo/edk2-devel