From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4845821B0285B for ; Thu, 7 Dec 2017 05:45:15 -0800 (PST) Received: by mail-it0-x241.google.com with SMTP id o130so725797itg.0 for ; Thu, 07 Dec 2017 05:49:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=CNvuNrG2nnGEXipqoFDR+YEMRRIAzpi/9VQAKxnTYVA=; b=ZRlxZX+9b3ZH2uptisJzqQ7ymyVtzYTqPkjmmUYIT9q+mzos4hjxT9OOM+pHnknowL JUvu4yN4TYF4/Oo/3E2VBZgb9Gl0FBfYFiLob2xUyEoDCgQW3HpprClpoxzUUtqBuQUV SxYdD79Eg7io/QtBhsJ43vsLSgk8yEeIQn33Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=CNvuNrG2nnGEXipqoFDR+YEMRRIAzpi/9VQAKxnTYVA=; b=HTN67SB08tE1W0/k8BYfuoaVV7T+S4icuixozufHlap9kiVdWw4PfnKJdBV8EowjUd vLfeboWy4Qr5Ad1nnRHSjxOyphbo4g7Qx99G93k97LjUfnl/OyWgMyFgcD3/41VcMFmy 09lUeJYevoJ21MLSxjFV4k52FGXI5G5pqogE3uSXm3lq7ZveKmknmCia7pXuHOJT7ZSQ f8AubTPyPlFbEAP3uDjWl0OnUmEYXA73HqSQIdvFOp/tIkt/7bRC9HySO/tP9JHR5TND Lo7Ud2pw8aV06gBBzY6yRLsPYT3qivM9Qf8a4S05/5FQJcrFcGZbE9dalunwMzbpryzP sSoQ== X-Gm-Message-State: AKGB3mKAaZOMshMH7lW2EpzE5dxgFj8tRRsPp3fnzmA/uCwoPljBSXwr MrZ6zjUiDNvjaYdEjzlYozmg+A01B91ow/x2LYREaw== X-Google-Smtp-Source: AGs4zMY2vua3BzsE/dDVO2QfBabVxEXgRYMbYf/uXkTIQXimmZGDJrVs65E56xoPhzzEw+08ZOHGcUok4rBkEWiuT9Y= X-Received: by 10.36.145.203 with SMTP id i194mr1364795ite.73.1512654587628; Thu, 07 Dec 2017 05:49:47 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Thu, 7 Dec 2017 05:49:47 -0800 (PST) In-Reply-To: References: <20171130185355.20985-1-ard.biesheuvel@linaro.org> <20171201125719.ffca5swpw5wajlwz@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 7 Dec 2017 13:49:47 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms v2] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Dec 2017 13:45:15 -0000 Content-Type: text/plain; charset="UTF-8" On 1 December 2017 at 17:53, Ard Biesheuvel wrote: > On 1 December 2017 at 12:57, Leif Lindholm wrote: >> On Thu, Nov 30, 2017 at 06:53:55PM +0000, Ard Biesheuvel wrote: >>> As it turns out, it is surprisingly easy to configure both the NETSEC >>> and eMMC devices as cache coherent for DMA, given that they are both >>> behind the same SMMU which is already configured in passthrough mode >>> by the firmware running on the SCP. >>> >>> So update the static SMMU configuration to make memory accesses performed >>> by these devices inner shareable inner/outer writeback cacheable, which >>> makes them cache coherent with the CPUs. >>> >>> Contributed-under: TianoCore Contribution Agreement 1.1 >>> Signed-off-by: Ard Biesheuvel >> >> Looks fine to me: >> Reviewed-by: Leif Lindholm >> (If you want to hold back for Tested-by:s, feel free to.) >> > > Thanks. It actually depends on the patch that adds the EMMC driver > stack, which depends on the SD/MMC override patches for EDK2, so it > needs to wait anyway. Pushed as ce95ec196da05885844afb79bd2570c5cd9f6b27. I have reordered this with the EMMC driver patch, which will simply be DMA coherent from the start (but I kept the DT bit so the EMMC reference in the commit log is still relevant)