From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.groups.io with SMTP id smtpd.web09.2571.1583444469610126503 for ; Thu, 05 Mar 2020 13:41:10 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=LDztMJ+R; spf=pass (domain: linaro.org, ip: 209.85.128.66, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wm1-f66.google.com with SMTP id a132so189502wme.1 for ; Thu, 05 Mar 2020 13:41:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8ssUWJGFFiqYqkrbNWoupxX77G6RcJe6sq6btqKYzGE=; b=LDztMJ+RnKwuD6t0mAeRil3Z+DCT40n3kT8etyqSvMIfCYQxWLW2vyPUY2OAQ43wgG OUxoTlpwnezSK7rePWiYVsGa9TsKR16H9AP96PKOf3yrWlioADZPgxzI/rUQBN4AUM1v oJOOJQ4IFrDc7KWy9I7AGE/gdTGtIFcinxUsHEqsWLLVEVzZ1nfHeAOFowDnzbOCrPzg 4FcAwbUV7u/eto+OqbojquuORcq2gM1GWdU0fjUQU3OSPUhY5mpYFw6EnC0K4tWrSRcQ Y16MV80Ci/U3APWSnUCYr1cWVdnl35td2OQmE5YCtjsGMIGxA40ybwq0MhfnSl9w9e7p a79g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8ssUWJGFFiqYqkrbNWoupxX77G6RcJe6sq6btqKYzGE=; b=JgiO6UlJMu/ovQlBgtm8r13HJ/Q8ZXZDNJHsfwP0/hSKJ+DmGASLC0p7miFwvQIl+p cpkusdR6/CLyKrLR811PIss4Hx3whR2ch6xWUxPdAP4Gck072QBjOeLB5Sv8zxWFRJ19 7ns4oQRJZ8MhbcLRN1tUln4264wUKKoHAI8KM2bPzvGMa3WUMEO6LcwHPs5phyBnyTj2 DdlYvBvgeLHSPASHpufMUfLx+yaRqTy/9VaqfyT6KSh+AbnNh1aQqe/vQnykA1H3wPYv zBg317I3rvTPP75GjtsSP48IhqSHzEJJ/HRmyEncOpJ8TMrwcQ7BBGOmJBjRqsn4GGjN F5sw== X-Gm-Message-State: ANhLgQ0+l9iYmqY6zMR9PwPq5tDdoFEshuq3PCxgn9gqo8srZqDXesal MDt3MYW4e36Vo1jOL/ILDfhL0ysIwWqKEMce5XIuuA== X-Google-Smtp-Source: ADFU+vu7BMLXgAHevl9JRP/1+3hqFNC4qjgddl6scuEtDl7onWPzraaeHUglQfywfYcj5XMo1AFWnrOZ87ZXW+QTyxY= X-Received: by 2002:a05:600c:24b:: with SMTP id 11mr767982wmj.1.1583444468008; Thu, 05 Mar 2020 13:41:08 -0800 (PST) MIME-Version: 1.0 References: <20200304181246.23513-1-ard.biesheuvel@linaro.org> <20200305162946.GA23627@bivouac.eciton.net> In-Reply-To: <20200305162946.GA23627@bivouac.eciton.net> From: "Ard Biesheuvel" Date: Thu, 5 Mar 2020 22:40:57 +0100 Message-ID: Subject: Re: [PATCH v2 0/9] ArmPkg: eradicate and deprecate by set/way cache ops To: Leif Lindholm Cc: edk2-devel-groups-io Content-Type: text/plain; charset="UTF-8" On Thu, 5 Mar 2020 at 17:29, Leif Lindholm wrote: > > On Wed, Mar 04, 2020 at 19:12:37 +0100, Ard Biesheuvel wrote: > > This is a combination of v1 'ArmPkg: eradicate and deprecate by set/way cache > > ops' and v1 'ArmPkg/ArmLib: ASSERT() on misuse of set/way ops' > > > > As it turns out, there were still some instances of set/way ops left in > > the core code, in ArmMmuLib to be precise. > > > > This series fixes ArmMmuLib to perform the appropriate cache invalidation > > when populating page tables with the MMU and caches off, allowing us to > > get rid of the cache clean/disable/enable sequences which are incorrect > > and pointless at the same time. > > > > I have incorporated some ArmLib changes that I posted separately before, > > with the end result being that all uses pf set/way ops are gone from the > > EDK2 core code, and the routines themselves will now ASSERT() when used > > for anything other than managing the caches while the MMU is still off. > > (Note that BeagleBoard in edk2-platforms still relies on this) > > > > Changes since v1[s]: > > - don't deprecate the set/way ops but make the usable before MMU is enabled > > only > > - use a more elaborate sequence for invalidating the page table entries on > > 32-bit ARM, to ensure we are compliant with the nooks and crannies of > > version 7 of the architecture. > > - incorporate patch #1, which was still pending on the list, and is related > > (its PrePeiCore sibling was already reviewed and merged) > > > > Ard Biesheuvel (9): > > ArmPlatformPkg/PrePi: replace set/way cache ops with by-VA ones > > ArmPkg/ArmMmuLib ARM: remove dummy constructor > > ArmPkg/ArmMmuLib ARM: split ArmMmuLibCore.c into core and update code > > ArmPkg/ArmMmuLib ARM: cache-invalidate initial page table entries > > ArmPkg/ArmMmuLib AARCH64: cache-invalidate initial page table entries > > ArmPkg/ArmLib: move set/way helper functions into private header > > ArmPkg/ArmLib: clean up library includes > > ArmPkg/ArmLib: remove bogus protocol declaration > > ArmPkg/ArmLib: ASSERT on set/way cache ops being used with MMU on > > Apart from the minor nit pointed out (which you can fix before > committing) - for the series: > Reviewed-by: Leif Lindholm > Thanks. These are merged now, along with the followup series, and the only vaguely related cleanups for ARM. I did spot one other issue on AArch64 though, so I'll send out another followup patch to address that.