From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::143; helo=mail-it1-x143.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x143.google.com (mail-it1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9BBED21A09130 for ; Mon, 26 Nov 2018 03:46:41 -0800 (PST) Received: by mail-it1-x143.google.com with SMTP id h193so27040783ita.5 for ; Mon, 26 Nov 2018 03:46:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=6Mk2s+o72heUNWoKGN9uo2LbCNFkOgGjGrC5mVEPdyo=; b=MagYM2B3SupdmtpRD7jwO4t5+Oi1DLNXMetbds/LDUtlx0SJTlsRFgDDrspq8HCm9o fT/5aRH5vtgyAgL4jeQl7hfc6jHy3zXmyjh326YQdWrkJftQasrqlc/IGhBGQ3Bgn0oC XzGzuPUjolBh41TVt/yxUsLZQNCCuGmiS0b7Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=6Mk2s+o72heUNWoKGN9uo2LbCNFkOgGjGrC5mVEPdyo=; b=dbxUJnLpFT+GV3qDYRHvpNXSP0/w+OxyQBYk3XBu1LYUJ1/8o9KVYkhzdAsRTAyaI3 JSpB75r0ZldlCMKv4QFZJC1j5+oOUVxrzcMKYJ3DJHpEuU7j5xX2V06qXaYbmTDvNpiQ Tp1x2yT2EkcACfVG/nl9hddlAi6KejOqprUQQ58D9dOQX/QtnFM4n1X2YcoxaQNXa9T6 TwGN74TWp14ZPC8/QkI83y3R0QO2od5sKf+lmfZoy1i8x3qMq+KmBePLSYtos+60RXak mztnd+3w6VeonwkQ4cTx+FScymihWCDJVc3Uo9Nlz2EcQXh/Om9nncgZIM6d6vS26MeU RMdA== X-Gm-Message-State: AA+aEWZeiT36L0YAnQuvOZXmMRy3AftygDYUgIMfzfBUb42f8DAt8hzR uU1CH0bpEkaSjKC1e9e1GBnjx2QRJkxQn67W3Y4esF4g X-Google-Smtp-Source: AFSGD/WyE0F90Wz7JbVmks3VCHalVKo07V9sGhE4NoqYgtYYjCYNaTLfpbocDrpZY+6mdHWstZBkKLzY3OBEW1wO5sk= X-Received: by 2002:a02:4c9:: with SMTP id 192mr23129029jab.2.1543232800756; Mon, 26 Nov 2018 03:46:40 -0800 (PST) MIME-Version: 1.0 References: <20181123121431.22353-1-ard.biesheuvel@linaro.org> <20181123121431.22353-2-ard.biesheuvel@linaro.org> In-Reply-To: <20181123121431.22353-2-ard.biesheuvel@linaro.org> From: Ard Biesheuvel Date: Mon, 26 Nov 2018 12:46:29 +0100 Message-ID: To: "edk2-devel@lists.01.org" Cc: Laszlo Ersek , Leif Lindholm , Auger Eric , Andrew Jones , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Julien Grall Subject: Re: [PATCH 1/5] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Nov 2018 11:46:41 -0000 Content-Type: text/plain; charset="UTF-8" On Fri, 23 Nov 2018 at 13:14, Ard Biesheuvel wrote: > > Add a helper function that returns the maximum physical address space > size as supported by the current CPU. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Include/Library/ArmLib.h | 6 ++++++ > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 16 ++++++++++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ > 3 files changed, 30 insertions(+) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index ffda50e9d767..9a804c15fdb6 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -733,4 +733,10 @@ ArmWriteCntvOff ( > UINT64 Val > ); > > +UINTN > +EFIAPI > +ArmGetPhysicalAddressBits ( > + VOID > + ); > + > #endif // __ARM_LIB__ > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > index 1ef2f61f5979..75ab8dade485 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > @@ -196,4 +196,20 @@ ASM_FUNC(ArmWriteSctlr) > 3:msr sctlr_el3, x0 > 4:ret > > +ASM_FUNC(ArmGetPhysicalAddressBits) > + mrs x0, id_aa64mmfr0_el1 > + adr x1, .LPARanges > + and x0, x0, #7 > + ldrb w0, [x1, x0] > + ret > + > +// > +// Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the > +// physical address space support on this CPU: > +// 0 == 32 bits, 1 == 36 bits, etc etc > +// 6 and 7 are reserved > +// > +.LPARanges: > + .byte 32, 36, 40, 42, 44, 48, -1, -1 > + Note: as Drew pointed out, we want 52 bits included as well in this enumeration. I will fix that up when applying (unless anyone objects) > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > index f2a517671f0a..f2f3c9a25991 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) > isb > bx lr > > +ASM_FUNC (ArmGetPhysicalAddressBits) > + mrc p15, 0, r0, c0, c1, 4 // MMFR0 > + and r0, r0, #0xf // VMSA [3:0] > + cmp r0, #5 // >5 implies LPAE support > + movlt r0, #32 // 32 bits if no LPAE > + movge r0, #40 // 40 bits if LPAE > + bx lr > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > -- > 2.17.1 >