From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::22f; helo=mail-it0-x22f.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x22f.google.com (mail-it0-x22f.google.com [IPv6:2607:f8b0:4001:c0b::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D9AD2034D81B for ; Tue, 7 Nov 2017 03:04:41 -0800 (PST) Received: by mail-it0-x22f.google.com with SMTP id 72so1928605itl.5 for ; Tue, 07 Nov 2017 03:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ePuoTEEz7zHwK+D6p+mgE0sl8dJ1KUn4KOozF/z6UWI=; b=KloA/ndk2DwOLVhHwIwXPN3N4lbIKIVxCE+EHZKzxvgs4Y7L52q/zL//f9dE5fKbEY 210wLM1YNBfeZuJ1nOAOFs6pIiHab1TtKbeQpsYNzMcADO1c1DvvDAFPhPz7U+oBzvP4 72Q53HnneZsDa4oTHqfYWOTsC3nG5bzCS/AQs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ePuoTEEz7zHwK+D6p+mgE0sl8dJ1KUn4KOozF/z6UWI=; b=R+PpSJhbqWxZuiDiBwJ9lyJt38vAQ43ykB+wv9vRMK8/mAKrMzQ18odWY4kF1AiI+m JLxJVfCzgglo2Piwx3dcMQ06Cqhj8Lj0O8zm6ykCFqx45sj8atv14AW/eT2wOXXDDSqf KfyrEqmNx9eYCCHIumoXDBXkYrit3s4NrlXOuzXj4qV4955El343boXBRJ9MqefbEtAZ IpLOmjrIfXSosaRlT1GhLRWm9rM1ApgG01WEThWBjZV9VrZejBswQQhpHHJ2+eeSs/Q/ TokpDO8ouPcihGsnWWgYgz6ptG+kqtEC1jB6hdkGllS4lbzbfPjjkQBlfRJ7KztlgQ9J coWQ== X-Gm-Message-State: AJaThX6W9fgI1lrq/vDHitICu3d7fjsI53CovJBPHnamnu70+8rhJbY4 oLsUipHS/WyvtS4mM5LBKRQxYb2k7uRvhmOLYw0j+w== X-Google-Smtp-Source: ABhQp+Q+q/F7wsamVznini3F9bosBGu9NaSDjLVrCfzHjRUypuNNBcbhkk9ToDTtmLkkjw+iAlsv642XsVQsVzqYqUI= X-Received: by 10.36.210.198 with SMTP id z189mr1530518itf.65.1510052919926; Tue, 07 Nov 2017 03:08:39 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Tue, 7 Nov 2017 03:08:39 -0800 (PST) In-Reply-To: <1510052748-5564-1-git-send-email-heyi.guo@linaro.org> References: <1510052748-5564-1-git-send-email-heyi.guo@linaro.org> From: Ard Biesheuvel Date: Tue, 7 Nov 2017 11:08:39 +0000 Message-ID: To: Heyi Guo Cc: linaro-uefi , "edk2-devel@lists.01.org" , Peicong Li , Leif Lindholm Subject: Re: [RFC] ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHARE X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Nov 2017 11:04:41 -0000 Content-Type: text/plain; charset="UTF-8" On 7 November 2017 at 11:05, Heyi Guo wrote: > From: Peicong Li > > Flash region needs to be set as cacheable (write back) to increase > performance, if PEI is still XIP on flash or DXE FV is decompressed > from flash FV. However some ARM platforms do not support to set flash > as inner shareable since flash is not normal DDR memory and it will > not respond to cache snoop request, which will causes system hang > after MMU is enabled. > > So we need a new ARM memory region attribute WRITE_BACK_NONSHARE for > flash region on these platforms specifically. This attribute will set > the region as write back but not inner shared. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Peicong Li > Signed-off-by: Heyi Guo > Cc: Leif Lindholm > Cc: Ard Biesheuvel > --- > ArmPkg/Include/Library/ArmLib.h | 2 ++ > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 4 ++++ > 2 files changed, 6 insertions(+) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index 24ffe9f..e43e375 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -39,6 +39,8 @@ > typedef enum { > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, > ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, > + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHARE, > + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHARE, > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, > ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK, > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index 8bd1c6f..cc10143 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -35,6 +35,10 @@ ArmMemoryAttributeToPageAttribute ( > ) > { > switch (Attributes) { > + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHARE: > + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHARE: > + return TT_ATTR_INDX_MEMORY_WRITE_BACK; > + > case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: > case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: > return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; > -- > 2.7.2.windows.1 > I'd prefer the name ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE but other than that, this looks sensible to me. Leif?