From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::232; helo=mail-io0-x232.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x232.google.com (mail-io0-x232.google.com [IPv6:2607:f8b0:4001:c06::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BC126222CF1B5 for ; Wed, 10 Jan 2018 01:47:49 -0800 (PST) Received: by mail-io0-x232.google.com with SMTP id z130so21743956ioe.13 for ; Wed, 10 Jan 2018 01:53:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=cYgT/PnVVOY87Er4fj/y2mtGm1FBlZuXWI2MGDne5cU=; b=c6guAX8A6ITgE+sup19SZZD3Ja4SkcUo3Pc21jwyF8WFQbCoTP7qg0poertLQxuUBB GbCY6z/ep/jCSdfUwGWQaYOq7mSG+AjkTIm2dloeECTu45xbsoHg8kvzTqlag8JYXVaS 3IweWCR13LUmGQD3F1/Z7zf8fAKTAz9xHOcwc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=cYgT/PnVVOY87Er4fj/y2mtGm1FBlZuXWI2MGDne5cU=; b=mun6Q8/JeFDNTBVFw3hkyoWhqvVJ0OElnNkViecjAcfVisEVdj/+INJpD9YfBDVpDv scVyE0yLfnR/hUkSDiNfZvwf6LSbopYHhQ33yuK4oFMq2iS+E8d0N3aepekRkwYcFyGf kDEwjSU4kl9UkoWQUMHT3BKuOkuzaz88ARttRnaGqHtxbb+5YdnkZxRvILawC8CmGzhb brq51JWdKfY6o5oEw+krSpb0rCBtinPNz648JWdHU3PlQs1Q1AOLiblgM9KW7ll0+NrF vby1bjgUVKse2dsQCINKDF4YSKcK9TnvUcPoxhL+7SS5ZBgiaHe2L+/vxbipZLMSqi3V q4tA== X-Gm-Message-State: AKwxytfCDWLDZFPY9poTbY12dtJ/suScGF5feAoZQ1+0y1uvMB1fM5v+ 1YjXxHSYH6KVvvDq/DGOem3Ia62M6HtQ5EWbna0dMA== X-Google-Smtp-Source: ACJfBouF1Gseg6lpTr8ICP6J/+MIt4W2onHCf9vLIIWwwz2gdCqPyCZ5hLlonctR2n2vqWDAUjiMqmiO7pQRSOwdjcg= X-Received: by 10.107.135.205 with SMTP id r74mr513736ioi.248.1515577980523; Wed, 10 Jan 2018 01:53:00 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.37.197 with HTTP; Wed, 10 Jan 2018 01:52:48 -0800 (PST) In-Reply-To: References: <1515410208-14559-1-git-send-email-meenakshi.aggarwal@nxp.com> <1515410208-14559-2-git-send-email-meenakshi.aggarwal@nxp.com> <4ea591d7-5218-d174-7fde-90ecf8a76f02@Intel.com> From: Ard Biesheuvel Date: Wed, 10 Jan 2018 09:52:48 +0000 Message-ID: To: Udit Kumar Cc: "Ni, Ruiyu" , Meenakshi Aggarwal , "edk2-devel@lists.01.org" , "Zeng, Star" , "leif.lindholm@linaro.org" Subject: Re: [RFC] SATA : Implemented NXP errata A008402 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 10 Jan 2018 09:47:50 -0000 Content-Type: text/plain; charset="UTF-8" On 10 January 2018 at 09:43, Udit Kumar wrote: > Hi Ruiyu, > >> -----Original Message----- >> > >> > And this change will not impact any other hardware so no one is basically >> impacted by this change. >> >> Your buggy HW only need the value zero. But the addition of PCD exposes >> an interface that can use any size of PRD. >> I am not sure the AtaAtapiPassThru can work if some platform sets the PCD >> value to others than 0 or 3F_FFFFh. > > I don't see someone using this driver will set Pcd randomly, but I agree on this > point other value should be handled. > Error or Assert could be added, if Pcd value is not 0 or 3F_FFFFh. > >> Can you please >> just duplicate the AtaAtapiPassThru in your platform? >> Because the driver is very stable today, not much code sync effort will be >> needed if core version is changed. > > Duplicating is always a possibility :), but When we will push this duplicated driver > (just for one line change) for upstreaming. > will this be acceptable ?? My main concern with this (and with using a PCD) is that the setting affects all SATA controllers in the system, including ones the you stick into a PCIe slot. So I think forking the driver is the only possible solution, but it will not be a one-line change: you need to ensure that you apply the workaround only to the SATA controllers in the SoC. -- Ard.