From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 31F8E22402DFE for ; Wed, 28 Feb 2018 08:12:44 -0800 (PST) Received: by mail-it0-x241.google.com with SMTP id u66so1741329ith.1 for ; Wed, 28 Feb 2018 08:18:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=J0krrYsJ+kf7G3pTgawFzgW81qsf5vI1B4tV/nA/jnY=; b=PQM8sVeYWZEX7mWDhcrOOaH2JfvgjsOYfd6qASKSBYRza03Yvrwa25MJrzGAg2g1eo 0r5uvQI8Mdlie+XRHroX6booalhvNryrkLYpoEVFj/AJx8sIRADCsxBQqMWpDah5RD9l 3wHlQLNquDRDymjAFZfEeNF2G91Gr/+IQlzgQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=J0krrYsJ+kf7G3pTgawFzgW81qsf5vI1B4tV/nA/jnY=; b=Ffo2giCN4DGTbIU94SI7Y6ZIRg4aAVyZ87UnJ+SiHZeZr43GDHwKgvtESoEaac3UPJ z2qBlCXq1F6XjbTmtb1cbGKqnGMxzKrx2LSzHS8VC0VQOsOQgiXsekFTRmA7oJDjD2mC Rt9g4bcgckb3G4TnAHNxyjg/6czpS+x9xPVYUtpTv0or8wDOQh9Nenwu9e/oYPeZSlKa KwWJs/cdREDD9ss3MldghzeER3YjFEnWGVnEm1hnOzHCiNuewOuDIi0DDzfYQ3W6T7j6 TjZUFoMjOgbUZ2Q863V2D2Rz9Zg/ZVXZN/s+rYDjagCWxvKhGHcl69KlZBQcvvPpo0Kt eGrg== X-Gm-Message-State: APf1xPDCnyoHbtaNPYaSEF3az+r9B8q8l2TP8n8Jt+4NC80G7DIWN9Y8 cJ6RNdoKKUUcPylY4HgpmB+n84AF5U8H4QwsM+szvg== X-Google-Smtp-Source: AG47ELtFtZvP0j5gqpLL/rcixIDEuibadZan9lC6Mk2wvA0ltSO/qLfzR4pWGPr5pTRvAGtX+XwQLMUzMNUjfwa1TgI= X-Received: by 10.36.90.5 with SMTP id v5mr21731657ita.138.1519834731008; Wed, 28 Feb 2018 08:18:51 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Wed, 28 Feb 2018 08:18:50 -0800 (PST) In-Reply-To: <20180228161750.4h5fx4yxfocujfob@bivouac.eciton.net> References: <20180227092017.23617-1-ard.biesheuvel@linaro.org> <20180227092017.23617-2-ard.biesheuvel@linaro.org> <20180228161750.4h5fx4yxfocujfob@bivouac.eciton.net> From: Ard Biesheuvel Date: Wed, 28 Feb 2018 16:18:50 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Graeme Gregory , Masahisa Kojima Subject: Re: [PATCH edk2-platforms 1/5] Platform/Socionext/DeveloperBox: fix PCIe slot to B/D/F mapping X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Feb 2018 16:12:44 -0000 Content-Type: text/plain; charset="UTF-8" On 28 February 2018 at 16:17, Leif Lindholm wrote: > On Tue, Feb 27, 2018 at 09:20:13AM +0000, Ard Biesheuvel wrote: >> Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots >> on the DeveloperBox PCB. > > What is the user-observable problem that is addressed by this patch? > That limiting the speed of slot 1 affects slot 2 >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> index ee2357be9a06..2d3d5cd91be0 100644 >> --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h >> @@ -62,7 +62,7 @@ >> >> #define SYNQUACER_PCI_LOCATION(s,b,d) (((s) << 16) | ((b) << 8) | (d)) >> #define SYNQUACER_PCI_SLOT0_LOCATION SYNQUACER_PCI_LOCATION(1, 0, 0) >> -#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) >> -#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) >> +#define SYNQUACER_PCI_SLOT1_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 3) >> +#define SYNQUACER_PCI_SLOT2_LOCATION SYNQUACER_PCI_LOCATION(0, 1, 7) >> >> #endif >> -- >> 2.11.0 >>