* [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: enable Gen2 speed
@ 2017-11-29 18:44 Ard Biesheuvel
2017-11-29 19:12 ` Leif Lindholm
0 siblings, 1 reply; 3+ messages in thread
From: Ard Biesheuvel @ 2017-11-29 18:44 UTC (permalink / raw)
To: edk2-devel, leif.lindholm, daniel.thompson
Cc: masahisa.kojima, methavanitpong.pipat, masami.hiramatsu,
Ard Biesheuvel
As it turns out, getting the PCIe controllers to switch to Gen2 speed
is surprisingly easy. It only involves setting the 'speed change' bit
in the controller at initialization time, after which the hardware
will automatically attempt to switch to Gen2 speed after training at
Gen1 speed has completed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
index 6b42d3e29806..e63b3a4bb23b 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
@@ -113,6 +113,9 @@
#define PROGRAM_INTERFACE 0x0000FF00
#define PROGRAM_INTERFACE_VALUE 0x00
+#define GEN2_CONTROL_OFF 0x80c
+#define DIRECT_SPEED_CHANGE BIT17
+
#define MISC_CONTROL_1_OFF 0x8BC
#define DBI_RO_WR_EN BIT0
@@ -295,6 +298,9 @@ PciInitController (
EFI_PCI_COMMAND_MEMORY_SPACE |
EFI_PCI_COMMAND_BUS_MASTER);
+ // Force link speed change to Gen2 at link up
+ MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
+
// Region 0: MMIO32 range
ConfigureWindow (DbiBase, 0,
RootBridge->Mem.Base,
--
2.11.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: enable Gen2 speed
2017-11-29 18:44 [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: enable Gen2 speed Ard Biesheuvel
@ 2017-11-29 19:12 ` Leif Lindholm
2017-11-30 18:49 ` Ard Biesheuvel
0 siblings, 1 reply; 3+ messages in thread
From: Leif Lindholm @ 2017-11-29 19:12 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel, daniel.thompson, masahisa.kojima,
methavanitpong.pipat, masami.hiramatsu
On Wed, Nov 29, 2017 at 06:44:59PM +0000, Ard Biesheuvel wrote:
> As it turns out, getting the PCIe controllers to switch to Gen2 speed
> is surprisingly easy. It only involves setting the 'speed change' bit
> in the controller at initialization time, after which the hardware
> will automatically attempt to switch to Gen2 speed after training at
> Gen1 speed has completed.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Hmm?
Well, that sounds like an improvement.
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
> index 6b42d3e29806..e63b3a4bb23b 100644
> --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
> +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c
> @@ -113,6 +113,9 @@
> #define PROGRAM_INTERFACE 0x0000FF00
> #define PROGRAM_INTERFACE_VALUE 0x00
>
> +#define GEN2_CONTROL_OFF 0x80c
> +#define DIRECT_SPEED_CHANGE BIT17
> +
> #define MISC_CONTROL_1_OFF 0x8BC
> #define DBI_RO_WR_EN BIT0
>
> @@ -295,6 +298,9 @@ PciInitController (
> EFI_PCI_COMMAND_MEMORY_SPACE |
> EFI_PCI_COMMAND_BUS_MASTER);
>
> + // Force link speed change to Gen2 at link up
> + MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
> +
> // Region 0: MMIO32 range
> ConfigureWindow (DbiBase, 0,
> RootBridge->Mem.Base,
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: enable Gen2 speed
2017-11-29 19:12 ` Leif Lindholm
@ 2017-11-30 18:49 ` Ard Biesheuvel
0 siblings, 0 replies; 3+ messages in thread
From: Ard Biesheuvel @ 2017-11-30 18:49 UTC (permalink / raw)
To: Leif Lindholm
Cc: edk2-devel@lists.01.org, Daniel Thompson, masahisa.kojima,
Pipat/メタワニットポン ピパット,
Masami Hiramatsu
On 29 November 2017 at 19:12, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Wed, Nov 29, 2017 at 06:44:59PM +0000, Ard Biesheuvel wrote:
>> As it turns out, getting the PCIe controllers to switch to Gen2 speed
>> is surprisingly easy. It only involves setting the 'speed change' bit
>> in the controller at initialization time, after which the hardware
>> will automatically attempt to switch to Gen2 speed after training at
>> Gen1 speed has completed.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> Hmm?
> Well, that sounds like an improvement.
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
Thanks. Pushed as b490ebc08f2a8c3b95b5fd22f142badc72925358
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-11-29 18:44 [PATCH edk2-platforms] Silicon/SynQuacerPciHostBridgeLib: enable Gen2 speed Ard Biesheuvel
2017-11-29 19:12 ` Leif Lindholm
2017-11-30 18:49 ` Ard Biesheuvel
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