Re: [PATCH edk2-platforms v4 29/34] Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch

[Ard Biesheuvel <ard.biesheuvel@linaro.org>]

On 17 November 2017 at 15:51, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Fri, Nov 10, 2017 at 02:21:22PM +0000, Ard Biesheuvel wrote:
>> Ordinary computers typically have a physical switch or jumper on the
>> board that allows non-volatile settings to be cleared. Let's implement
>> the same using DIP switch #1 on block #3, and clear the EFI variable
>> store if it is set to ON at boot time.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>>  Platform/Socionext/DeveloperBox/DeveloperBox.dsc                                        |  4 ++++
>>  Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc                            |  4 ++++
>>  Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf                            |  1 +
>>  Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c   | 25 +++++++++++++++++++-
>>  Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf |  6 +++++
>>  Silicon/Socionext/SynQuacer/SynQuacer.dec                                               |  2 ++
>>  6 files changed, 41 insertions(+), 1 deletion(-)
>>
>> diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
>> index 10d070773cdc..af978db2c034 100644
>> --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
>> +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
>> @@ -381,6 +381,9 @@ [PcdsFixedAtBuild.common]
>>    gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO
>>    gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
>>
>> +  # set DIP switch DSW3-PIN1 to clear the varstore
>> +  gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0
>
> Just one question - how does 0 end up being pin 1 on block 3?
>

Blocks 1 and 2 are not connected to GPIOs at all, but to other SoC
PINs for boot mode, debug, etc.