From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9CB5521B00DC1 for ; Fri, 17 Nov 2017 07:48:51 -0800 (PST) Received: by mail-it0-x241.google.com with SMTP id m191so4554454itg.2 for ; Fri, 17 Nov 2017 07:53:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=97kdDNndBV/SeiVuSzTEufIZPeCnnC0lNAXKlagFSeQ=; b=WMS9jjtDSa9/AYE6P2SVp7JLfhgAHzyMkyUxnDyu90A786U4cac8BV4R1fPtVUUbNN 45ySpfP0zFCYKVkc+SEu+qg9upKVdcIRA6NsXFPm+LKYidpUp3YuCNqmIM5bR+mlqHB/ NqpjywoCDvnMTji8FJ3XhZEeXzoSrm0G+4Ts8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=97kdDNndBV/SeiVuSzTEufIZPeCnnC0lNAXKlagFSeQ=; b=n1vZzAmgemQPAItCjXNcJdl/Hhj+qabOkedc6mc6r95tK7WVLnzVBGNXmn0G6AWoLk yZka5p71GTe097PHq6qV+MiSamGW+65rKH1U2GTVSsMDkX/GzSH+0b26efiP/ZCzo1pe ExMxsRvIv0MJvT/5ih2mr4Wh2LmIUsApaO7v0ghF6A51v0NJIU48b51nmb8uRDBR/LR9 CViJqtVDNUW6zHhIVmdkqGvWQv9zWIMECAhbYaa/wugx704gYG0TZ0IoXFvTr9dJi26M 2+odmYu1lScaud8kKmKjrc4AgWUWXomHXUcsT5rzJjZGKqAPDbNJZBtc229nysIJYP6P vNAA== X-Gm-Message-State: AJaThX4yRvIhgKUGO44R3rSik2a9YA/ulje2/fnz60ncTQjnQFNLCwx8 6uhmvH8bdD2MbNEaIe3AhG60peZj8f7v7LaLEmvXtQ== X-Google-Smtp-Source: AGs4zMZeFTxE++nScEv00p+UAaWjGAO1s+cUH4ckCQZtzHhPzuV6yol1wuNoNQeMnBjFUaNoxT36iyCKwwKNKxNSOtQ= X-Received: by 10.36.31.212 with SMTP id d203mr6879790itd.48.1510933981626; Fri, 17 Nov 2017 07:53:01 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.3 with HTTP; Fri, 17 Nov 2017 07:53:01 -0800 (PST) In-Reply-To: <20171117155143.7xfr6et7fyti3p2k@bivouac.eciton.net> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> <20171110142127.12018-30-ard.biesheuvel@linaro.org> <20171117155143.7xfr6et7fyti3p2k@bivouac.eciton.net> From: Ard Biesheuvel Date: Fri, 17 Nov 2017 15:53:01 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Daniel Thompson , Masami Hiramatsu , =?UTF-8?B?UGlwYXQv44Oh44K/44Ov44OL44OD44OI44Od44OzIOODlOODkeODg+ODiA==?= , Masahisa Kojima Subject: Re: [PATCH edk2-platforms v4 29/34] Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 17 Nov 2017 15:48:51 -0000 Content-Type: text/plain; charset="UTF-8" On 17 November 2017 at 15:51, Leif Lindholm wrote: > On Fri, Nov 10, 2017 at 02:21:22PM +0000, Ard Biesheuvel wrote: >> Ordinary computers typically have a physical switch or jumper on the >> board that allows non-volatile settings to be cleared. Let's implement >> the same using DIP switch #1 on block #3, and clear the EFI variable >> store if it is set to ON at boot time. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 4 ++++ >> Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 4 ++++ >> Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 1 + >> Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 25 +++++++++++++++++++- >> Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 6 +++++ >> Silicon/Socionext/SynQuacer/SynQuacer.dec | 2 ++ >> 6 files changed, 41 insertions(+), 1 deletion(-) >> >> diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc >> index 10d070773cdc..af978db2c034 100644 >> --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc >> +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc >> @@ -381,6 +381,9 @@ [PcdsFixedAtBuild.common] >> gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO >> gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1 >> >> + # set DIP switch DSW3-PIN1 to clear the varstore >> + gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0 > > Just one question - how does 0 end up being pin 1 on block 3? > Blocks 1 and 2 are not connected to GPIOs at all, but to other SoC PINs for boot mode, debug, etc.