From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-x22c.google.com (mail-io0-x22c.google.com [IPv6:2607:f8b0:4001:c06::22c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0E76581E44 for ; Wed, 18 Jan 2017 12:56:06 -0800 (PST) Received: by mail-io0-x22c.google.com with SMTP id l66so22127169ioi.1 for ; Wed, 18 Jan 2017 12:56:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=JblmAorPWHr6JIJFb9NObxvHDgYyTO+3bxgPbRHAl0E=; b=OyWhVaLiImEdrTbmuRI8yukBiWdzhHUk4B3M40ROUofEYbyCx+lRIaBuX70soApQ4S nq+11SvmoiYO8qxJ6szbhNvAWJUoHa0eW5YBVt5L7ugdELSaOgwLHn2gnOnLt+uh96uk avHqMNLf6YmeRePz26eV4+I3yjyKYhhfqJrdY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=JblmAorPWHr6JIJFb9NObxvHDgYyTO+3bxgPbRHAl0E=; b=BPdXhtUkdlU5I5h6ytXHdMydcqPgaXsJkH/S67/TKA9NMqRNJ1Qj3AZtnQMtX/MPKm cmjTTJCxiVZvuDpWVvRn1qKBmygQjeQORnGRvYpJH9esRwZkj3PnY1e+n0y5aMRvMSVq cEvh5JBopY9OXvm6ti2iu9rOwys8979ZUW4W/JKm5BzpSimooVzIHphGACWglCWYxfvl 1pUtGxor80teI+MDuQPMEO0gdk2O1QY0b319qTMSJW51d+CVR49Q27+IZfhHYnMvYwqc MZVoXYV/t0S14bnbaB3I+WcRTc2APbS4UE0LUrV8d4NCn/dg9FHy3/PJnMSorWKzJGCW q/lg== X-Gm-Message-State: AIkVDXKjtbAqg5Uh3y6PhvUNUN9myx9dkh8wEhbmpZ8TsLSOilS5ChcV6Vi8gJqMA8DxUAlJZW75wsSSx9yT8KW4 X-Received: by 10.107.12.150 with SMTP id 22mr5207629iom.138.1484772965355; Wed, 18 Jan 2017 12:56:05 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.144.135 with HTTP; Wed, 18 Jan 2017 12:56:04 -0800 (PST) In-Reply-To: <1484771046-21296-1-git-send-email-achin.gupta@arm.com> References: <1484771046-21296-1-git-send-email-achin.gupta@arm.com> From: Ard Biesheuvel Date: Wed, 18 Jan 2017 20:56:04 +0000 Message-ID: To: Achin Gupta Cc: "edk2-devel@lists.01.org" , Leif Lindholm , nd@arm.com Subject: Re: [PATCH] ArmPlatformPkg/ArmVExpressPkg: Fix memory attributes for NOR Flash X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2017 20:56:06 -0000 Content-Type: text/plain; charset=UTF-8 On 18 January 2017 at 20:24, wrote: > From: Achin Gupta > > The NOR flash banks were being mapped in the translation tables with the same > memory attributes as RAM in the system. These attributes mark the region as > Normal Memory and could additionally be cacheable or non-cacheable. > > Either type of attributes are unsuitable for NOR Flash since write operations > could be performed on it. Normal Memory does not guarantee ordering of > transactions that Device memory does. So the commands sent to the Flash device > may not arrive in the right order unless barriers are used. Commands might not > get past the CPU caches in case the region has been mapped with cacheable > attributes. > > This patch fixes the problem by mapping the NOR Flash memory region with Device > memory attributes. > Device attributes should imply NX, which means we can no longer execute from the NOR flash > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Achin Gupta > --- > ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > index 14c7e8e..2685114 100644 > --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > @@ -116,7 +116,7 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; > VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; > VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ; > - VirtualMemoryTable[Index].Attributes = CacheAttributes; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > // SMB CS2 - SRAM > VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE; > -- > 1.9.1 >