From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x233.google.com (mail-it0-x233.google.com [IPv6:2607:f8b0:4001:c0b::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 35CBA2095A6A6 for ; Tue, 4 Jul 2017 09:01:02 -0700 (PDT) Received: by mail-it0-x233.google.com with SMTP id m68so103086389ith.1 for ; Tue, 04 Jul 2017 09:02:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=LIXjQa+G3PV5KM9V4vKIpxQUVc0PV9CD1ZgTq212XfQ=; b=hCirG56DN7kL4AFEL0juAH9YpznSLAv39ttlnX/4n1MH27B2vbsSOoc9VaVw6A7MiK adehHNmD6GVc88j2fgEMVEO+aA1U3qh1aWFa6pZ28rpQvQYCQu3qzrO2FdnTqeB52dq0 3NjbbpNDslwnrVy3chzja1Z4cQl7WfPlsDr4E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=LIXjQa+G3PV5KM9V4vKIpxQUVc0PV9CD1ZgTq212XfQ=; b=hXYg5mC1/TW4A11hmFdPyIXxyZObAdiejg56VZ1+DLO5piRzAUFNOqHZE/epnbPgk9 l+U747Vn+xnXHjsyaVFZR/ImIz5ipHYGyNWsOQQUwgnPW6B2VxniW7zww06hm2zOo9xr ld6Q683IuISNfYMOY2xuda2xwTZwyNJ4Ze7ArSOYQRTHm41FSQXHBU6AI40FKj57EUoe 97UjJNUd8y5P5WNQTRqdhHbj4VEKJ9cv7pMdLJxBF7TD/jpy3xB843oCknwa2/czWiso NXM7gZDd3i88JdJ2H/y/AdaM0Sb0p8+V2v/MkdQnhRvU5kP1XSq7n079lJWInTYzCUMr Pe6A== X-Gm-Message-State: AKS2vOw6AOhZHmTMpw8KZx/oeMDWMKV84QCr3V4oRcJlNmjiHeVehMB9 OV2H0mq0A+i5jek8avAQHZ7aLhFsFGfb X-Received: by 10.36.46.134 with SMTP id i128mr37815822ita.98.1499184159970; Tue, 04 Jul 2017 09:02:39 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.134.134 with HTTP; Tue, 4 Jul 2017 09:02:39 -0700 (PDT) In-Reply-To: <20170704153844.GQ26676@bivouac.eciton.net> References: <1499174653-330-1-git-send-email-mw@semihalf.com> <1499174653-330-11-git-send-email-mw@semihalf.com> <20170704153844.GQ26676@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 4 Jul 2017 17:02:39 +0100 Message-ID: To: Leif Lindholm Cc: Marcin Wojtas , "edk2-devel@lists.01.org" , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , jinghua@marvell.com Subject: Re: [platforms: PATCH 10/10] Platform/Marvell: ComPhyLib: Add support for SATA ports on CP110 slave X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 16:01:02 -0000 Content-Type: text/plain; charset="UTF-8" On 4 July 2017 at 16:38, Leif Lindholm wrote: > On Tue, Jul 04, 2017 at 03:24:13PM +0200, Marcin Wojtas wrote: >> From: Ard Biesheuvel >> >> Add support for PHY_TYPE_SATA2 and PHY_TYPE_SATA3, which map to the >> SATA ports on the second CP110's AHCI controller. >> >> While at it, add a missing newline in the debug output to make it more >> legible. > > Now now, one logical change per patch please. > >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Ard Biesheuvel >> Signed-off-by: Marcin Wojtas >> --- >> Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 20 +++++++++++--------- >> 1 file changed, 11 insertions(+), 9 deletions(-) >> >> diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c >> index de35265..5180060 100755 >> --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c >> +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c >> @@ -54,21 +54,23 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; >> */ >> COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { >> /* Lane 0 */ >> - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4}}}, >> + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4}, >> + {COMPHY_TYPE_SATA3, 0x4}}}, >> /* Lane 1 */ >> - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}}, >> + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4}, >> + {COMPHY_TYPE_SATA2, 0x4}}}, >> /* Lane 2 */ >> {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_TYPE_RXAUI0, 0x1}, >> - {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}}, >> + {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}}, >> /* Lane 3 */ >> - {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2}, >> - {COMPHY_TYPE_SATA1, 0x4}}}, >> + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2}, >> + {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}}, >> /* Lane 4 */ >> - {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2}, >> + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2}, >> {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}}, >> /* Lane 5 */ >> - {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2}, >> - {COMPHY_TYPE_SATA1, 0x4}}}, >> + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2}, >> + {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}}, >> }; >> >> COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = { >> @@ -1840,7 +1842,7 @@ ComPhyCp110Init ( >> break; >> } >> if (EFI_ERROR(Status)) { >> - DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x", Lane, Status)); >> + DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x\n", Lane, Status)); > > Please drop this hunk. Submit it separately if you care enough. > Yeah, that's my bad. It was in my patch, which I never intended to propose as-is.